Microchip Technology Inc. ATSAME70N19A 2024.06.03 ATSAME70N19A false ACC Analog Comparator Controller ACC 0x0 0x0 0x4000 registers n ACC 33 ACR Analog Control Register 0x94 32 read-write n 0x0 0x0 HYST Hysteresis Selection 1 2 ISEL Current Selection 0 1 ISELSelect LOPW Low-power option. 0 HISP High-speed option. 1 CR Control Register 0x0 32 write-only n 0x0 0x0 SWRST Software Reset 0 1 IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 CE Comparison Edge 0 1 IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 CE Comparison Edge 0 1 IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 CE Comparison Edge 0 1 ISR Interrupt Status Register 0x30 32 read-only n 0x0 0x0 CE Comparison Edge (cleared on read) 0 1 MASK Flag Mask 31 1 SCO Synchronized Comparator Output 1 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 ACEN Analog Comparator Enable 8 1 ACENSelect DIS Analog comparator disabled. 0 EN Analog comparator enabled. 1 EDGETYP Edge Type 9 2 EDGETYPSelect RISING Only rising edge of comparator output 0 FALLING Falling edge of comparator output 1 ANY Any edge of comparator output 2 FE Fault Enable 14 1 FESelect DIS The FAULT output is tied to 0. 0 EN The FAULT output is driven by the signal defined by SELFS. 1 INV Invert Comparator Output 12 1 INVSelect DIS Analog comparator output is directly processed. 0 EN Analog comparator output is inverted prior to being processed. 1 SELFS Selection Of Fault Source 13 1 SELFSSelect CE The CE flag is used to drive the FAULT output. 0 OUTPUT The output of the analog comparator flag is used to drive the FAULT output. 1 SELMINUS Selection for Minus Comparator Input 0 3 SELMINUSSelect TS Select TS 0 VREFP Select VREFP 1 DAC0 Select DAC0 2 DAC1 Select DAC1 3 AFE0_AD0 Select AFE0_AD0 4 AFE0_AD1 Select AFE0_AD1 5 AFE0_AD2 Select AFE0_AD2 6 AFE0_AD3 Select AFE0_AD3 7 SELPLUS Selection For Plus Comparator Input 4 3 SELPLUSSelect AFE0_AD0 Select AFE0_AD0 0 AFE0_AD1 Select AFE0_AD1 1 AFE0_AD2 Select AFE0_AD2 2 AFE0_AD3 Select AFE0_AD3 3 AFE0_AD4 Select AFE0_AD4 4 AFE0_AD5 Select AFE0_AD5 5 AFE1_AD0 Select AFE1_AD0 6 AFE1_AD1 Select AFE1_AD1 7 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 4277059 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 AES Advanced Encryption Standard AES 0x0 0x0 0x4000 registers n AES 56 AADLENR Additional Authenticated Data Length Register 0x70 32 read-write n 0x0 0x0 AADLEN Additional Authenticated Data Length 0 32 CLENR Plaintext/Ciphertext Length Register 0x74 32 read-write n 0x0 0x0 CLEN Plaintext/Ciphertext Length 0 32 CR Control Register 0x0 32 write-only n 0x0 0x0 START Start Processing 0 1 SWRST Software Reset 8 1 CTRR GCM Encryption Counter Value Register 0x98 32 read-only n 0x0 0x0 CTR GCM Encryption Counter 0 32 GCMHR0 GCM H Word Register 0x9C 32 read-write n H GCM H Word x 0 32 read-write GCMHR1 GCM H Word Register 0xA0 32 read-write n H GCM H Word x 0 32 read-write GCMHR2 GCM H Word Register 0xA4 32 read-write n H GCM H Word x 0 32 read-write GCMHR3 GCM H Word Register 0xA8 32 read-write n H GCM H Word x 0 32 read-write GCMHR[0] GCM H Word Register 0 0x138 32 read-write n 0x0 0x0 H GCM H Word x 0 32 GCMHR[1] GCM H Word Register 0 0x1D8 32 read-write n 0x0 0x0 H GCM H Word x 0 32 GCMHR[2] GCM H Word Register 0 0x27C 32 read-write n 0x0 0x0 H GCM H Word x 0 32 GCMHR[3] GCM H Word Register 0 0x324 32 read-write n 0x0 0x0 H GCM H Word x 0 32 GHASHR0 GCM Intermediate Hash Word Register 0x78 32 read-write n GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR1 GCM Intermediate Hash Word Register 0x7C 32 read-write n GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR2 GCM Intermediate Hash Word Register 0x80 32 read-write n GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR3 GCM Intermediate Hash Word Register 0x84 32 read-write n GHASH Intermediate GCM Hash Word x 0 32 read-write GHASHR[0] GCM Intermediate Hash Word Register 0 0xF0 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 GHASHR[1] GCM Intermediate Hash Word Register 0 0x16C 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 GHASHR[2] GCM Intermediate Hash Word Register 0 0x1EC 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 GHASHR[3] GCM Intermediate Hash Word Register 0 0x270 32 read-write n 0x0 0x0 GHASH Intermediate GCM Hash Word x 0 32 IDATAR0 Input Data Register 0x40 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR1 Input Data Register 0x44 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR2 Input Data Register 0x48 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR3 Input Data Register 0x4C 32 write-only n IDATA Input Data Word 0 32 write-only IDATAR[0] Input Data Register 0 0x80 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 IDATAR[1] Input Data Register 0 0xC4 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 IDATAR[2] Input Data Register 0 0x10C 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 IDATAR[3] Input Data Register 0 0x158 32 write-only n 0x0 0x0 IDATA Input Data Word 0 32 IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 TAGRDY GCM Tag Ready Interrupt Disable 16 1 URAD Unspecified Register Access Detection Interrupt Disable 8 1 IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 TAGRDY GCM Tag Ready Interrupt Enable 16 1 URAD Unspecified Register Access Detection Interrupt Enable 8 1 IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 TAGRDY GCM Tag Ready Interrupt Mask 16 1 URAD Unspecified Register Access Detection Interrupt Mask 8 1 ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) 0 1 TAGRDY GCM Tag Ready 16 1 URAD Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) 8 1 URAT Unspecified Register Access (cleared by writing SWRST in AES_CR) 12 4 URATSelect IDR_WR_PROCESSING Input Data Register written during the data processing when SMOD = 0x2 mode. 0 ODR_RD_PROCESSING Output Data Register read during the data processing. 1 MR_WR_PROCESSING Mode Register written during the data processing. 2 ODR_RD_SUBKGEN Output Data Register read during the sub-keys generation. 3 MR_WR_SUBKGEN Mode Register written during the sub-keys generation. 4 WOR_RD_ACCESS Write-only register read access. 5 IVR0 Initialization Vector Register 0x60 32 write-only n IV Initialization Vector 0 32 write-only IVR1 Initialization Vector Register 0x64 32 write-only n IV Initialization Vector 0 32 write-only IVR2 Initialization Vector Register 0x68 32 write-only n IV Initialization Vector 0 32 write-only IVR3 Initialization Vector Register 0x6C 32 write-only n IV Initialization Vector 0 32 write-only IVR[0] Initialization Vector Register 0 0xC0 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 IVR[1] Initialization Vector Register 0 0x124 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 IVR[2] Initialization Vector Register 0 0x18C 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 IVR[3] Initialization Vector Register 0 0x1F8 32 write-only n 0x0 0x0 IV Initialization Vector 0 32 KEYWR0 Key Word Register 0x20 32 write-only n KEYW Key Word 0 32 write-only KEYWR1 Key Word Register 0x24 32 write-only n KEYW Key Word 0 32 write-only KEYWR2 Key Word Register 0x28 32 write-only n KEYW Key Word 0 32 write-only KEYWR3 Key Word Register 0x2C 32 write-only n KEYW Key Word 0 32 write-only KEYWR4 Key Word Register 0x30 32 write-only n KEYW Key Word 0 32 write-only KEYWR5 Key Word Register 0x34 32 write-only n KEYW Key Word 0 32 write-only KEYWR6 Key Word Register 0x38 32 write-only n KEYW Key Word 0 32 write-only KEYWR7 Key Word Register 0x3C 32 write-only n KEYW Key Word 0 32 write-only KEYWR[0] Key Word Register 0 0x40 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR[1] Key Word Register 0 0x64 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR[2] Key Word Register 0 0x8C 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR[3] Key Word Register 0 0xB8 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR[4] Key Word Register 0 0xE8 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR[5] Key Word Register 0 0x11C 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR[6] Key Word Register 0 0x154 32 write-only n 0x0 0x0 KEYW Key Word 0 32 KEYWR[7] Key Word Register 0 0x190 32 write-only n 0x0 0x0 KEYW Key Word 0 32 MR Mode Register 0x4 32 read-write n 0x0 0x0 CFBS Cipher Feedback Data Size 16 3 CFBSSelect SIZE_128BIT 128-bit 0 SIZE_64BIT 64-bit 1 SIZE_32BIT 32-bit 2 SIZE_16BIT 16-bit 3 SIZE_8BIT 8-bit 4 CIPHER Processing Mode 0 1 CKEY Countermeasure Key 20 4 CKEYSelect PASSWD This field must be written with 0xE to allow CMTYPx bit configuration changes. Any other values will abort the write operation in CMTYPx bits.Always reads as 0. 14 DUALBUFF Dual Input Buffer 3 1 DUALBUFFSelect INACTIVE AES_IDATARx cannot be written during processing of previous block. 0 ACTIVE AES_IDATARx can be written during processing of previous block when SMOD = 2. It speeds up the overall runtime of large files. 1 GTAGEN GCM Automatic Tag Generation Enable 1 1 KEYSIZE Key Size 10 2 KEYSIZESelect AES128 AES Key Size is 128 bits 0 AES192 AES Key Size is 192 bits 1 AES256 AES Key Size is 256 bits 2 LOD Last Output Data Mode 15 1 OPMOD Operating Mode 12 3 OPMODSelect ECB ECB: Electronic Code Book mode 0 CBC CBC: Cipher Block Chaining mode 1 OFB OFB: Output Feedback mode 2 CFB CFB: Cipher Feedback mode 3 CTR CTR: Counter mode (16-bit internal counter) 4 GCM GCM: Galois/Counter mode 5 PROCDLY Processing Delay 4 4 SMOD Start Mode 8 2 SMODSelect MANUAL_START Manual Mode 0 AUTO_START Auto Mode 1 IDATAR0_START AES_IDATAR0 access only Auto Mode (DMA) 2 ODATAR0 Output Data Register 0x50 32 read-only n ODATA Output Data 0 32 read-only ODATAR1 Output Data Register 0x54 32 read-only n ODATA Output Data 0 32 read-only ODATAR2 Output Data Register 0x58 32 read-only n ODATA Output Data 0 32 read-only ODATAR3 Output Data Register 0x5C 32 read-only n ODATA Output Data 0 32 read-only ODATAR[0] Output Data Register 0 0xA0 32 read-only n 0x0 0x0 ODATA Output Data 0 32 ODATAR[1] Output Data Register 0 0xF4 32 read-only n 0x0 0x0 ODATA Output Data 0 32 ODATAR[2] Output Data Register 0 0x14C 32 read-only n 0x0 0x0 ODATA Output Data 0 32 ODATAR[3] Output Data Register 0 0x1A8 32 read-only n 0x0 0x0 ODATA Output Data 0 32 TAGR0 GCM Authentication Tag Word Register 0x88 32 read-only n TAG GCM Authentication Tag x 0 32 read-only TAGR1 GCM Authentication Tag Word Register 0x8C 32 read-only n TAG GCM Authentication Tag x 0 32 read-only TAGR2 GCM Authentication Tag Word Register 0x90 32 read-only n TAG GCM Authentication Tag x 0 32 read-only TAGR3 GCM Authentication Tag Word Register 0x94 32 read-only n TAG GCM Authentication Tag x 0 32 read-only TAGR[0] GCM Authentication Tag Word Register 0 0x110 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 TAGR[1] GCM Authentication Tag Word Register 0 0x19C 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 TAGR[2] GCM Authentication Tag Word Register 0 0x22C 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 TAGR[3] GCM Authentication Tag Word Register 0 0x2C0 32 read-only n 0x0 0x0 TAG GCM Authentication Tag x 0 32 AFEC0 Analog Front-End Controller 0 AFEC 0x0 0x0 0x4000 registers n AFEC0 29 ACR AFEC Analog Control Register 0x94 32 read-write n 0x0 IBCTL AFE Bias Current Control 8 2 read-write PGA0EN PGA0 Enable 2 1 read-write PGA1EN PGA1 Enable 3 1 read-write AFEC_AFEC_ACR AFEC Analog Control Register 0x94 32 read-write n 0x0 0x0 IBCTL AFE Bias Current Control 8 2 PGA0EN PGA0 Enable 2 1 PGA1EN PGA1 Enable 3 1 AFEC_AFEC_CDR AFEC Channel Data Register 0x68 32 read-only n 0x0 0x0 DATA Converted Data 0 16 AFEC_AFEC_CECR AFEC Channel Error Correction Register 0xD8 32 read-write n 0x0 0x0 ECORR0 Error Correction Enable for channel 0 0 1 ECORR1 Error Correction Enable for channel 1 1 1 ECORR10 Error Correction Enable for channel 10 10 1 ECORR11 Error Correction Enable for channel 11 11 1 ECORR2 Error Correction Enable for channel 2 2 1 ECORR3 Error Correction Enable for channel 3 3 1 ECORR4 Error Correction Enable for channel 4 4 1 ECORR5 Error Correction Enable for channel 5 5 1 ECORR6 Error Correction Enable for channel 6 6 1 ECORR7 Error Correction Enable for channel 7 7 1 ECORR8 Error Correction Enable for channel 8 8 1 ECORR9 Error Correction Enable for channel 9 9 1 AFEC_AFEC_CGR AFEC Channel Gain Register 0x54 32 read-write n 0x0 0x0 GAIN0 Gain for Channel 0 0 2 GAIN1 Gain for Channel 1 2 2 GAIN10 Gain for Channel 10 20 2 GAIN11 Gain for Channel 11 22 2 GAIN2 Gain for Channel 2 4 2 GAIN3 Gain for Channel 3 6 2 GAIN4 Gain for Channel 4 8 2 GAIN5 Gain for Channel 5 10 2 GAIN6 Gain for Channel 6 12 2 GAIN7 Gain for Channel 7 14 2 GAIN8 Gain for Channel 8 16 2 GAIN9 Gain for Channel 9 18 2 AFEC_AFEC_CHDR AFEC Channel Disable Register 0x18 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 CH1 Channel 1 Disable 1 1 CH10 Channel 10 Disable 10 1 CH11 Channel 11 Disable 11 1 CH2 Channel 2 Disable 2 1 CH3 Channel 3 Disable 3 1 CH4 Channel 4 Disable 4 1 CH5 Channel 5 Disable 5 1 CH6 Channel 6 Disable 6 1 CH7 Channel 7 Disable 7 1 CH8 Channel 8 Disable 8 1 CH9 Channel 9 Disable 9 1 AFEC_AFEC_CHER AFEC Channel Enable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 CH1 Channel 1 Enable 1 1 CH10 Channel 10 Enable 10 1 CH11 Channel 11 Enable 11 1 CH2 Channel 2 Enable 2 1 CH3 Channel 3 Enable 3 1 CH4 Channel 4 Enable 4 1 CH5 Channel 5 Enable 5 1 CH6 Channel 6 Enable 6 1 CH7 Channel 7 Enable 7 1 CH8 Channel 8 Enable 8 1 CH9 Channel 9 Enable 9 1 AFEC_AFEC_CHSR AFEC Channel Status Register 0x1C 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 CH1 Channel 1 Status 1 1 CH10 Channel 10 Status 10 1 CH11 Channel 11 Status 11 1 CH2 Channel 2 Status 2 1 CH3 Channel 3 Status 3 1 CH4 Channel 4 Status 4 1 CH5 Channel 5 Status 5 1 CH6 Channel 6 Status 6 1 CH7 Channel 7 Status 7 1 CH8 Channel 8 Status 8 1 CH9 Channel 9 Status 9 1 AFEC_AFEC_COCR AFEC Channel Offset Compensation Register 0x6C 32 read-write n 0x0 0x0 AOFF Analog Offset 0 10 AFEC_AFEC_COSR AFEC Correction Select Register 0xD0 32 read-write n 0x0 0x0 CSEL Sample & Hold unit Correction Select 0 1 AFEC_AFEC_CR AFEC Control Register 0x0 32 write-only n 0x0 0x0 START Start Conversion 1 1 SWRST Software Reset 0 1 AFEC_AFEC_CSELR AFEC Channel Selection Register 0x64 32 read-write n 0x0 0x0 CSEL Channel Selection 0 4 AFEC_AFEC_CVR AFEC Correction Values Register 0xD4 32 read-write n 0x0 0x0 GAINCORR Gain Correction 16 16 OFFSETCORR Offset Correction 0 16 AFEC_AFEC_CWR AFEC Compare Window Register 0x50 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 16 LOWTHRES Low Threshold 0 16 AFEC_AFEC_DIFFR AFEC Channel Differential Register 0x60 32 read-write n 0x0 0x0 DIFF0 Differential inputs for channel 0 0 1 DIFF1 Differential inputs for channel 1 1 1 DIFF10 Differential inputs for channel 10 10 1 DIFF11 Differential inputs for channel 11 11 1 DIFF2 Differential inputs for channel 2 2 1 DIFF3 Differential inputs for channel 3 3 1 DIFF4 Differential inputs for channel 4 4 1 DIFF5 Differential inputs for channel 5 5 1 DIFF6 Differential inputs for channel 6 6 1 DIFF7 Differential inputs for channel 7 7 1 DIFF8 Differential inputs for channel 8 8 1 DIFF9 Differential inputs for channel 9 9 1 AFEC_AFEC_EMR AFEC Extended Mode Register 0x8 32 read-write n 0x0 0x0 CMPALL Compare All Channels 9 1 CMPFILTER Compare Event Filtering 12 2 CMPMODE Comparison Mode 0 2 CMPMODESelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 1 IN Generates an event when the converted data is in the comparison window. 2 OUT Generates an event when the converted data is out of the comparison window. 3 CMPSEL Comparison Selected Channel 3 5 RES Resolution 16 3 RESSelect NO_AVERAGE 12-bit resolution, AFE sample rate is maximum (no averaging). 0 OSR4 13-bit resolution, AFE sample rate divided by 4 (averaging). 2 OSR16 14-bit resolution, AFE sample rate divided by 16 (averaging). 3 OSR64 15-bit resolution, AFE sample rate divided by 64 (averaging). 4 OSR256 16-bit resolution, AFE sample rate divided by 256 (averaging). 5 SIGNMODE Sign Mode 28 2 SIGNMODESelect SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 1 ALL_UNSIGNED All channels: Unsigned conversions. 2 ALL_SIGNED All channels: Signed conversions. 3 STM Single Trigger Mode 25 1 TAG TAG of the AFEC_LDCR 24 1 AFEC_AFEC_IDR AFEC Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 DRDY Data Ready Interrupt Disable 24 1 EOC0 End of Conversion Interrupt Disable 0 0 1 EOC1 End of Conversion Interrupt Disable 1 1 1 EOC10 End of Conversion Interrupt Disable 10 10 1 EOC11 End of Conversion Interrupt Disable 11 11 1 EOC2 End of Conversion Interrupt Disable 2 2 1 EOC3 End of Conversion Interrupt Disable 3 3 1 EOC4 End of Conversion Interrupt Disable 4 4 1 EOC5 End of Conversion Interrupt Disable 5 5 1 EOC6 End of Conversion Interrupt Disable 6 6 1 EOC7 End of Conversion Interrupt Disable 7 7 1 EOC8 End of Conversion Interrupt Disable 8 8 1 EOC9 End of Conversion Interrupt Disable 9 9 1 GOVRE General Overrun Error Interrupt Disable 25 1 TEMPCHG Temperature Change Interrupt Disable 30 1 AFEC_AFEC_IER AFEC Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 DRDY Data Ready Interrupt Enable 24 1 EOC0 End of Conversion Interrupt Enable 0 0 1 EOC1 End of Conversion Interrupt Enable 1 1 1 EOC10 End of Conversion Interrupt Enable 10 10 1 EOC11 End of Conversion Interrupt Enable 11 11 1 EOC2 End of Conversion Interrupt Enable 2 2 1 EOC3 End of Conversion Interrupt Enable 3 3 1 EOC4 End of Conversion Interrupt Enable 4 4 1 EOC5 End of Conversion Interrupt Enable 5 5 1 EOC6 End of Conversion Interrupt Enable 6 6 1 EOC7 End of Conversion Interrupt Enable 7 7 1 EOC8 End of Conversion Interrupt Enable 8 8 1 EOC9 End of Conversion Interrupt Enable 9 9 1 GOVRE General Overrun Error Interrupt Enable 25 1 TEMPCHG Temperature Change Interrupt Enable 30 1 AFEC_AFEC_IMR AFEC Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 DRDY Data Ready Interrupt Mask 24 1 EOC0 End of Conversion Interrupt Mask 0 0 1 EOC1 End of Conversion Interrupt Mask 1 1 1 EOC10 End of Conversion Interrupt Mask 10 10 1 EOC11 End of Conversion Interrupt Mask 11 11 1 EOC2 End of Conversion Interrupt Mask 2 2 1 EOC3 End of Conversion Interrupt Mask 3 3 1 EOC4 End of Conversion Interrupt Mask 4 4 1 EOC5 End of Conversion Interrupt Mask 5 5 1 EOC6 End of Conversion Interrupt Mask 6 6 1 EOC7 End of Conversion Interrupt Mask 7 7 1 EOC8 End of Conversion Interrupt Mask 8 8 1 EOC9 End of Conversion Interrupt Mask 9 9 1 GOVRE General Overrun Error Interrupt Mask 25 1 TEMPCHG Temperature Change Interrupt Mask 30 1 AFEC_AFEC_ISR AFEC Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Error (cleared by reading AFEC_ISR) 26 1 DRDY Data Ready (cleared by reading AFEC_LCDR) 24 1 EOC0 End of Conversion 0 (cleared by reading AFEC_CDRx) 0 1 EOC1 End of Conversion 1 (cleared by reading AFEC_CDRx) 1 1 EOC10 End of Conversion 10 (cleared by reading AFEC_CDRx) 10 1 EOC11 End of Conversion 11 (cleared by reading AFEC_CDRx) 11 1 EOC2 End of Conversion 2 (cleared by reading AFEC_CDRx) 2 1 EOC3 End of Conversion 3 (cleared by reading AFEC_CDRx) 3 1 EOC4 End of Conversion 4 (cleared by reading AFEC_CDRx) 4 1 EOC5 End of Conversion 5 (cleared by reading AFEC_CDRx) 5 1 EOC6 End of Conversion 6 (cleared by reading AFEC_CDRx) 6 1 EOC7 End of Conversion 7 (cleared by reading AFEC_CDRx) 7 1 EOC8 End of Conversion 8 (cleared by reading AFEC_CDRx) 8 1 EOC9 End of Conversion 9 (cleared by reading AFEC_CDRx) 9 1 GOVRE General Overrun Error (cleared by reading AFEC_ISR) 25 1 TEMPCHG Temperature Change (cleared on read) 30 1 AFEC_AFEC_LCDR AFEC Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 24 4 LDATA Last Data Converted 0 16 AFEC_AFEC_MR AFEC Mode Register 0x4 32 read-write n 0x0 0x0 FREERUN Free Run Mode 7 1 FREERUNSelect OFF Normal mode 0 ON Free Run mode: Never wait for any trigger. 1 FWUP Fast Wake-up 6 1 FWUPSelect OFF Normal Sleep mode: The sleep mode is defined by the SLEEP bit. 0 ON Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. 1 ONE One 23 1 PRESCAL Prescaler Rate Selection 8 8 SLEEP Sleep Mode 5 1 SLEEPSelect NORMAL Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. 1 STARTUP Start-up Time 16 4 STARTUPSelect SUT0 0 periods of AFE clock 0 SUT8 8 periods of AFE clock 1 SUT640 640 periods of AFE clock 10 SUT704 704 periods of AFE clock 11 SUT768 768 periods of AFE clock 12 SUT832 832 periods of AFE clock 13 SUT896 896 periods of AFE clock 14 SUT960 960 periods of AFE clock 15 SUT16 16 periods of AFE clock 2 SUT24 24 periods of AFE clock 3 SUT64 64 periods of AFE clock 4 SUT80 80 periods of AFE clock 5 SUT96 96 periods of AFE clock 6 SUT112 112 periods of AFE clock 7 SUT512 512 periods of AFE clock 8 SUT576 576 periods of AFE clock 9 TRACKTIM Tracking Time 24 4 TRANSFER Transfer Period 28 2 TRGEN Trigger Enable 0 1 TRGENSelect DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 TRGSELSelect AFEC_TRIG0 AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 0 AFEC_TRIG1 TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 1 AFEC_TRIG2 TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 2 AFEC_TRIG3 TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 3 AFEC_TRIG4 PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 4 AFEC_TRIG5 PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 5 AFEC_TRIG6 Analog Comparator 6 USEQ User Sequence Enable 31 1 USEQSelect NUM_ORDER Normal mode: The controller converts channels in a simple numeric order. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. 1 AFEC_AFEC_OVER AFEC Overrun Status Register 0x4C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 OVRE1 Overrun Error 1 1 1 OVRE10 Overrun Error 10 10 1 OVRE11 Overrun Error 11 11 1 OVRE2 Overrun Error 2 2 1 OVRE3 Overrun Error 3 3 1 OVRE4 Overrun Error 4 4 1 OVRE5 Overrun Error 5 5 1 OVRE6 Overrun Error 6 6 1 OVRE7 Overrun Error 7 7 1 OVRE8 Overrun Error 8 8 1 OVRE9 Overrun Error 9 9 1 AFEC_AFEC_SEQ1R AFEC Channel Sequence 1 Register 0xC 32 read-write n 0x0 0x0 USCH0 User Sequence Number 0 0 4 USCH1 User Sequence Number 1 4 4 USCH2 User Sequence Number 2 8 4 USCH3 User Sequence Number 3 12 4 USCH4 User Sequence Number 4 16 4 USCH5 User Sequence Number 5 20 4 USCH6 User Sequence Number 6 24 4 USCH7 User Sequence Number 7 28 4 AFEC_AFEC_SEQ2R AFEC Channel Sequence 2 Register 0x10 32 read-write n 0x0 0x0 USCH10 User Sequence Number 10 8 4 USCH11 User Sequence Number 11 12 4 USCH8 User Sequence Number 8 0 4 USCH9 User Sequence Number 9 4 4 AFEC_AFEC_SHMR AFEC Sample and Hold Mode Register 0xA0 32 read-write n 0x0 0x0 DUAL0 Dual Sample & Hold for channel 0 0 1 DUAL1 Dual Sample & Hold for channel 1 1 1 DUAL10 Dual Sample & Hold for channel 10 10 1 DUAL11 Dual Sample & Hold for channel 11 11 1 DUAL2 Dual Sample & Hold for channel 2 2 1 DUAL3 Dual Sample & Hold for channel 3 3 1 DUAL4 Dual Sample & Hold for channel 4 4 1 DUAL5 Dual Sample & Hold for channel 5 5 1 DUAL6 Dual Sample & Hold for channel 6 6 1 DUAL7 Dual Sample & Hold for channel 7 7 1 DUAL8 Dual Sample & Hold for channel 8 8 1 DUAL9 Dual Sample & Hold for channel 9 9 1 AFEC_AFEC_TEMPCWR AFEC Temperature Compare Window Register 0x74 32 read-write n 0x0 0x0 THIGHTHRES Temperature High Threshold 16 16 TLOWTHRES Temperature Low Threshold 0 16 AFEC_AFEC_TEMPMR AFEC Temperature Sensor Mode Register 0x70 32 read-write n 0x0 0x0 RTCT Temperature Sensor RTC Trigger Mode 0 1 TEMPCMPMOD Temperature Comparison Mode 4 2 TEMPCMPMODSelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 1 IN Generates an event when the converted data is in the comparison window. 2 OUT Generates an event when the converted data is out of the comparison window. 3 AFEC_AFEC_WPMR AFEC Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protect KEY 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 4277315 AFEC_AFEC_WPSR AFEC Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 WPVSRC Write Protect Violation Source 8 16 CDR AFEC Channel Data Register 0x68 32 read-only n 0x0 DATA Converted Data 0 16 read-only CECR AFEC Channel Error Correction Register 0xD8 32 read-write n 0x0 ECORR0 Error Correction Enable for channel 0 0 1 read-write ECORR1 Error Correction Enable for channel 1 1 1 read-write ECORR10 Error Correction Enable for channel 10 10 1 read-write ECORR11 Error Correction Enable for channel 11 11 1 read-write ECORR2 Error Correction Enable for channel 2 2 1 read-write ECORR3 Error Correction Enable for channel 3 3 1 read-write ECORR4 Error Correction Enable for channel 4 4 1 read-write ECORR5 Error Correction Enable for channel 5 5 1 read-write ECORR6 Error Correction Enable for channel 6 6 1 read-write ECORR7 Error Correction Enable for channel 7 7 1 read-write ECORR8 Error Correction Enable for channel 8 8 1 read-write ECORR9 Error Correction Enable for channel 9 9 1 read-write CGR AFEC Channel Gain Register 0x54 32 read-write n 0x0 GAIN0 Gain for Channel 0 0 2 read-write GAIN1 Gain for Channel 1 2 2 read-write GAIN10 Gain for Channel 10 20 2 read-write GAIN11 Gain for Channel 11 22 2 read-write GAIN2 Gain for Channel 2 4 2 read-write GAIN3 Gain for Channel 3 6 2 read-write GAIN4 Gain for Channel 4 8 2 read-write GAIN5 Gain for Channel 5 10 2 read-write GAIN6 Gain for Channel 6 12 2 read-write GAIN7 Gain for Channel 7 14 2 read-write GAIN8 Gain for Channel 8 16 2 read-write GAIN9 Gain for Channel 9 18 2 read-write CHDR AFEC Channel Disable Register 0x18 32 write-only n CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CH10 Channel 10 Disable 10 1 write-only CH11 Channel 11 Disable 11 1 write-only CH2 Channel 2 Disable 2 1 write-only CH3 Channel 3 Disable 3 1 write-only CH4 Channel 4 Disable 4 1 write-only CH5 Channel 5 Disable 5 1 write-only CH6 Channel 6 Disable 6 1 write-only CH7 Channel 7 Disable 7 1 write-only CH8 Channel 8 Disable 8 1 write-only CH9 Channel 9 Disable 9 1 write-only CHER AFEC Channel Enable Register 0x14 32 write-only n CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CH10 Channel 10 Enable 10 1 write-only CH11 Channel 11 Enable 11 1 write-only CH2 Channel 2 Enable 2 1 write-only CH3 Channel 3 Enable 3 1 write-only CH4 Channel 4 Enable 4 1 write-only CH5 Channel 5 Enable 5 1 write-only CH6 Channel 6 Enable 6 1 write-only CH7 Channel 7 Enable 7 1 write-only CH8 Channel 8 Enable 8 1 write-only CH9 Channel 9 Enable 9 1 write-only CHSR AFEC Channel Status Register 0x1C 32 read-only n 0x0 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CH10 Channel 10 Status 10 1 read-only CH11 Channel 11 Status 11 1 read-only CH2 Channel 2 Status 2 1 read-only CH3 Channel 3 Status 3 1 read-only CH4 Channel 4 Status 4 1 read-only CH5 Channel 5 Status 5 1 read-only CH6 Channel 6 Status 6 1 read-only CH7 Channel 7 Status 7 1 read-only CH8 Channel 8 Status 8 1 read-only CH9 Channel 9 Status 9 1 read-only COCR AFEC Channel Offset Compensation Register 0x6C 32 read-write n 0x0 AOFF Analog Offset 0 10 read-write COSR AFEC Correction Select Register 0xD0 32 read-write n 0x0 CSEL Sample and Hold unit Correction Select 0 1 read-write CR AFEC Control Register 0x0 32 write-only n START Start Conversion 1 1 write-only SWRST Software Reset 0 1 write-only CSELR AFEC Channel Selection Register 0x64 32 read-write n 0x0 CSEL Channel Selection 0 4 read-write CVR AFEC Correction Values Register 0xD4 32 read-write n 0x0 GAINCORR Gain Correction 16 16 read-write OFFSETCORR Offset Correction 0 16 read-write CWR AFEC Compare Window Register 0x50 32 read-write n 0x0 HIGHTHRES High Threshold 16 16 read-write LOWTHRES Low Threshold 0 16 read-write DIFFR AFEC Channel Differential Register 0x60 32 read-write n 0x0 DIFF0 Differential inputs for channel 0 0 1 read-write DIFF1 Differential inputs for channel 1 1 1 read-write DIFF10 Differential inputs for channel 10 10 1 read-write DIFF11 Differential inputs for channel 11 11 1 read-write DIFF2 Differential inputs for channel 2 2 1 read-write DIFF3 Differential inputs for channel 3 3 1 read-write DIFF4 Differential inputs for channel 4 4 1 read-write DIFF5 Differential inputs for channel 5 5 1 read-write DIFF6 Differential inputs for channel 6 6 1 read-write DIFF7 Differential inputs for channel 7 7 1 read-write DIFF8 Differential inputs for channel 8 8 1 read-write DIFF9 Differential inputs for channel 9 9 1 read-write EMR AFEC Extended Mode Register 0x8 32 read-write n 0x0 CMPALL Compare All Channels 9 1 read-write CMPFILTER Compare Event Filtering 12 2 read-write CMPMODE Comparison Mode 0 2 read-write LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 3 5 read-write RES Resolution 16 3 read-write NO_AVERAGE 12-bit resolution, AFE sample rate is maximum (no averaging). 0x0 OSR4 13-bit resolution, AFE sample rate divided by 4 (averaging). 0x2 OSR16 14-bit resolution, AFE sample rate divided by 16 (averaging). 0x3 OSR64 15-bit resolution, AFE sample rate divided by 64 (averaging). 0x4 OSR256 16-bit resolution, AFE sample rate divided by 256 (averaging). 0x5 SIGNMODE Sign Mode 28 2 read-write SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0x0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 0x1 ALL_UNSIGNED All channels: Unsigned conversions. 0x2 ALL_SIGNED All channels: Signed conversions. 0x3 STM Single Trigger Mode 25 1 read-write TAG TAG of the AFEC_LDCR 24 1 read-write IDR AFEC Interrupt Disable Register 0x28 32 write-only n COMPE Comparison Event Interrupt Disable 26 1 write-only DRDY Data Ready Interrupt Disable 24 1 write-only EOC0 End of Conversion Interrupt Disable 0 0 1 write-only EOC1 End of Conversion Interrupt Disable 1 1 1 write-only EOC10 End of Conversion Interrupt Disable 10 10 1 write-only EOC11 End of Conversion Interrupt Disable 11 11 1 write-only EOC2 End of Conversion Interrupt Disable 2 2 1 write-only EOC3 End of Conversion Interrupt Disable 3 3 1 write-only EOC4 End of Conversion Interrupt Disable 4 4 1 write-only EOC5 End of Conversion Interrupt Disable 5 5 1 write-only EOC6 End of Conversion Interrupt Disable 6 6 1 write-only EOC7 End of Conversion Interrupt Disable 7 7 1 write-only EOC8 End of Conversion Interrupt Disable 8 8 1 write-only EOC9 End of Conversion Interrupt Disable 9 9 1 write-only GOVRE General Overrun Error Interrupt Disable 25 1 write-only TEMPCHG Temperature Change Interrupt Disable 30 1 write-only IER AFEC Interrupt Enable Register 0x24 32 write-only n COMPE Comparison Event Interrupt Enable 26 1 write-only DRDY Data Ready Interrupt Enable 24 1 write-only EOC0 End of Conversion Interrupt Enable 0 0 1 write-only EOC1 End of Conversion Interrupt Enable 1 1 1 write-only EOC10 End of Conversion Interrupt Enable 10 10 1 write-only EOC11 End of Conversion Interrupt Enable 11 11 1 write-only EOC2 End of Conversion Interrupt Enable 2 2 1 write-only EOC3 End of Conversion Interrupt Enable 3 3 1 write-only EOC4 End of Conversion Interrupt Enable 4 4 1 write-only EOC5 End of Conversion Interrupt Enable 5 5 1 write-only EOC6 End of Conversion Interrupt Enable 6 6 1 write-only EOC7 End of Conversion Interrupt Enable 7 7 1 write-only EOC8 End of Conversion Interrupt Enable 8 8 1 write-only EOC9 End of Conversion Interrupt Enable 9 9 1 write-only GOVRE General Overrun Error Interrupt Enable 25 1 write-only TEMPCHG Temperature Change Interrupt Enable 30 1 write-only IMR AFEC Interrupt Mask Register 0x2C 32 read-only n 0x0 COMPE Comparison Event Interrupt Mask 26 1 read-only DRDY Data Ready Interrupt Mask 24 1 read-only EOC0 End of Conversion Interrupt Mask 0 0 1 read-only EOC1 End of Conversion Interrupt Mask 1 1 1 read-only EOC10 End of Conversion Interrupt Mask 10 10 1 read-only EOC11 End of Conversion Interrupt Mask 11 11 1 read-only EOC2 End of Conversion Interrupt Mask 2 2 1 read-only EOC3 End of Conversion Interrupt Mask 3 3 1 read-only EOC4 End of Conversion Interrupt Mask 4 4 1 read-only EOC5 End of Conversion Interrupt Mask 5 5 1 read-only EOC6 End of Conversion Interrupt Mask 6 6 1 read-only EOC7 End of Conversion Interrupt Mask 7 7 1 read-only EOC8 End of Conversion Interrupt Mask 8 8 1 read-only EOC9 End of Conversion Interrupt Mask 9 9 1 read-only GOVRE General Overrun Error Interrupt Mask 25 1 read-only TEMPCHG Temperature Change Interrupt Mask 30 1 read-only ISR AFEC Interrupt Status Register 0x30 32 read-only n 0x0 COMPE Comparison Error (cleared by reading AFEC_ISR) 26 1 read-only DRDY Data Ready (cleared by reading AFEC_LCDR) 24 1 read-only EOC0 End of Conversion 0 (cleared by reading AFEC_CDRx) 0 1 read-only EOC1 End of Conversion 1 (cleared by reading AFEC_CDRx) 1 1 read-only EOC10 End of Conversion 10 (cleared by reading AFEC_CDRx) 10 1 read-only EOC11 End of Conversion 11 (cleared by reading AFEC_CDRx) 11 1 read-only EOC2 End of Conversion 2 (cleared by reading AFEC_CDRx) 2 1 read-only EOC3 End of Conversion 3 (cleared by reading AFEC_CDRx) 3 1 read-only EOC4 End of Conversion 4 (cleared by reading AFEC_CDRx) 4 1 read-only EOC5 End of Conversion 5 (cleared by reading AFEC_CDRx) 5 1 read-only EOC6 End of Conversion 6 (cleared by reading AFEC_CDRx) 6 1 read-only EOC7 End of Conversion 7 (cleared by reading AFEC_CDRx) 7 1 read-only EOC8 End of Conversion 8 (cleared by reading AFEC_CDRx) 8 1 read-only EOC9 End of Conversion 9 (cleared by reading AFEC_CDRx) 9 1 read-only GOVRE General Overrun Error (cleared by reading AFEC_ISR) 25 1 read-only TEMPCHG Temperature Change (cleared on read) 30 1 read-only LCDR AFEC Last Converted Data Register 0x20 32 read-only n 0x0 CHNB Channel Number 24 4 read-only LDATA Last Data Converted 0 16 read-only MR AFEC Mode Register 0x4 32 read-write n 0x0 FREERUN Free Run Mode 7 1 read-write OFF Normal mode 0 ON Free Run mode: Never wait for any trigger. 1 FWUP Fast Wake-up 6 1 read-write OFF Normal Sleep mode: The sleep mode is defined by the SLEEP bit. 0 ON Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. 1 ONE One 23 1 read-write PRESCAL Prescaler Rate Selection 8 8 read-write SLEEP Sleep Mode 5 1 read-write NORMAL Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. 1 STARTUP Start-up Time 16 4 read-write SUT0 0 periods of AFE clock 0x0 SUT8 8 periods of AFE clock 0x1 SUT16 16 periods of AFE clock 0x2 SUT24 24 periods of AFE clock 0x3 SUT64 64 periods of AFE clock 0x4 SUT80 80 periods of AFE clock 0x5 SUT96 96 periods of AFE clock 0x6 SUT112 112 periods of AFE clock 0x7 SUT512 512 periods of AFE clock 0x8 SUT576 576 periods of AFE clock 0x9 SUT640 640 periods of AFE clock 0xA SUT704 704 periods of AFE clock 0xB SUT768 768 periods of AFE clock 0xC SUT832 832 periods of AFE clock 0xD SUT896 896 periods of AFE clock 0xE SUT960 960 periods of AFE clock 0xF TRACKTIM Tracking Time 24 4 read-write TRANSFER Transfer Period 28 2 read-write TRGEN Trigger Enable 0 1 read-write DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 read-write AFEC_TRIG0 AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 0x0 AFEC_TRIG1 TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 0x1 AFEC_TRIG2 TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 0x2 AFEC_TRIG3 TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 0x3 AFEC_TRIG4 PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 0x4 AFEC_TRIG5 PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 0x5 AFEC_TRIG6 Analog Comparator 0x6 USEQ User Sequence Enable 31 1 read-write NUM_ORDER Normal mode: The controller converts channels in a simple numeric order. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. 1 OVER AFEC Overrun Status Register 0x4C 32 read-only n 0x0 OVRE0 Overrun Error 0 0 1 read-only OVRE1 Overrun Error 1 1 1 read-only OVRE10 Overrun Error 10 10 1 read-only OVRE11 Overrun Error 11 11 1 read-only OVRE2 Overrun Error 2 2 1 read-only OVRE3 Overrun Error 3 3 1 read-only OVRE4 Overrun Error 4 4 1 read-only OVRE5 Overrun Error 5 5 1 read-only OVRE6 Overrun Error 6 6 1 read-only OVRE7 Overrun Error 7 7 1 read-only OVRE8 Overrun Error 8 8 1 read-only OVRE9 Overrun Error 9 9 1 read-only SEQ1R AFEC Channel Sequence 1 Register 0xC 32 read-write n 0x0 USCH0 User Sequence Number 0 0 4 read-write USCH1 User Sequence Number 1 4 4 read-write USCH2 User Sequence Number 2 8 4 read-write USCH3 User Sequence Number 3 12 4 read-write USCH4 User Sequence Number 4 16 4 read-write USCH5 User Sequence Number 5 20 4 read-write USCH6 User Sequence Number 6 24 4 read-write USCH7 User Sequence Number 7 28 4 read-write SEQ2R AFEC Channel Sequence 2 Register 0x10 32 read-write n 0x0 USCH10 User Sequence Number 10 8 4 read-write USCH11 User Sequence Number 11 12 4 read-write USCH12 User Sequence Number 12 16 4 read-write USCH13 User Sequence Number 13 20 4 read-write USCH14 User Sequence Number 14 24 4 read-write USCH15 User Sequence Number 15 28 4 read-write USCH8 User Sequence Number 8 0 4 read-write USCH9 User Sequence Number 9 4 4 read-write SHMR AFEC Sample and Hold Mode Register 0xA0 32 read-write n 0x0 DUAL0 Dual Sample and Hold for channel 0 0 1 read-write DUAL1 Dual Sample and Hold for channel 1 1 1 read-write DUAL10 Dual Sample and Hold for channel 10 10 1 read-write DUAL11 Dual Sample and Hold for channel 11 11 1 read-write DUAL2 Dual Sample and Hold for channel 2 2 1 read-write DUAL3 Dual Sample and Hold for channel 3 3 1 read-write DUAL4 Dual Sample and Hold for channel 4 4 1 read-write DUAL5 Dual Sample and Hold for channel 5 5 1 read-write DUAL6 Dual Sample and Hold for channel 6 6 1 read-write DUAL7 Dual Sample and Hold for channel 7 7 1 read-write DUAL8 Dual Sample and Hold for channel 8 8 1 read-write DUAL9 Dual Sample and Hold for channel 9 9 1 read-write TEMPCWR AFEC Temperature Compare Window Register 0x74 32 read-write n 0x0 THIGHTHRES Temperature High Threshold 16 16 read-write TLOWTHRES Temperature Low Threshold 0 16 read-write TEMPMR AFEC Temperature Sensor Mode Register 0x70 32 read-write n 0x0 RTCT Temperature Sensor RTC Trigger Mode 0 1 read-write TEMPCMPMOD Temperature Comparison Mode 4 2 read-write LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 WPMR AFEC Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x414443 WPSR AFEC Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only AFEC1 Analog Front-End Controller 1 AFEC 0x0 0x0 0x4000 registers n AFEC1 40 ACR AFEC Analog Control Register 0x94 32 read-write n 0x0 IBCTL AFE Bias Current Control 8 2 read-write PGA0EN PGA0 Enable 2 1 read-write PGA1EN PGA1 Enable 3 1 read-write AFEC_AFEC_ACR AFEC Analog Control Register 0x94 32 read-write n 0x0 0x0 IBCTL AFE Bias Current Control 8 2 PGA0EN PGA0 Enable 2 1 PGA1EN PGA1 Enable 3 1 AFEC_AFEC_CDR AFEC Channel Data Register 0x68 32 read-only n 0x0 0x0 DATA Converted Data 0 16 AFEC_AFEC_CECR AFEC Channel Error Correction Register 0xD8 32 read-write n 0x0 0x0 ECORR0 Error Correction Enable for channel 0 0 1 ECORR1 Error Correction Enable for channel 1 1 1 ECORR10 Error Correction Enable for channel 10 10 1 ECORR11 Error Correction Enable for channel 11 11 1 ECORR2 Error Correction Enable for channel 2 2 1 ECORR3 Error Correction Enable for channel 3 3 1 ECORR4 Error Correction Enable for channel 4 4 1 ECORR5 Error Correction Enable for channel 5 5 1 ECORR6 Error Correction Enable for channel 6 6 1 ECORR7 Error Correction Enable for channel 7 7 1 ECORR8 Error Correction Enable for channel 8 8 1 ECORR9 Error Correction Enable for channel 9 9 1 AFEC_AFEC_CGR AFEC Channel Gain Register 0x54 32 read-write n 0x0 0x0 GAIN0 Gain for Channel 0 0 2 GAIN1 Gain for Channel 1 2 2 GAIN10 Gain for Channel 10 20 2 GAIN11 Gain for Channel 11 22 2 GAIN2 Gain for Channel 2 4 2 GAIN3 Gain for Channel 3 6 2 GAIN4 Gain for Channel 4 8 2 GAIN5 Gain for Channel 5 10 2 GAIN6 Gain for Channel 6 12 2 GAIN7 Gain for Channel 7 14 2 GAIN8 Gain for Channel 8 16 2 GAIN9 Gain for Channel 9 18 2 AFEC_AFEC_CHDR AFEC Channel Disable Register 0x18 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 CH1 Channel 1 Disable 1 1 CH10 Channel 10 Disable 10 1 CH11 Channel 11 Disable 11 1 CH2 Channel 2 Disable 2 1 CH3 Channel 3 Disable 3 1 CH4 Channel 4 Disable 4 1 CH5 Channel 5 Disable 5 1 CH6 Channel 6 Disable 6 1 CH7 Channel 7 Disable 7 1 CH8 Channel 8 Disable 8 1 CH9 Channel 9 Disable 9 1 AFEC_AFEC_CHER AFEC Channel Enable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 CH1 Channel 1 Enable 1 1 CH10 Channel 10 Enable 10 1 CH11 Channel 11 Enable 11 1 CH2 Channel 2 Enable 2 1 CH3 Channel 3 Enable 3 1 CH4 Channel 4 Enable 4 1 CH5 Channel 5 Enable 5 1 CH6 Channel 6 Enable 6 1 CH7 Channel 7 Enable 7 1 CH8 Channel 8 Enable 8 1 CH9 Channel 9 Enable 9 1 AFEC_AFEC_CHSR AFEC Channel Status Register 0x1C 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 CH1 Channel 1 Status 1 1 CH10 Channel 10 Status 10 1 CH11 Channel 11 Status 11 1 CH2 Channel 2 Status 2 1 CH3 Channel 3 Status 3 1 CH4 Channel 4 Status 4 1 CH5 Channel 5 Status 5 1 CH6 Channel 6 Status 6 1 CH7 Channel 7 Status 7 1 CH8 Channel 8 Status 8 1 CH9 Channel 9 Status 9 1 AFEC_AFEC_COCR AFEC Channel Offset Compensation Register 0x6C 32 read-write n 0x0 0x0 AOFF Analog Offset 0 10 AFEC_AFEC_COSR AFEC Correction Select Register 0xD0 32 read-write n 0x0 0x0 CSEL Sample & Hold unit Correction Select 0 1 AFEC_AFEC_CR AFEC Control Register 0x0 32 write-only n 0x0 0x0 START Start Conversion 1 1 SWRST Software Reset 0 1 AFEC_AFEC_CSELR AFEC Channel Selection Register 0x64 32 read-write n 0x0 0x0 CSEL Channel Selection 0 4 AFEC_AFEC_CVR AFEC Correction Values Register 0xD4 32 read-write n 0x0 0x0 GAINCORR Gain Correction 16 16 OFFSETCORR Offset Correction 0 16 AFEC_AFEC_CWR AFEC Compare Window Register 0x50 32 read-write n 0x0 0x0 HIGHTHRES High Threshold 16 16 LOWTHRES Low Threshold 0 16 AFEC_AFEC_DIFFR AFEC Channel Differential Register 0x60 32 read-write n 0x0 0x0 DIFF0 Differential inputs for channel 0 0 1 DIFF1 Differential inputs for channel 1 1 1 DIFF10 Differential inputs for channel 10 10 1 DIFF11 Differential inputs for channel 11 11 1 DIFF2 Differential inputs for channel 2 2 1 DIFF3 Differential inputs for channel 3 3 1 DIFF4 Differential inputs for channel 4 4 1 DIFF5 Differential inputs for channel 5 5 1 DIFF6 Differential inputs for channel 6 6 1 DIFF7 Differential inputs for channel 7 7 1 DIFF8 Differential inputs for channel 8 8 1 DIFF9 Differential inputs for channel 9 9 1 AFEC_AFEC_EMR AFEC Extended Mode Register 0x8 32 read-write n 0x0 0x0 CMPALL Compare All Channels 9 1 CMPFILTER Compare Event Filtering 12 2 CMPMODE Comparison Mode 0 2 CMPMODESelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 1 IN Generates an event when the converted data is in the comparison window. 2 OUT Generates an event when the converted data is out of the comparison window. 3 CMPSEL Comparison Selected Channel 3 5 RES Resolution 16 3 RESSelect NO_AVERAGE 12-bit resolution, AFE sample rate is maximum (no averaging). 0 OSR4 13-bit resolution, AFE sample rate divided by 4 (averaging). 2 OSR16 14-bit resolution, AFE sample rate divided by 16 (averaging). 3 OSR64 15-bit resolution, AFE sample rate divided by 64 (averaging). 4 OSR256 16-bit resolution, AFE sample rate divided by 256 (averaging). 5 SIGNMODE Sign Mode 28 2 SIGNMODESelect SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 1 ALL_UNSIGNED All channels: Unsigned conversions. 2 ALL_SIGNED All channels: Signed conversions. 3 STM Single Trigger Mode 25 1 TAG TAG of the AFEC_LDCR 24 1 AFEC_AFEC_IDR AFEC Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Disable 26 1 DRDY Data Ready Interrupt Disable 24 1 EOC0 End of Conversion Interrupt Disable 0 0 1 EOC1 End of Conversion Interrupt Disable 1 1 1 EOC10 End of Conversion Interrupt Disable 10 10 1 EOC11 End of Conversion Interrupt Disable 11 11 1 EOC2 End of Conversion Interrupt Disable 2 2 1 EOC3 End of Conversion Interrupt Disable 3 3 1 EOC4 End of Conversion Interrupt Disable 4 4 1 EOC5 End of Conversion Interrupt Disable 5 5 1 EOC6 End of Conversion Interrupt Disable 6 6 1 EOC7 End of Conversion Interrupt Disable 7 7 1 EOC8 End of Conversion Interrupt Disable 8 8 1 EOC9 End of Conversion Interrupt Disable 9 9 1 GOVRE General Overrun Error Interrupt Disable 25 1 TEMPCHG Temperature Change Interrupt Disable 30 1 AFEC_AFEC_IER AFEC Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 COMPE Comparison Event Interrupt Enable 26 1 DRDY Data Ready Interrupt Enable 24 1 EOC0 End of Conversion Interrupt Enable 0 0 1 EOC1 End of Conversion Interrupt Enable 1 1 1 EOC10 End of Conversion Interrupt Enable 10 10 1 EOC11 End of Conversion Interrupt Enable 11 11 1 EOC2 End of Conversion Interrupt Enable 2 2 1 EOC3 End of Conversion Interrupt Enable 3 3 1 EOC4 End of Conversion Interrupt Enable 4 4 1 EOC5 End of Conversion Interrupt Enable 5 5 1 EOC6 End of Conversion Interrupt Enable 6 6 1 EOC7 End of Conversion Interrupt Enable 7 7 1 EOC8 End of Conversion Interrupt Enable 8 8 1 EOC9 End of Conversion Interrupt Enable 9 9 1 GOVRE General Overrun Error Interrupt Enable 25 1 TEMPCHG Temperature Change Interrupt Enable 30 1 AFEC_AFEC_IMR AFEC Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 COMPE Comparison Event Interrupt Mask 26 1 DRDY Data Ready Interrupt Mask 24 1 EOC0 End of Conversion Interrupt Mask 0 0 1 EOC1 End of Conversion Interrupt Mask 1 1 1 EOC10 End of Conversion Interrupt Mask 10 10 1 EOC11 End of Conversion Interrupt Mask 11 11 1 EOC2 End of Conversion Interrupt Mask 2 2 1 EOC3 End of Conversion Interrupt Mask 3 3 1 EOC4 End of Conversion Interrupt Mask 4 4 1 EOC5 End of Conversion Interrupt Mask 5 5 1 EOC6 End of Conversion Interrupt Mask 6 6 1 EOC7 End of Conversion Interrupt Mask 7 7 1 EOC8 End of Conversion Interrupt Mask 8 8 1 EOC9 End of Conversion Interrupt Mask 9 9 1 GOVRE General Overrun Error Interrupt Mask 25 1 TEMPCHG Temperature Change Interrupt Mask 30 1 AFEC_AFEC_ISR AFEC Interrupt Status Register 0x30 32 read-only n 0x0 0x0 COMPE Comparison Error (cleared by reading AFEC_ISR) 26 1 DRDY Data Ready (cleared by reading AFEC_LCDR) 24 1 EOC0 End of Conversion 0 (cleared by reading AFEC_CDRx) 0 1 EOC1 End of Conversion 1 (cleared by reading AFEC_CDRx) 1 1 EOC10 End of Conversion 10 (cleared by reading AFEC_CDRx) 10 1 EOC11 End of Conversion 11 (cleared by reading AFEC_CDRx) 11 1 EOC2 End of Conversion 2 (cleared by reading AFEC_CDRx) 2 1 EOC3 End of Conversion 3 (cleared by reading AFEC_CDRx) 3 1 EOC4 End of Conversion 4 (cleared by reading AFEC_CDRx) 4 1 EOC5 End of Conversion 5 (cleared by reading AFEC_CDRx) 5 1 EOC6 End of Conversion 6 (cleared by reading AFEC_CDRx) 6 1 EOC7 End of Conversion 7 (cleared by reading AFEC_CDRx) 7 1 EOC8 End of Conversion 8 (cleared by reading AFEC_CDRx) 8 1 EOC9 End of Conversion 9 (cleared by reading AFEC_CDRx) 9 1 GOVRE General Overrun Error (cleared by reading AFEC_ISR) 25 1 TEMPCHG Temperature Change (cleared on read) 30 1 AFEC_AFEC_LCDR AFEC Last Converted Data Register 0x20 32 read-only n 0x0 0x0 CHNB Channel Number 24 4 LDATA Last Data Converted 0 16 AFEC_AFEC_MR AFEC Mode Register 0x4 32 read-write n 0x0 0x0 FREERUN Free Run Mode 7 1 FREERUNSelect OFF Normal mode 0 ON Free Run mode: Never wait for any trigger. 1 FWUP Fast Wake-up 6 1 FWUPSelect OFF Normal Sleep mode: The sleep mode is defined by the SLEEP bit. 0 ON Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. 1 ONE One 23 1 PRESCAL Prescaler Rate Selection 8 8 SLEEP Sleep Mode 5 1 SLEEPSelect NORMAL Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. 1 STARTUP Start-up Time 16 4 STARTUPSelect SUT0 0 periods of AFE clock 0 SUT8 8 periods of AFE clock 1 SUT640 640 periods of AFE clock 10 SUT704 704 periods of AFE clock 11 SUT768 768 periods of AFE clock 12 SUT832 832 periods of AFE clock 13 SUT896 896 periods of AFE clock 14 SUT960 960 periods of AFE clock 15 SUT16 16 periods of AFE clock 2 SUT24 24 periods of AFE clock 3 SUT64 64 periods of AFE clock 4 SUT80 80 periods of AFE clock 5 SUT96 96 periods of AFE clock 6 SUT112 112 periods of AFE clock 7 SUT512 512 periods of AFE clock 8 SUT576 576 periods of AFE clock 9 TRACKTIM Tracking Time 24 4 TRANSFER Transfer Period 28 2 TRGEN Trigger Enable 0 1 TRGENSelect DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 TRGSELSelect AFEC_TRIG0 AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 0 AFEC_TRIG1 TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 1 AFEC_TRIG2 TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 2 AFEC_TRIG3 TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 3 AFEC_TRIG4 PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 4 AFEC_TRIG5 PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 5 AFEC_TRIG6 Analog Comparator 6 USEQ User Sequence Enable 31 1 USEQSelect NUM_ORDER Normal mode: The controller converts channels in a simple numeric order. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. 1 AFEC_AFEC_OVER AFEC Overrun Status Register 0x4C 32 read-only n 0x0 0x0 OVRE0 Overrun Error 0 0 1 OVRE1 Overrun Error 1 1 1 OVRE10 Overrun Error 10 10 1 OVRE11 Overrun Error 11 11 1 OVRE2 Overrun Error 2 2 1 OVRE3 Overrun Error 3 3 1 OVRE4 Overrun Error 4 4 1 OVRE5 Overrun Error 5 5 1 OVRE6 Overrun Error 6 6 1 OVRE7 Overrun Error 7 7 1 OVRE8 Overrun Error 8 8 1 OVRE9 Overrun Error 9 9 1 AFEC_AFEC_SEQ1R AFEC Channel Sequence 1 Register 0xC 32 read-write n 0x0 0x0 USCH0 User Sequence Number 0 0 4 USCH1 User Sequence Number 1 4 4 USCH2 User Sequence Number 2 8 4 USCH3 User Sequence Number 3 12 4 USCH4 User Sequence Number 4 16 4 USCH5 User Sequence Number 5 20 4 USCH6 User Sequence Number 6 24 4 USCH7 User Sequence Number 7 28 4 AFEC_AFEC_SEQ2R AFEC Channel Sequence 2 Register 0x10 32 read-write n 0x0 0x0 USCH10 User Sequence Number 10 8 4 USCH11 User Sequence Number 11 12 4 USCH8 User Sequence Number 8 0 4 USCH9 User Sequence Number 9 4 4 AFEC_AFEC_SHMR AFEC Sample and Hold Mode Register 0xA0 32 read-write n 0x0 0x0 DUAL0 Dual Sample & Hold for channel 0 0 1 DUAL1 Dual Sample & Hold for channel 1 1 1 DUAL10 Dual Sample & Hold for channel 10 10 1 DUAL11 Dual Sample & Hold for channel 11 11 1 DUAL2 Dual Sample & Hold for channel 2 2 1 DUAL3 Dual Sample & Hold for channel 3 3 1 DUAL4 Dual Sample & Hold for channel 4 4 1 DUAL5 Dual Sample & Hold for channel 5 5 1 DUAL6 Dual Sample & Hold for channel 6 6 1 DUAL7 Dual Sample & Hold for channel 7 7 1 DUAL8 Dual Sample & Hold for channel 8 8 1 DUAL9 Dual Sample & Hold for channel 9 9 1 AFEC_AFEC_TEMPCWR AFEC Temperature Compare Window Register 0x74 32 read-write n 0x0 0x0 THIGHTHRES Temperature High Threshold 16 16 TLOWTHRES Temperature Low Threshold 0 16 AFEC_AFEC_TEMPMR AFEC Temperature Sensor Mode Register 0x70 32 read-write n 0x0 0x0 RTCT Temperature Sensor RTC Trigger Mode 0 1 TEMPCMPMOD Temperature Comparison Mode 4 2 TEMPCMPMODSelect LOW Generates an event when the converted data is lower than the low threshold of the window. 0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 1 IN Generates an event when the converted data is in the comparison window. 2 OUT Generates an event when the converted data is out of the comparison window. 3 AFEC_AFEC_WPMR AFEC Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protect KEY 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 4277315 AFEC_AFEC_WPSR AFEC Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protect Violation Status 0 1 WPVSRC Write Protect Violation Source 8 16 CDR AFEC Channel Data Register 0x68 32 read-only n 0x0 DATA Converted Data 0 16 read-only CECR AFEC Channel Error Correction Register 0xD8 32 read-write n 0x0 ECORR0 Error Correction Enable for channel 0 0 1 read-write ECORR1 Error Correction Enable for channel 1 1 1 read-write ECORR10 Error Correction Enable for channel 10 10 1 read-write ECORR11 Error Correction Enable for channel 11 11 1 read-write ECORR2 Error Correction Enable for channel 2 2 1 read-write ECORR3 Error Correction Enable for channel 3 3 1 read-write ECORR4 Error Correction Enable for channel 4 4 1 read-write ECORR5 Error Correction Enable for channel 5 5 1 read-write ECORR6 Error Correction Enable for channel 6 6 1 read-write ECORR7 Error Correction Enable for channel 7 7 1 read-write ECORR8 Error Correction Enable for channel 8 8 1 read-write ECORR9 Error Correction Enable for channel 9 9 1 read-write CGR AFEC Channel Gain Register 0x54 32 read-write n 0x0 GAIN0 Gain for Channel 0 0 2 read-write GAIN1 Gain for Channel 1 2 2 read-write GAIN10 Gain for Channel 10 20 2 read-write GAIN11 Gain for Channel 11 22 2 read-write GAIN2 Gain for Channel 2 4 2 read-write GAIN3 Gain for Channel 3 6 2 read-write GAIN4 Gain for Channel 4 8 2 read-write GAIN5 Gain for Channel 5 10 2 read-write GAIN6 Gain for Channel 6 12 2 read-write GAIN7 Gain for Channel 7 14 2 read-write GAIN8 Gain for Channel 8 16 2 read-write GAIN9 Gain for Channel 9 18 2 read-write CHDR AFEC Channel Disable Register 0x18 32 write-only n CH0 Channel 0 Disable 0 1 write-only CH1 Channel 1 Disable 1 1 write-only CH10 Channel 10 Disable 10 1 write-only CH11 Channel 11 Disable 11 1 write-only CH2 Channel 2 Disable 2 1 write-only CH3 Channel 3 Disable 3 1 write-only CH4 Channel 4 Disable 4 1 write-only CH5 Channel 5 Disable 5 1 write-only CH6 Channel 6 Disable 6 1 write-only CH7 Channel 7 Disable 7 1 write-only CH8 Channel 8 Disable 8 1 write-only CH9 Channel 9 Disable 9 1 write-only CHER AFEC Channel Enable Register 0x14 32 write-only n CH0 Channel 0 Enable 0 1 write-only CH1 Channel 1 Enable 1 1 write-only CH10 Channel 10 Enable 10 1 write-only CH11 Channel 11 Enable 11 1 write-only CH2 Channel 2 Enable 2 1 write-only CH3 Channel 3 Enable 3 1 write-only CH4 Channel 4 Enable 4 1 write-only CH5 Channel 5 Enable 5 1 write-only CH6 Channel 6 Enable 6 1 write-only CH7 Channel 7 Enable 7 1 write-only CH8 Channel 8 Enable 8 1 write-only CH9 Channel 9 Enable 9 1 write-only CHSR AFEC Channel Status Register 0x1C 32 read-only n 0x0 CH0 Channel 0 Status 0 1 read-only CH1 Channel 1 Status 1 1 read-only CH10 Channel 10 Status 10 1 read-only CH11 Channel 11 Status 11 1 read-only CH2 Channel 2 Status 2 1 read-only CH3 Channel 3 Status 3 1 read-only CH4 Channel 4 Status 4 1 read-only CH5 Channel 5 Status 5 1 read-only CH6 Channel 6 Status 6 1 read-only CH7 Channel 7 Status 7 1 read-only CH8 Channel 8 Status 8 1 read-only CH9 Channel 9 Status 9 1 read-only COCR AFEC Channel Offset Compensation Register 0x6C 32 read-write n 0x0 AOFF Analog Offset 0 10 read-write COSR AFEC Correction Select Register 0xD0 32 read-write n 0x0 CSEL Sample and Hold unit Correction Select 0 1 read-write CR AFEC Control Register 0x0 32 write-only n START Start Conversion 1 1 write-only SWRST Software Reset 0 1 write-only CSELR AFEC Channel Selection Register 0x64 32 read-write n 0x0 CSEL Channel Selection 0 4 read-write CVR AFEC Correction Values Register 0xD4 32 read-write n 0x0 GAINCORR Gain Correction 16 16 read-write OFFSETCORR Offset Correction 0 16 read-write CWR AFEC Compare Window Register 0x50 32 read-write n 0x0 HIGHTHRES High Threshold 16 16 read-write LOWTHRES Low Threshold 0 16 read-write DIFFR AFEC Channel Differential Register 0x60 32 read-write n 0x0 DIFF0 Differential inputs for channel 0 0 1 read-write DIFF1 Differential inputs for channel 1 1 1 read-write DIFF10 Differential inputs for channel 10 10 1 read-write DIFF11 Differential inputs for channel 11 11 1 read-write DIFF2 Differential inputs for channel 2 2 1 read-write DIFF3 Differential inputs for channel 3 3 1 read-write DIFF4 Differential inputs for channel 4 4 1 read-write DIFF5 Differential inputs for channel 5 5 1 read-write DIFF6 Differential inputs for channel 6 6 1 read-write DIFF7 Differential inputs for channel 7 7 1 read-write DIFF8 Differential inputs for channel 8 8 1 read-write DIFF9 Differential inputs for channel 9 9 1 read-write EMR AFEC Extended Mode Register 0x8 32 read-write n 0x0 CMPALL Compare All Channels 9 1 read-write CMPFILTER Compare Event Filtering 12 2 read-write CMPMODE Comparison Mode 0 2 read-write LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 CMPSEL Comparison Selected Channel 3 5 read-write RES Resolution 16 3 read-write NO_AVERAGE 12-bit resolution, AFE sample rate is maximum (no averaging). 0x0 OSR4 13-bit resolution, AFE sample rate divided by 4 (averaging). 0x2 OSR16 14-bit resolution, AFE sample rate divided by 16 (averaging). 0x3 OSR64 15-bit resolution, AFE sample rate divided by 64 (averaging). 0x4 OSR256 16-bit resolution, AFE sample rate divided by 256 (averaging). 0x5 SIGNMODE Sign Mode 28 2 read-write SE_UNSG_DF_SIGN Single-Ended channels: Unsigned conversions.Differential channels: Signed conversions. 0x0 SE_SIGN_DF_UNSG Single-Ended channels: Signed conversions.Differential channels: Unsigned conversions. 0x1 ALL_UNSIGNED All channels: Unsigned conversions. 0x2 ALL_SIGNED All channels: Signed conversions. 0x3 STM Single Trigger Mode 25 1 read-write TAG TAG of the AFEC_LDCR 24 1 read-write IDR AFEC Interrupt Disable Register 0x28 32 write-only n COMPE Comparison Event Interrupt Disable 26 1 write-only DRDY Data Ready Interrupt Disable 24 1 write-only EOC0 End of Conversion Interrupt Disable 0 0 1 write-only EOC1 End of Conversion Interrupt Disable 1 1 1 write-only EOC10 End of Conversion Interrupt Disable 10 10 1 write-only EOC11 End of Conversion Interrupt Disable 11 11 1 write-only EOC2 End of Conversion Interrupt Disable 2 2 1 write-only EOC3 End of Conversion Interrupt Disable 3 3 1 write-only EOC4 End of Conversion Interrupt Disable 4 4 1 write-only EOC5 End of Conversion Interrupt Disable 5 5 1 write-only EOC6 End of Conversion Interrupt Disable 6 6 1 write-only EOC7 End of Conversion Interrupt Disable 7 7 1 write-only EOC8 End of Conversion Interrupt Disable 8 8 1 write-only EOC9 End of Conversion Interrupt Disable 9 9 1 write-only GOVRE General Overrun Error Interrupt Disable 25 1 write-only TEMPCHG Temperature Change Interrupt Disable 30 1 write-only IER AFEC Interrupt Enable Register 0x24 32 write-only n COMPE Comparison Event Interrupt Enable 26 1 write-only DRDY Data Ready Interrupt Enable 24 1 write-only EOC0 End of Conversion Interrupt Enable 0 0 1 write-only EOC1 End of Conversion Interrupt Enable 1 1 1 write-only EOC10 End of Conversion Interrupt Enable 10 10 1 write-only EOC11 End of Conversion Interrupt Enable 11 11 1 write-only EOC2 End of Conversion Interrupt Enable 2 2 1 write-only EOC3 End of Conversion Interrupt Enable 3 3 1 write-only EOC4 End of Conversion Interrupt Enable 4 4 1 write-only EOC5 End of Conversion Interrupt Enable 5 5 1 write-only EOC6 End of Conversion Interrupt Enable 6 6 1 write-only EOC7 End of Conversion Interrupt Enable 7 7 1 write-only EOC8 End of Conversion Interrupt Enable 8 8 1 write-only EOC9 End of Conversion Interrupt Enable 9 9 1 write-only GOVRE General Overrun Error Interrupt Enable 25 1 write-only TEMPCHG Temperature Change Interrupt Enable 30 1 write-only IMR AFEC Interrupt Mask Register 0x2C 32 read-only n 0x0 COMPE Comparison Event Interrupt Mask 26 1 read-only DRDY Data Ready Interrupt Mask 24 1 read-only EOC0 End of Conversion Interrupt Mask 0 0 1 read-only EOC1 End of Conversion Interrupt Mask 1 1 1 read-only EOC10 End of Conversion Interrupt Mask 10 10 1 read-only EOC11 End of Conversion Interrupt Mask 11 11 1 read-only EOC2 End of Conversion Interrupt Mask 2 2 1 read-only EOC3 End of Conversion Interrupt Mask 3 3 1 read-only EOC4 End of Conversion Interrupt Mask 4 4 1 read-only EOC5 End of Conversion Interrupt Mask 5 5 1 read-only EOC6 End of Conversion Interrupt Mask 6 6 1 read-only EOC7 End of Conversion Interrupt Mask 7 7 1 read-only EOC8 End of Conversion Interrupt Mask 8 8 1 read-only EOC9 End of Conversion Interrupt Mask 9 9 1 read-only GOVRE General Overrun Error Interrupt Mask 25 1 read-only TEMPCHG Temperature Change Interrupt Mask 30 1 read-only ISR AFEC Interrupt Status Register 0x30 32 read-only n 0x0 COMPE Comparison Error (cleared by reading AFEC_ISR) 26 1 read-only DRDY Data Ready (cleared by reading AFEC_LCDR) 24 1 read-only EOC0 End of Conversion 0 (cleared by reading AFEC_CDRx) 0 1 read-only EOC1 End of Conversion 1 (cleared by reading AFEC_CDRx) 1 1 read-only EOC10 End of Conversion 10 (cleared by reading AFEC_CDRx) 10 1 read-only EOC11 End of Conversion 11 (cleared by reading AFEC_CDRx) 11 1 read-only EOC2 End of Conversion 2 (cleared by reading AFEC_CDRx) 2 1 read-only EOC3 End of Conversion 3 (cleared by reading AFEC_CDRx) 3 1 read-only EOC4 End of Conversion 4 (cleared by reading AFEC_CDRx) 4 1 read-only EOC5 End of Conversion 5 (cleared by reading AFEC_CDRx) 5 1 read-only EOC6 End of Conversion 6 (cleared by reading AFEC_CDRx) 6 1 read-only EOC7 End of Conversion 7 (cleared by reading AFEC_CDRx) 7 1 read-only EOC8 End of Conversion 8 (cleared by reading AFEC_CDRx) 8 1 read-only EOC9 End of Conversion 9 (cleared by reading AFEC_CDRx) 9 1 read-only GOVRE General Overrun Error (cleared by reading AFEC_ISR) 25 1 read-only TEMPCHG Temperature Change (cleared on read) 30 1 read-only LCDR AFEC Last Converted Data Register 0x20 32 read-only n 0x0 CHNB Channel Number 24 4 read-only LDATA Last Data Converted 0 16 read-only MR AFEC Mode Register 0x4 32 read-write n 0x0 FREERUN Free Run Mode 7 1 read-write OFF Normal mode 0 ON Free Run mode: Never wait for any trigger. 1 FWUP Fast Wake-up 6 1 read-write OFF Normal Sleep mode: The sleep mode is defined by the SLEEP bit. 0 ON Fast wake-up Sleep mode: The voltage reference is ON between conversions and AFE is OFF. 1 ONE One 23 1 read-write PRESCAL Prescaler Rate Selection 8 8 read-write SLEEP Sleep Mode 5 1 read-write NORMAL Normal mode: The AFE and reference voltage circuitry are kept ON between conversions. 0 SLEEP Sleep mode: The AFE and reference voltage circuitry are OFF between conversions. 1 STARTUP Start-up Time 16 4 read-write SUT0 0 periods of AFE clock 0x0 SUT8 8 periods of AFE clock 0x1 SUT16 16 periods of AFE clock 0x2 SUT24 24 periods of AFE clock 0x3 SUT64 64 periods of AFE clock 0x4 SUT80 80 periods of AFE clock 0x5 SUT96 96 periods of AFE clock 0x6 SUT112 112 periods of AFE clock 0x7 SUT512 512 periods of AFE clock 0x8 SUT576 576 periods of AFE clock 0x9 SUT640 640 periods of AFE clock 0xA SUT704 704 periods of AFE clock 0xB SUT768 768 periods of AFE clock 0xC SUT832 832 periods of AFE clock 0xD SUT896 896 periods of AFE clock 0xE SUT960 960 periods of AFE clock 0xF TRACKTIM Tracking Time 24 4 read-write TRANSFER Transfer Period 28 2 read-write TRGEN Trigger Enable 0 1 read-write DIS Hardware triggers are disabled. Starting a conversion is only possible by software. 0 EN Hardware trigger selected by TRGSEL field is enabled. 1 TRGSEL Trigger Selection 1 3 read-write AFEC_TRIG0 AFE0_ADTRG for AFEC0 / AFE1_ADTRG for AFEC1 0x0 AFEC_TRIG1 TIOA Output of the Timer Counter Channel 0 for AFEC0/TIOA Output of the Timer Counter Channel 3 for AFEC1 0x1 AFEC_TRIG2 TIOA Output of the Timer Counter Channel 1 for AFEC0/TIOA Output of the Timer Counter Channel 4 for AFEC1 0x2 AFEC_TRIG3 TIOA Output of the Timer Counter Channel 2 for AFEC0/TIOA Output of the Timer Counter Channel 5 for AFEC1 0x3 AFEC_TRIG4 PWM0 event line 0 for AFEC0 / PWM1 event line 0 for AFEC1 0x4 AFEC_TRIG5 PWM0 event line 1 for AFEC0 / PWM1 event line 1 for AFEC1 0x5 AFEC_TRIG6 Analog Comparator 0x6 USEQ User Sequence Enable 31 1 read-write NUM_ORDER Normal mode: The controller converts channels in a simple numeric order. 0 REG_ORDER User Sequence mode: The sequence respects what is defined in AFEC_SEQ1R and AFEC_SEQ1R. 1 OVER AFEC Overrun Status Register 0x4C 32 read-only n 0x0 OVRE0 Overrun Error 0 0 1 read-only OVRE1 Overrun Error 1 1 1 read-only OVRE10 Overrun Error 10 10 1 read-only OVRE11 Overrun Error 11 11 1 read-only OVRE2 Overrun Error 2 2 1 read-only OVRE3 Overrun Error 3 3 1 read-only OVRE4 Overrun Error 4 4 1 read-only OVRE5 Overrun Error 5 5 1 read-only OVRE6 Overrun Error 6 6 1 read-only OVRE7 Overrun Error 7 7 1 read-only OVRE8 Overrun Error 8 8 1 read-only OVRE9 Overrun Error 9 9 1 read-only SEQ1R AFEC Channel Sequence 1 Register 0xC 32 read-write n 0x0 USCH0 User Sequence Number 0 0 4 read-write USCH1 User Sequence Number 1 4 4 read-write USCH2 User Sequence Number 2 8 4 read-write USCH3 User Sequence Number 3 12 4 read-write USCH4 User Sequence Number 4 16 4 read-write USCH5 User Sequence Number 5 20 4 read-write USCH6 User Sequence Number 6 24 4 read-write USCH7 User Sequence Number 7 28 4 read-write SEQ2R AFEC Channel Sequence 2 Register 0x10 32 read-write n 0x0 USCH10 User Sequence Number 10 8 4 read-write USCH11 User Sequence Number 11 12 4 read-write USCH12 User Sequence Number 12 16 4 read-write USCH13 User Sequence Number 13 20 4 read-write USCH14 User Sequence Number 14 24 4 read-write USCH15 User Sequence Number 15 28 4 read-write USCH8 User Sequence Number 8 0 4 read-write USCH9 User Sequence Number 9 4 4 read-write SHMR AFEC Sample and Hold Mode Register 0xA0 32 read-write n 0x0 DUAL0 Dual Sample and Hold for channel 0 0 1 read-write DUAL1 Dual Sample and Hold for channel 1 1 1 read-write DUAL10 Dual Sample and Hold for channel 10 10 1 read-write DUAL11 Dual Sample and Hold for channel 11 11 1 read-write DUAL2 Dual Sample and Hold for channel 2 2 1 read-write DUAL3 Dual Sample and Hold for channel 3 3 1 read-write DUAL4 Dual Sample and Hold for channel 4 4 1 read-write DUAL5 Dual Sample and Hold for channel 5 5 1 read-write DUAL6 Dual Sample and Hold for channel 6 6 1 read-write DUAL7 Dual Sample and Hold for channel 7 7 1 read-write DUAL8 Dual Sample and Hold for channel 8 8 1 read-write DUAL9 Dual Sample and Hold for channel 9 9 1 read-write TEMPCWR AFEC Temperature Compare Window Register 0x74 32 read-write n 0x0 THIGHTHRES Temperature High Threshold 16 16 read-write TLOWTHRES Temperature Low Threshold 0 16 read-write TEMPMR AFEC Temperature Sensor Mode Register 0x70 32 read-write n 0x0 RTCT Temperature Sensor RTC Trigger Mode 0 1 read-write TEMPCMPMOD Temperature Comparison Mode 4 2 read-write LOW Generates an event when the converted data is lower than the low threshold of the window. 0x0 HIGH Generates an event when the converted data is higher than the high threshold of the window. 0x1 IN Generates an event when the converted data is in the comparison window. 0x2 OUT Generates an event when the converted data is out of the comparison window. 0x3 WPMR AFEC Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protect KEY 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x414443 WPSR AFEC Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protect Violation Status 0 1 read-only WPVSRC Write Protect Violation Source 8 16 read-only CHIPID Chip Identifier CHIPID 0x0 0x0 0x8 registers n CIDR Chip ID Register 0x0 32 read-only n 0x0 0x0 ARCH Architecture Identifier 20 8 ARCHSelect SAME70 SAM E70 16 SAMS70 SAM S70 17 SAMV71 SAM V71 18 SAMV70 SAM V70 19 EPROC Embedded Processor 5 3 EPROCSelect SAMx7 Cortex-M7 0 ARM946ES ARM946ES 1 ARM7TDMI ARM7TDMI 2 CM3 Cortex-M3 3 ARM920T ARM920T 4 ARM926EJS ARM926EJS 5 CA5 Cortex-A5 6 CM4 Cortex-M4 7 EXT Extension Flag 31 1 NVPSIZ Nonvolatile Program Memory Size 8 4 NVPSIZSelect NONE None 0 _8K 8 Kbytes 1 _512K 512 Kbytes 10 _1024K 1024 Kbytes 12 _2048K 2048 Kbytes 14 _16K 16 Kbytes 2 _32K 32 Kbytes 3 _64K 64 Kbytes 5 _128K 128 Kbytes 7 _160K 160 Kbytes 8 _256K 256 Kbytes 9 NVPSIZ2 Second Nonvolatile Program Memory Size 12 4 NVPSIZ2Select NONE None 0 _8K 8 Kbytes 1 _512K 512 Kbytes 10 _1024K 1024 Kbytes 12 _2048K 2048 Kbytes 14 _16K 16 Kbytes 2 _32K 32 Kbytes 3 _64K 64 Kbytes 5 _128K 128 Kbytes 7 _256K 256 Kbytes 9 NVPTYP Nonvolatile Program Memory Type 28 3 NVPTYPSelect ROM ROM 0 ROMLESS ROMless or on-chip Flash 1 FLASH Embedded Flash Memory 2 ROM_FLASH ROM and Embedded Flash Memory- NVPSIZ is ROM size- NVPSIZ2 is Flash size 3 SRAM SRAM emulating ROM 4 SRAMSIZ Internal SRAM Size 16 4 SRAMSIZSelect _48K 48 Kbytes 0 _192K 192 Kbytes 1 _32K 32 Kbytes 10 _64K 64 Kbytes 11 _128K 128 Kbytes 12 _256K 256 Kbytes 13 _96K 96 Kbytes 14 _512K 512 Kbytes 15 _384K 384 Kbytes 2 _6K 6 Kbytes 3 _24K 24 Kbytes 4 _4K 4 Kbytes 5 _80K 80 Kbytes 6 _160K 160 Kbytes 7 _8K 8 Kbytes 8 _16K 16 Kbytes 9 VERSION Version of the Device 0 5 EXID Chip ID Extension Register 0x4 32 read-only n 0x0 0x0 EXID Chip ID Extension 0 32 DACC Digital-to-Analog Converter Controller DACC 0x0 0x0 0x4000 registers n DACC 30 ACR Analog Current Register 0x94 32 read-write n 0x0 0x0 IBCTLCH0 Analog Output Current Control 0 2 IBCTLCH1 Analog Output Current Control 2 2 CDR0 Conversion Data Register 0x1C 32 write-only n DATA0 Data to Convert for channel 0 0 16 write-only DATA1 Data to Convert for channel 1 16 16 write-only CDR1 Conversion Data Register 0x20 32 write-only n DATA0 Data to Convert for channel 0 0 16 write-only DATA1 Data to Convert for channel 1 16 16 write-only CDR[0] Conversion Data Register 0 0x38 32 write-only n 0x0 0x0 DATA0 Data to Convert for channel 0 0 16 DATA1 Data to Convert for channel 1 16 16 CDR[1] Conversion Data Register 0 0x58 32 write-only n 0x0 0x0 DATA0 Data to Convert for channel 0 0 16 DATA1 Data to Convert for channel 1 16 16 CHDR Channel Disable Register 0x14 32 write-only n 0x0 0x0 CH0 Channel 0 Disable 0 1 CH1 Channel 1 Disable 1 1 CHER Channel Enable Register 0x10 32 write-only n 0x0 0x0 CH0 Channel 0 Enable 0 1 CH1 Channel 1 Enable 1 1 CHSR Channel Status Register 0x18 32 read-only n 0x0 0x0 CH0 Channel 0 Status 0 1 CH1 Channel 1 Status 1 1 DACRDY0 DAC Ready Flag 8 1 DACRDY1 DAC Ready Flag 9 1 CR Control Register 0x0 32 write-only n 0x0 0x0 SWRST Software Reset 0 1 IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 EOC0 End of Conversion Interrupt Disable of channel 0 4 1 EOC1 End of Conversion Interrupt Disable of channel 1 5 1 TXRDY0 Transmit Ready Interrupt Disable of channel 0 0 1 TXRDY1 Transmit Ready Interrupt Disable of channel 1 1 1 IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 EOC0 End of Conversion Interrupt Enable of channel 0 4 1 EOC1 End of Conversion Interrupt Enable of channel 1 5 1 TXRDY0 Transmit Ready Interrupt Enable of channel 0 0 1 TXRDY1 Transmit Ready Interrupt Enable of channel 1 1 1 IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 EOC0 End of Conversion Interrupt Mask of channel 0 4 1 EOC1 End of Conversion Interrupt Mask of channel 1 5 1 TXRDY0 Transmit Ready Interrupt Mask of channel 0 0 1 TXRDY1 Transmit Ready Interrupt Mask of channel 1 1 1 ISR Interrupt Status Register 0x30 32 read-only n 0x0 0x0 EOC0 End of Conversion Interrupt Flag of channel 0 4 1 EOC1 End of Conversion Interrupt Flag of channel 1 5 1 TXRDY0 Transmit Ready Interrupt Flag of channel 0 0 1 TXRDY1 Transmit Ready Interrupt Flag of channel 1 1 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 DIFF Differential Mode 23 1 DIFFSelect DISABLED DAC0 and DAC1 are single-ended outputs. 0 ENABLED DACP and DACN are differential outputs. The differential level is configured by the channel 0 value. 1 MAXS0 Max Speed Mode for Channel 0 0 1 MAXS0Select TRIG_EVENT External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) 0 MAXIMUM Max speed mode enabled. 1 MAXS1 Max Speed Mode for Channel 1 1 1 MAXS1Select TRIG_EVENT External trigger mode or Free-running mode enabled. (See TRGENx.DACC_TRIGR.) 0 MAXIMUM Max speed mode enabled. 1 PRESCALER Peripheral Clock to DAC Clock Ratio 24 4 WORD Word Transfer Mode 4 1 WORDSelect DISABLED One data to convert is written to the FIFO per access to DACC. 0 ENABLED Two data to convert are written to the FIFO per access to DACC (reduces the number of requests to DMA and the number of system bus accesses). 1 ZERO Must always be written to 0. 5 1 TRIGR Trigger Register 0x8 32 read-write n 0x0 0x0 OSR0 Over Sampling Ratio of Channel 0 16 3 OSR0Select OSR_1 OSR = 1 0 OSR_2 OSR = 2 1 OSR_4 OSR = 4 2 OSR_8 OSR = 8 3 OSR_16 OSR = 16 4 OSR_32 OSR = 32 5 OSR1 Over Sampling Ratio of Channel 1 20 3 OSR1Select OSR_1 OSR = 1 0 OSR_2 OSR = 2 1 OSR_4 OSR = 4 2 OSR_8 OSR = 8 3 OSR_16 OSR = 16 4 OSR_32 OSR = 32 5 TRGEN0 Trigger Enable of Channel 0 0 1 TRGEN0Select DIS External trigger mode disabled. DACC is in Free-running mode or Max speed mode. 0 EN External trigger mode enabled. 1 TRGEN1 Trigger Enable of Channel 1 1 1 TRGEN1Select DIS External trigger mode disabled. DACC is in Free-running mode or Max speed mode. 0 EN External trigger mode enabled. 1 TRGSEL0 Trigger Selection of Channel 0 4 3 TRGSEL0Select TRGSEL0 DATRG 0 TRGSEL1 TC0 output 1 TRGSEL2 TC1 output 2 TRGSEL3 TC2 output 3 TRGSEL4 PWM0 event 0 4 TRGSEL5 PWM0 event 1 5 TRGSEL6 PWM1 event 0 6 TRGSEL7 PWM1 event 1 7 TRGSEL1 Trigger Selection of Channel 1 8 3 TRGSEL1Select TRGSEL0 DATRG 0 TRGSEL1 TC0 output 1 TRGSEL2 TC1 output 2 TRGSEL3 TC2 output 3 TRGSEL4 PWM0 event 0 4 TRGSEL5 PWM0 event 1 5 TRGSEL6 PWM1 event 0 6 TRGSEL7 PWM1 event 1 7 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protect Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of bit WPEN.Always reads as 0. 4473155 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 8 EFC Embedded Flash Controller EFC 0x0 0x0 0xE8 registers n EFC 6 EEFC_FCR EEFC Flash Command Register 0x4 32 write-only n 0x0 0x0 FARG Flash Command Argument 8 16 FCMD Flash Command 0 8 FCMDSelect GETD Get Flash descriptor 0 WP Write page 1 GLB Get lock bit 10 SGPB Set GPNVM bit 11 CGPB Clear GPNVM bit 12 GGPB Get GPNVM bit 13 STUI Start read unique identifier 14 SPUI Stop read unique identifier 15 GCALB Get CALIB bit 16 ES Erase sector 17 WUS Write user signature 18 EUS Erase user signature 19 WPL Write page and lock 2 STUS Start read user signature 20 SPUS Stop read user signature 21 EWP Erase page and write page 3 EWPL Erase page and write page then lock 4 EA Erase all 5 EPA Erase pages 7 SLB Set lock bit 8 CLB Clear lock bit 9 FKEY Flash Writing Protection Key 24 8 FKEYSelect PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 90 EEFC_FMR EEFC Flash Mode Register 0x0 32 read-write n 0x0 0x0 CLOE Code Loop Optimization Enable 26 1 FRDY Flash Ready Interrupt Enable 0 1 FWS Flash Wait State 8 4 SCOD Sequential Code Optimization Disable 16 1 EEFC_FRR EEFC Flash Result Register 0xC 32 read-only n 0x0 0x0 FVALUE Flash Result Value 0 32 EEFC_FSR EEFC Flash Status Register 0x8 32 read-only n 0x0 0x0 FCMDE Flash Command Error Status (cleared on read or by writing EEFC_FCR) 1 1 FLERR Flash Error Status (cleared when a programming operation starts) 3 1 FLOCKE Flash Lock Error Status (cleared on read) 2 1 FRDY Flash Ready Status (cleared when Flash is busy) 0 1 MECCELSB Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) 17 1 MECCEMSB Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) 19 1 UECCELSB Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) 16 1 UECCEMSB Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) 18 1 EEFC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 4539971 FCR EEFC Flash Command Register 0x4 32 write-only n FARG Flash Command Argument 8 16 write-only FCMD Flash Command 0 8 write-only GETD Get Flash descriptor 0x00 WP Write page 0x01 WPL Write page and lock 0x02 EWP Erase page and write page 0x03 EWPL Erase page and write page then lock 0x04 EA Erase all 0x05 EPA Erase pages 0x07 SLB Set lock bit 0x08 CLB Clear lock bit 0x09 GLB Get lock bit 0x0A SGPB Set GPNVM bit 0x0B CGPB Clear GPNVM bit 0x0C GGPB Get GPNVM bit 0x0D STUI Start read unique identifier 0x0E SPUI Stop read unique identifier 0x0F GCALB Get CALIB bit 0x10 ES Erase sector 0x11 WUS Write user signature 0x12 EUS Erase user signature 0x13 STUS Start read user signature 0x14 SPUS Stop read user signature 0x15 FKEY Flash Writing Protection Key 24 8 write-only PASSWD The 0x5A value enables the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. 0x5A FMR EEFC Flash Mode Register 0x0 32 read-write n 0x0 CLOE Code Loop Optimization Enable 26 1 read-write FRDY Flash Ready Interrupt Enable 0 1 read-write FWS Flash Wait State 8 4 read-write SCOD Sequential Code Optimization Disable 16 1 read-write FRR EEFC Flash Result Register 0xC 32 read-only n 0x0 FVALUE Flash Result Value 0 32 read-only FSR EEFC Flash Status Register 0x8 32 read-only n 0x0 FCMDE Flash Command Error Status (cleared on read or by writing EEFC_FCR) 1 1 read-only FLERR Flash Error Status (cleared when a programming operation starts) 3 1 read-only FLOCKE Flash Lock Error Status (cleared on read) 2 1 read-only FRDY Flash Ready Status (cleared when Flash is busy) 0 1 read-only MECCELSB Multiple ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) 17 1 read-only MECCEMSB Multiple ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) 19 1 read-only UECCELSB Unique ECC Error on LSB Part of the Memory Flash Data Bus (cleared on read) 16 1 read-only UECCEMSB Unique ECC Error on MSB Part of the Memory Flash Data Bus (cleared on read) 18 1 read-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x454643 FPU Floating Point Unit FPU 0x0 0x0 0x1C registers n FPU 61 IXC 68 FPCAR Floating-point Context Address Register 0x8 32 read-write n 0x0 0x0 ADDRESS The location of the unpopulated floating-point register space allocated on an exception stack frame. 3 29 FPCCR Floating-point Context Control Register 0x4 32 read-write n 0x0 0x0 ASPEN Enables CONTROL.FPCA setting on execution of a floating-point instruction. This results in automatic hardware state preservation and restoration, for floating-point context, on exception entry and exit. 31 1 BFRDY BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated. 6 1 HFRDY Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated. 4 1 LSPACT Lazy state preservation is active. Floating-point stack frame has been allocated but saving state to it has been deferred. 0 1 LSPEN Enable automatic lazy state preservation for floating-point context. 30 1 MMRDY MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated. 5 1 MONRDY DebugMonitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated. 8 1 THREAD Mode was Thread Mode when the floating-point stack frame was allocated. 3 1 USER Privilege level was user when the floating-point stack frame was allocated. 1 1 FPDSCR Floating-point Default Status Control Register 0xC 32 read-write n 0x0 0x0 AHP Default value for FPSCR.AHP. 26 1 DN Default value for FPSCR.DN. 25 1 FZ Default value for FPSCR.FZ. 24 1 RMode Default value for FPSCR.RMode. 22 2 MVFR0 Media and VFP Feature Register 0 0x10 32 read-only n 0x0 0x0 A_SIMD_registers Indicates the size of the FP register bank 0 4 Divide Indicates the hardware support for FP divide operations 16 4 Double_precision Indicates the hardware support for FP double-precision operations 8 4 FP_excep_trapping Indicates whether the FP hardware implementation supports exception trapping 12 4 FP_rounding_modes Indicates the rounding modes supported by the FP floating-point hardware 28 4 Short_vectors Indicates the hardware support for FP short vectors 24 4 Single_precision Indicates the hardware support for FP single-precision operations 4 4 Square_root Indicates the hardware support for FP square root operations 20 4 MVFR1 Media and VFP Feature Register 1 0x14 32 read-only n 0x0 0x0 D_NaN_mode Indicates whether the FP hardware implementation supports only the Default NaN mode 4 4 FP_fused_MAC Indicates whether the FP supports fused multiply accumulate operations 28 4 FP_HPFP Floating Point Half-Precision and double-precision 24 4 FtZ_mode Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation 0 4 MVFR2 Media and VFP Feature Register 2 0x18 32 read-only n 0x0 0x0 VFP_Misc Indicates the hardware support for FP miscellaneous features 4 4 GMAC Gigabit Ethernet MAC GMAC 0x0 0x0 0x4000 registers n GMAC 39 GMAC_Q1 66 GMAC_Q2 67 AE Alignment Errors Register 0x19C 32 read-only n 0x0 0x0 AER Alignment Errors 0 10 BCFR Broadcast Frames Received Register 0x15C 32 read-only n 0x0 0x0 BFRX Broadcast Frames Received without Error 0 32 BCFT Broadcast Frames Transmitted Register 0x10C 32 read-only n 0x0 0x0 BFTX Broadcast Frames Transmitted without Error 0 32 BFR64 64 Byte Frames Received Register 0x168 32 read-only n 0x0 0x0 NFRX 64 Byte Frames Received without Error 0 32 BFT64 64 Byte Frames Transmitted Register 0x118 32 read-only n 0x0 0x0 NFTX 64 Byte Frames Transmitted without Error 0 32 CBSCR Credit-Based Shaping Control Register 0x4BC 32 read-write n 0x0 0x0 QAE Queue A CBS Enable 1 1 QBE Queue B CBS Enable 0 1 CBSISQA Credit-Based Shaping IdleSlope Register for Queue A 0x4C0 32 read-write n 0x0 0x0 IS IdleSlope 0 32 CBSISQB Credit-Based Shaping IdleSlope Register for Queue B 0x4C4 32 read-write n 0x0 0x0 IS IdleSlope 0 32 CSE Carrier Sense Errors Register 0x14C 32 read-only n 0x0 0x0 CSR Carrier Sense Error 0 10 DCFGR DMA Configuration Register 0x10 32 read-write n 0x0 0x0 DDRP DMA Discard Receive Packets 24 1 DRBS DMA Receive Buffer Size 16 8 ESMA Endian Swap Mode Enable for Management Descriptor Accesses 6 1 ESPA Endian Swap Mode Enable for Packet Data Accesses 7 1 FBLDO Fixed Burst Length for DMA Data Operations: 0 5 FBLDOSelect SINGLE 00001: Always use SINGLE AHB bursts 1 INCR16 1xxxx: Attempt to use INCR16 AHB bursts 16 INCR4 001xx: Attempt to use INCR4 AHB bursts (Default) 4 INCR8 01xxx: Attempt to use INCR8 AHB bursts 8 RXBMS Receiver Packet Buffer Memory Size Select 8 2 RXBMSSelect EIGHTH 4/8 Kbyte Memory Size 0 QUARTER 4/4 Kbytes Memory Size 1 HALF 4/2 Kbytes Memory Size 2 FULL 4 Kbytes Memory Size 3 TXCOEN Transmitter Checksum Generation Offload Enable 11 1 TXPBMS Transmitter Packet Buffer Memory Size Select 10 1 DTF Deferred Transmission Frames Register 0x148 32 read-only n 0x0 0x0 DEFT Deferred Transmission 0 18 EC Excessive Collisions Register 0x140 32 read-only n 0x0 0x0 XCOL Excessive Collisions 0 10 EFRN PTP Event Frame Received Nanoseconds Register 0x1EC 32 read-only n 0x0 0x0 RUD Register Update 0 30 EFRSH PTP Event Frame Received Seconds High Register 0xEC 32 read-only n 0x0 0x0 RUD Register Update 0 16 EFRSL PTP Event Frame Received Seconds Low Register 0x1E8 32 read-only n 0x0 0x0 RUD Register Update 0 32 EFTN PTP Event Frame Transmitted Nanoseconds Register 0x1E4 32 read-only n 0x0 0x0 RUD Register Update 0 30 EFTSH PTP Event Frame Transmitted Seconds High Register 0xE8 32 read-only n 0x0 0x0 RUD Register Update 0 16 EFTSL PTP Event Frame Transmitted Seconds Low Register 0x1E0 32 read-only n 0x0 0x0 RUD Register Update 0 32 FCSE Frame Check Sequence Errors Register 0x190 32 read-only n 0x0 0x0 FCKR Frame Check Sequence Errors 0 10 FR Frames Received Register 0x158 32 read-only n 0x0 0x0 FRX Frames Received without Error 0 32 FT Frames Transmitted Register 0x108 32 read-only n 0x0 0x0 FTX Frames Transmitted without Error 0 32 GTBFT1518 Greater Than 1518 Byte Frames Transmitted Register 0x130 32 read-only n 0x0 0x0 NFTX Greater than 1518 Byte Frames Transmitted without Error 0 32 HRB Hash Register Bottom 0x80 32 read-write n 0x0 0x0 ADDR Hash Address 0 32 HRT Hash Register Top 0x84 32 read-write n 0x0 0x0 ADDR Hash Address 0 32 IDR Interrupt Disable Register 0x2C 32 write-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 DRQFT PTP Delay Request Frame Transmitted 20 1 EXINT External Interrupt 15 1 HRESP HRESP Not OK 11 1 MFS Management Frame Sent 0 1 PDRQFR PDelay Request Frame Received 22 1 PDRQFT PDelay Request Frame Transmitted 24 1 PDRSFR PDelay Response Frame Received 23 1 PDRSFT PDelay Response Frame Transmitted 25 1 PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 PFTR Pause Frame Transmitted 14 1 PTZ Pause Time Zero 13 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 SFR PTP Sync Frame Received 19 1 SFT PTP Sync Frame Transmitted 21 1 SRI TSU Seconds Register Increment 26 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 TUR Transmit Underrun 4 1 TXUBR TX Used Bit Read 3 1 WOL Wake On LAN 28 1 IDRPQ0 Interrupt Disable Register Priority Queue (index = 1) 0x620 32 write-only n HRESP HRESP Not OK 11 1 write-only RCOMP Receive Complete 1 1 write-only RLEX Retry Limit Exceeded or Late Collision 5 1 write-only ROVR Receive Overrun 10 1 write-only RXUBR RX Used Bit Read 2 1 write-only TCOMP Transmit Complete 7 1 write-only TFC Transmit Frame Corruption Due to AHB Error 6 1 write-only IDRPQ1 Interrupt Disable Register Priority Queue (index = 1) 0x624 32 write-only n HRESP HRESP Not OK 11 1 write-only RCOMP Receive Complete 1 1 write-only RLEX Retry Limit Exceeded or Late Collision 5 1 write-only ROVR Receive Overrun 10 1 write-only RXUBR RX Used Bit Read 2 1 write-only TCOMP Transmit Complete 7 1 write-only TFC Transmit Frame Corruption Due to AHB Error 6 1 write-only IDRPQ[0] Interrupt Disable Register Priority Queue (index = 1) 0 0xC38 32 write-only n 0x0 0x0 HRESP HRESP Not OK 11 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 IDRPQ[1] Interrupt Disable Register Priority Queue (index = 1) 0 0x1258 32 write-only n 0x0 0x0 HRESP HRESP Not OK 11 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 IER Interrupt Enable Register 0x28 32 write-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 DRQFT PTP Delay Request Frame Transmitted 20 1 EXINT External Interrupt 15 1 HRESP HRESP Not OK 11 1 MFS Management Frame Sent 0 1 PDRQFR PDelay Request Frame Received 22 1 PDRQFT PDelay Request Frame Transmitted 24 1 PDRSFR PDelay Response Frame Received 23 1 PDRSFT PDelay Response Frame Transmitted 25 1 PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 PFTR Pause Frame Transmitted 14 1 PTZ Pause Time Zero 13 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 SFR PTP Sync Frame Received 19 1 SFT PTP Sync Frame Transmitted 21 1 SRI TSU Seconds Register Increment 26 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 TUR Transmit Underrun 4 1 TXUBR TX Used Bit Read 3 1 WOL Wake On LAN 28 1 IERPQ0 Interrupt Enable Register Priority Queue (index = 1) 0x600 32 write-only n HRESP HRESP Not OK 11 1 write-only RCOMP Receive Complete 1 1 write-only RLEX Retry Limit Exceeded or Late Collision 5 1 write-only ROVR Receive Overrun 10 1 write-only RXUBR RX Used Bit Read 2 1 write-only TCOMP Transmit Complete 7 1 write-only TFC Transmit Frame Corruption Due to AHB Error 6 1 write-only IERPQ1 Interrupt Enable Register Priority Queue (index = 1) 0x604 32 write-only n HRESP HRESP Not OK 11 1 write-only RCOMP Receive Complete 1 1 write-only RLEX Retry Limit Exceeded or Late Collision 5 1 write-only ROVR Receive Overrun 10 1 write-only RXUBR RX Used Bit Read 2 1 write-only TCOMP Transmit Complete 7 1 write-only TFC Transmit Frame Corruption Due to AHB Error 6 1 write-only IERPQ[0] Interrupt Enable Register Priority Queue (index = 1) 0 0xBF8 32 write-only n 0x0 0x0 HRESP HRESP Not OK 11 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 IERPQ[1] Interrupt Enable Register Priority Queue (index = 1) 0 0x11F8 32 write-only n 0x0 0x0 HRESP HRESP Not OK 11 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 IHCE IP Header Checksum Errors Register 0x1A8 32 read-only n 0x0 0x0 HCKER IP Header Checksum Errors 0 8 IMR Interrupt Mask Register 0x30 32 read-write n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 DRQFT PTP Delay Request Frame Transmitted 20 1 EXINT External Interrupt 15 1 HRESP HRESP Not OK 11 1 MFS Management Frame Sent 0 1 PDRQFR PDelay Request Frame Received 22 1 PDRQFT PDelay Request Frame Transmitted 24 1 PDRSFR PDelay Response Frame Received 23 1 PDRSFT PDelay Response Frame Transmitted 25 1 PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 PFTR Pause Frame Transmitted 14 1 PTZ Pause Time Zero 13 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 SFR PTP Sync Frame Received 19 1 SFT PTP Sync Frame Transmitted 21 1 SRI TSU Seconds Register Increment 26 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 TUR Transmit Underrun 4 1 TXUBR TX Used Bit Read 3 1 WOL Wake On LAN 28 1 IMRPQ0 Interrupt Mask Register Priority Queue (index = 1) 0x640 32 read-write n AHB AHB Error 6 1 read-write HRESP HRESP Not OK 11 1 read-write RCOMP Receive Complete 1 1 read-write RLEX Retry Limit Exceeded or Late Collision 5 1 read-write ROVR Receive Overrun 10 1 read-write RXUBR RX Used Bit Read 2 1 read-write TCOMP Transmit Complete 7 1 read-write IMRPQ1 Interrupt Mask Register Priority Queue (index = 1) 0x644 32 read-write n AHB AHB Error 6 1 read-write HRESP HRESP Not OK 11 1 read-write RCOMP Receive Complete 1 1 read-write RLEX Retry Limit Exceeded or Late Collision 5 1 read-write ROVR Receive Overrun 10 1 read-write RXUBR RX Used Bit Read 2 1 read-write TCOMP Transmit Complete 7 1 read-write IMRPQ[0] Interrupt Mask Register Priority Queue (index = 1) 0 0xC78 32 read-write n 0x0 0x0 AHB AHB Error 6 1 HRESP HRESP Not OK 11 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 TCOMP Transmit Complete 7 1 IMRPQ[1] Interrupt Mask Register Priority Queue (index = 1) 0 0x12B8 32 read-write n 0x0 0x0 AHB AHB Error 6 1 HRESP HRESP Not OK 11 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 TCOMP Transmit Complete 7 1 IPGS IPG Stretch Register 0xBC 32 read-write n 0x0 0x0 FL Frame Length 0 16 ISR Interrupt Status Register 0x24 32 read-only n 0x0 0x0 DRQFR PTP Delay Request Frame Received 18 1 DRQFT PTP Delay Request Frame Transmitted 20 1 HRESP HRESP Not OK 11 1 MFS Management Frame Sent 0 1 PDRQFR PDelay Request Frame Received 22 1 PDRQFT PDelay Request Frame Transmitted 24 1 PDRSFR PDelay Response Frame Received 23 1 PDRSFT PDelay Response Frame Transmitted 25 1 PFNZ Pause Frame with Non-zero Pause Quantum Received 12 1 PFTR Pause Frame Transmitted 14 1 PTZ Pause Time Zero 13 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 SFR PTP Sync Frame Received 19 1 SFT PTP Sync Frame Transmitted 21 1 SRI TSU Seconds Register Increment 26 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 TUR Transmit Underrun 4 1 TXUBR TX Used Bit Read 3 1 WOL Wake On LAN 28 1 ISRPQ0 Interrupt Status Register Priority Queue (index = 1) 0x400 32 read-only n HRESP HRESP Not OK 11 1 read-only RCOMP Receive Complete 1 1 read-only RLEX Retry Limit Exceeded or Late Collision 5 1 read-only ROVR Receive Overrun 10 1 read-only RXUBR RX Used Bit Read 2 1 read-only TCOMP Transmit Complete 7 1 read-only TFC Transmit Frame Corruption Due to AHB Error 6 1 read-only ISRPQ1 Interrupt Status Register Priority Queue (index = 1) 0x404 32 read-only n HRESP HRESP Not OK 11 1 read-only RCOMP Receive Complete 1 1 read-only RLEX Retry Limit Exceeded or Late Collision 5 1 read-only ROVR Receive Overrun 10 1 read-only RXUBR RX Used Bit Read 2 1 read-only TCOMP Transmit Complete 7 1 read-only TFC Transmit Frame Corruption Due to AHB Error 6 1 read-only ISRPQ[0] Interrupt Status Register Priority Queue (index = 1) 0 0x7F8 32 read-only n 0x0 0x0 HRESP HRESP Not OK 11 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 ISRPQ[1] Interrupt Status Register Priority Queue (index = 1) 0 0xBF8 32 read-only n 0x0 0x0 HRESP HRESP Not OK 11 1 RCOMP Receive Complete 1 1 RLEX Retry Limit Exceeded or Late Collision 5 1 ROVR Receive Overrun 10 1 RXUBR RX Used Bit Read 2 1 TCOMP Transmit Complete 7 1 TFC Transmit Frame Corruption Due to AHB Error 6 1 JR Jabbers Received Register 0x18C 32 read-only n 0x0 0x0 JRX Jabbers Received 0 10 LC Late Collisions Register 0x144 32 read-only n 0x0 0x0 LCOL Late Collisions 0 10 LFFE Length Field Frame Errors Register 0x194 32 read-only n 0x0 0x0 LFER Length Field Frame Errors 0 10 MAN PHY Maintenance Register 0x34 32 read-write n 0x0 0x0 CLTTO Clause 22 Operation 30 1 DATA PHY Data 0 16 OP Operation 28 2 PHYA PHY Address 23 5 REGA Register Address 18 5 WTN Write Ten 16 2 WZO Write ZERO 31 1 MCF Multiple Collision Frames Register 0x13C 32 read-only n 0x0 0x0 MCOL Multiple Collision 0 18 MFR Multicast Frames Received Register 0x160 32 read-only n 0x0 0x0 MFRX Multicast Frames Received without Error 0 32 MFT Multicast Frames Transmitted Register 0x110 32 read-only n 0x0 0x0 MFTX Multicast Frames Transmitted without Error 0 32 NCFGR Network Configuration Register 0x4 32 read-write n 0x0 0x0 CAF Copy All Frames 4 1 CLK MDC CLock Division 18 3 CLKSelect MCK_8 MCK divided by 8 (MCK up to 20 MHz) 0 MCK_16 MCK divided by 16 (MCK up to 40 MHz) 1 MCK_32 MCK divided by 32 (MCK up to 80 MHz) 2 MCK_48 MCK divided by 48 (MCK up to 120 MHz) 3 MCK_64 MCK divided by 64 (MCK up to 160 MHz) 4 MCK_96 MCK divided by 96 (MCK up to 240 MHz) 5 DBW Data Bus Width 21 2 DCPF Disable Copy of Pause Frames 23 1 DNVLAN Discard Non-VLAN FRAMES 2 1 EFRHD Enable Frames Received in Half Duplex 25 1 FD Full Duplex 1 1 IPGSEN IP Stretch Enable 28 1 IRXER Ignore IPG GRXER 30 1 IRXFCS Ignore RX FCS 26 1 JFRAME Jumbo Frame Size 3 1 LFERD Length Field Error Frame Discard 16 1 MAXFS 1536 Maximum Frame Size 8 1 MTIHEN Multicast Hash Enable 6 1 NBC No Broadcast 5 1 PEN Pause Enable 13 1 RFCS Remove FCS 17 1 RTY Retry Test 12 1 RXBP Receive Bad Preamble 29 1 RXBUFO Receive Buffer Offset 14 2 RXCOEN Receive Checksum Offload Enable 24 1 SPD Speed 0 1 UNIHEN Unicast Hash Enable 7 1 NCR Network Control Register 0x0 32 read-write n 0x0 0x0 BP Back pressure 8 1 CLRSTAT Clear Statistics Registers 5 1 ENPBPR Enable PFC Priority-based Pause Reception 16 1 FNP Flush Next Packet 18 1 INCSTAT Increment Statistics Registers 6 1 LBL Loop Back Local 1 1 MPE Management Port Enable 4 1 RXEN Receive Enable 2 1 SRTSM Store Receive Time Stamp to Memory 15 1 THALT Transmit Halt 10 1 TSTART Start Transmission 9 1 TXEN Transmit Enable 3 1 TXPBPF Transmit PFC Priority-based Pause Frame 17 1 TXPF Transmit Pause Frame 11 1 TXZQPF Transmit Zero Quantum Pause Frame 12 1 WESTAT Write Enable for Statistics Registers 7 1 NSC 1588 Timer Nanosecond Comparison Register 0xDC 32 read-write n 0x0 0x0 NANOSEC 1588 Timer Nanosecond Comparison Value 0 22 NSR Network Status Register 0x8 32 read-only n 0x0 0x0 IDLE PHY Management Logic Idle 2 1 MDIO MDIO Input Status 1 1 OFR Oversize Frames Received Register 0x188 32 read-only n 0x0 0x0 OFRX Oversized Frames Received 0 10 ORHI Octets Received High Received Register 0x154 32 read-only n 0x0 0x0 RXO Received Octets 0 16 ORLO Octets Received Low Received Register 0x150 32 read-only n 0x0 0x0 RXO Received Octets 0 32 OTHI Octets Transmitted High Register 0x104 32 read-only n 0x0 0x0 TXO Transmitted Octets 0 16 OTLO Octets Transmitted Low Register 0x100 32 read-only n 0x0 0x0 TXO Transmitted Octets 0 32 PEFRN PTP Peer Event Frame Received Nanoseconds Register 0x1FC 32 read-only n 0x0 0x0 RUD Register Update 0 30 PEFRSH PTP Peer Event Frame Received Seconds High Register 0xF4 32 read-only n 0x0 0x0 RUD Register Update 0 16 PEFRSL PTP Peer Event Frame Received Seconds Low Register 0x1F8 32 read-only n 0x0 0x0 RUD Register Update 0 32 PEFTN PTP Peer Event Frame Transmitted Nanoseconds Register 0x1F4 32 read-only n 0x0 0x0 RUD Register Update 0 30 PEFTSH PTP Peer Event Frame Transmitted Seconds High Register 0xF0 32 read-only n 0x0 0x0 RUD Register Update 0 16 PEFTSL PTP Peer Event Frame Transmitted Seconds Low Register 0x1F0 32 read-only n 0x0 0x0 RUD Register Update 0 32 PFR Pause Frames Received Register 0x164 32 read-only n 0x0 0x0 PFRX Pause Frames Received Register 0 16 PFT Pause Frames Transmitted Register 0x114 32 read-only n 0x0 0x0 PFTX Pause Frames Transmitted Register 0 16 RBQB Receive Buffer Queue Base Address Register 0x18 32 read-write n 0x0 0x0 ADDR Receive Buffer Queue Base Address 2 30 RBQBAPQ0 Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0x480 32 read-write n RXBQBA Receive Buffer Queue Base Address 2 30 read-write RBQBAPQ1 Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0x484 32 read-write n RXBQBA Receive Buffer Queue Base Address 2 30 read-write RBQBAPQ[0] Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 0x8F8 32 read-write n 0x0 0x0 RXBQBA Receive Buffer Queue Base Address 2 30 RBQBAPQ[1] Receive Buffer Queue Base Address Register Priority Queue (index = 1) 0 0xD78 32 read-write n 0x0 0x0 RXBQBA Receive Buffer Queue Base Address 2 30 RBSRPQ0 Receive Buffer Size Register Priority Queue (index = 1) 0x4A0 32 read-write n RBS Receive Buffer Size 0 16 read-write RBSRPQ1 Receive Buffer Size Register Priority Queue (index = 1) 0x4A4 32 read-write n RBS Receive Buffer Size 0 16 read-write RBSRPQ[0] Receive Buffer Size Register Priority Queue (index = 1) 0 0x938 32 read-write n 0x0 0x0 RBS Receive Buffer Size 0 16 RBSRPQ[1] Receive Buffer Size Register Priority Queue (index = 1) 0 0xDD8 32 read-write n 0x0 0x0 RBS Receive Buffer Size 0 16 RJFML RX Jumbo Frame Max Length Register 0x48 32 read-write n 0x0 0x0 FML Frame Max Length 0 14 ROE Receive Overrun Register 0x1A4 32 read-only n 0x0 0x0 RXOVR Receive Overruns 0 10 RPQ Received Pause Quantum Register 0x38 32 read-only n 0x0 0x0 RPQ Received Pause Quantum 0 16 RPSF RX Partial Store and Forward Register 0x44 32 read-write n 0x0 0x0 ENRXP Enable RX Partial Store and Forward Operation 31 1 RPB1ADR Receive Partial Store and Forward Address 0 12 RRE Receive Resource Errors Register 0x1A0 32 read-only n 0x0 0x0 RXRER Receive Resource Errors 0 18 RSE Receive Symbol Errors Register 0x198 32 read-only n 0x0 0x0 RXSE Receive Symbol Errors 0 10 RSR Receive Status Register 0x20 32 read-write n 0x0 0x0 BNA Buffer Not Available 0 1 HNO HRESP Not OK 3 1 REC Frame Received 1 1 RXOVR Receive Overrun 2 1 SA1-GMAC_SAB Specific Address 1 Bottom Register 0x88 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SA1-GMAC_SAT Specific Address 1 Top Register 0x8C 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SA2-GMAC_SA1-GMAC_SAB Specific Address 1 Bottom Register 0x118 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SA2-GMAC_SA1-GMAC_SAT Specific Address 1 Top Register 0x11C 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SA3-GMAC_SA2-GMAC_SA1-GMAC_SAB Specific Address 1 Bottom Register 0x1B0 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SA3-GMAC_SA2-GMAC_SA1-GMAC_SAT Specific Address 1 Top Register 0x1B4 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SA4-GMAC_SA3-GMAC_SA2-GMAC_SA1-GMAC_SAB Specific Address 1 Bottom Register 0x250 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 32 SA4-GMAC_SA3-GMAC_SA2-GMAC_SA1-GMAC_SAT Specific Address 1 Top Register 0x254 32 read-write n 0x0 0x0 ADDR Specific Address 1 0 16 SAB1 Specific Address 1 Bottom Register 0x88 32 read-write n 0x0 ADDR Specific Address 1 0 32 read-write SAB2 Specific Address 2 Bottom Register 0x90 32 read-write n 0x0 ADDR Specific Address 2 0 32 read-write SAB3 Specific Address 3 Bottom Register 0x98 32 read-write n 0x0 ADDR Specific Address 3 0 32 read-write SAB4 Specific Address 4 Bottom Register 0xA0 32 read-write n 0x0 ADDR Specific Address 4 0 32 read-write SAMB1 Specific Address 1 Mask Bottom Register 0xC8 32 read-write n 0x0 0x0 ADDR Specific Address 1 Mask 0 32 SAMT1 Specific Address 1 Mask Top Register 0xCC 32 read-write n 0x0 0x0 ADDR Specific Address 1 Mask 0 16 SAT1 Specific Address 1 Top Register 0x8C 32 read-write n 0x0 ADDR Specific Address 1 0 16 read-write SAT2 Specific Address 2 Top Register 0x94 32 read-write n 0x0 ADDR Specific Address 2 0 16 read-write SAT3 Specific Address 3 Top Register 0x9C 32 read-write n 0x0 ADDR Specific Address 3 0 16 read-write SAT4 Specific Address 4 Top Register 0xA4 32 read-write n 0x0 ADDR Specific Address 4 0 16 read-write SCF Single Collision Frames Register 0x138 32 read-only n 0x0 0x0 SCOL Single Collision 0 18 SCH 1588 Timer Second Comparison High Register 0xE4 32 read-write n 0x0 0x0 SEC 1588 Timer Second Comparison Value 0 16 SCL 1588 Timer Second Comparison Low Register 0xE0 32 read-write n 0x0 0x0 SEC 1588 Timer Second Comparison Value 0 32 ST1RPQ0 Screening Type 1 Register Priority Queue (index = 0) 0x500 32 read-write n DSTCE Differentiated Services or Traffic Class Match Enable 28 1 read-write DSTCM Differentiated Services or Traffic Class Match 4 8 read-write QNB Queue Number (0-2) 0 3 read-write UDPE UDP Port Match Enable 29 1 read-write UDPM UDP Port Match 12 16 read-write ST1RPQ1 Screening Type 1 Register Priority Queue (index = 0) 0x504 32 read-write n DSTCE Differentiated Services or Traffic Class Match Enable 28 1 read-write DSTCM Differentiated Services or Traffic Class Match 4 8 read-write QNB Queue Number (0-2) 0 3 read-write UDPE UDP Port Match Enable 29 1 read-write UDPM UDP Port Match 12 16 read-write ST1RPQ2 Screening Type 1 Register Priority Queue (index = 0) 0x508 32 read-write n DSTCE Differentiated Services or Traffic Class Match Enable 28 1 read-write DSTCM Differentiated Services or Traffic Class Match 4 8 read-write QNB Queue Number (0-2) 0 3 read-write UDPE UDP Port Match Enable 29 1 read-write UDPM UDP Port Match 12 16 read-write ST1RPQ3 Screening Type 1 Register Priority Queue (index = 0) 0x50C 32 read-write n DSTCE Differentiated Services or Traffic Class Match Enable 28 1 read-write DSTCM Differentiated Services or Traffic Class Match 4 8 read-write QNB Queue Number (0-2) 0 3 read-write UDPE UDP Port Match Enable 29 1 read-write UDPM UDP Port Match 12 16 read-write ST1RPQ[0] Screening Type 1 Register Priority Queue (index = 0) 0 0xA00 32 read-write n 0x0 0x0 DSTCE Differentiated Services or Traffic Class Match Enable 28 1 DSTCM Differentiated Services or Traffic Class Match 4 8 QNB Queue Number (0-2) 0 3 UDPE UDP Port Match Enable 29 1 UDPM UDP Port Match 12 16 ST1RPQ[1] Screening Type 1 Register Priority Queue (index = 0) 0 0xF04 32 read-write n 0x0 0x0 DSTCE Differentiated Services or Traffic Class Match Enable 28 1 DSTCM Differentiated Services or Traffic Class Match 4 8 QNB Queue Number (0-2) 0 3 UDPE UDP Port Match Enable 29 1 UDPM UDP Port Match 12 16 ST1RPQ[2] Screening Type 1 Register Priority Queue (index = 0) 0 0x140C 32 read-write n 0x0 0x0 DSTCE Differentiated Services or Traffic Class Match Enable 28 1 DSTCM Differentiated Services or Traffic Class Match 4 8 QNB Queue Number (0-2) 0 3 UDPE UDP Port Match Enable 29 1 UDPM UDP Port Match 12 16 ST1RPQ[3] Screening Type 1 Register Priority Queue (index = 0) 0 0x1918 32 read-write n 0x0 0x0 DSTCE Differentiated Services or Traffic Class Match Enable 28 1 DSTCM Differentiated Services or Traffic Class Match 4 8 QNB Queue Number (0-2) 0 3 UDPE UDP Port Match Enable 29 1 UDPM UDP Port Match 12 16 ST2CW00 Screening Type 2 Compare Word 0 Register (index = 0) 0x700 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW01 Screening Type 2 Compare Word 0 Register (index = 1) 0x708 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW010 Screening Type 2 Compare Word 0 Register (index = 10) 0x750 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW011 Screening Type 2 Compare Word 0 Register (index = 11) 0x758 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW012 Screening Type 2 Compare Word 0 Register (index = 12) 0x760 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW013 Screening Type 2 Compare Word 0 Register (index = 13) 0x768 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW014 Screening Type 2 Compare Word 0 Register (index = 14) 0x770 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW015 Screening Type 2 Compare Word 0 Register (index = 15) 0x778 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW016 Screening Type 2 Compare Word 0 Register (index = 16) 0x780 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW017 Screening Type 2 Compare Word 0 Register (index = 17) 0x788 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW018 Screening Type 2 Compare Word 0 Register (index = 18) 0x790 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW019 Screening Type 2 Compare Word 0 Register (index = 19) 0x798 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW02 Screening Type 2 Compare Word 0 Register (index = 2) 0x710 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW020 Screening Type 2 Compare Word 0 Register (index = 20) 0x7A0 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW021 Screening Type 2 Compare Word 0 Register (index = 21) 0x7A8 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW022 Screening Type 2 Compare Word 0 Register (index = 22) 0x7B0 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW023 Screening Type 2 Compare Word 0 Register (index = 23) 0x7B8 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW03 Screening Type 2 Compare Word 0 Register (index = 3) 0x718 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW04 Screening Type 2 Compare Word 0 Register (index = 4) 0x720 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW05 Screening Type 2 Compare Word 0 Register (index = 5) 0x728 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW06 Screening Type 2 Compare Word 0 Register (index = 6) 0x730 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW07 Screening Type 2 Compare Word 0 Register (index = 7) 0x738 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW08 Screening Type 2 Compare Word 0 Register (index = 8) 0x740 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW09 Screening Type 2 Compare Word 0 Register (index = 9) 0x748 32 read-write n 0x0 0x0 COMPVAL Compare Value 16 16 MASKVAL Mask Value 0 16 ST2CW10 Screening Type 2 Compare Word 1 Register (index = 0) 0x704 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW11 Screening Type 2 Compare Word 1 Register (index = 1) 0x70C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW110 Screening Type 2 Compare Word 1 Register (index = 10) 0x754 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW111 Screening Type 2 Compare Word 1 Register (index = 11) 0x75C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW112 Screening Type 2 Compare Word 1 Register (index = 12) 0x764 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW113 Screening Type 2 Compare Word 1 Register (index = 13) 0x76C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW114 Screening Type 2 Compare Word 1 Register (index = 14) 0x774 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW115 Screening Type 2 Compare Word 1 Register (index = 15) 0x77C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW116 Screening Type 2 Compare Word 1 Register (index = 16) 0x784 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW117 Screening Type 2 Compare Word 1 Register (index = 17) 0x78C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW118 Screening Type 2 Compare Word 1 Register (index = 18) 0x794 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW119 Screening Type 2 Compare Word 1 Register (index = 19) 0x79C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW12 Screening Type 2 Compare Word 1 Register (index = 2) 0x714 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW120 Screening Type 2 Compare Word 1 Register (index = 20) 0x7A4 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW121 Screening Type 2 Compare Word 1 Register (index = 21) 0x7AC 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW122 Screening Type 2 Compare Word 1 Register (index = 22) 0x7B4 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW123 Screening Type 2 Compare Word 1 Register (index = 23) 0x7BC 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW13 Screening Type 2 Compare Word 1 Register (index = 3) 0x71C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW14 Screening Type 2 Compare Word 1 Register (index = 4) 0x724 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW15 Screening Type 2 Compare Word 1 Register (index = 5) 0x72C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW16 Screening Type 2 Compare Word 1 Register (index = 6) 0x734 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW17 Screening Type 2 Compare Word 1 Register (index = 7) 0x73C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW18 Screening Type 2 Compare Word 1 Register (index = 8) 0x744 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2CW19 Screening Type 2 Compare Word 1 Register (index = 9) 0x74C 32 read-write n 0x0 0x0 OFFSSTRT Ethernet Frame Offset Start 7 2 OFFSSTRTSelect FRAMESTART Offset from the start of the frame 0 ETHERTYPE Offset from the byte after the EtherType field 1 IP Offset from the byte after the IP header field 2 TCP_UDP Offset from the byte after the TCP/UDP header field 3 OFFSVAL Offset Value in Bytes 0 7 ST2ER0 Screening Type 2 Ethertype Register (index = 0) 0x6E0 32 read-write n COMPVAL Ethertype Compare Value 0 16 read-write ST2ER1 Screening Type 2 Ethertype Register (index = 0) 0x6E4 32 read-write n COMPVAL Ethertype Compare Value 0 16 read-write ST2ER2 Screening Type 2 Ethertype Register (index = 0) 0x6E8 32 read-write n COMPVAL Ethertype Compare Value 0 16 read-write ST2ER3 Screening Type 2 Ethertype Register (index = 0) 0x6EC 32 read-write n COMPVAL Ethertype Compare Value 0 16 read-write ST2ER[0] Screening Type 2 Ethertype Register (index = 0) 0 0xDC0 32 read-write n 0x0 0x0 COMPVAL Ethertype Compare Value 0 16 ST2ER[1] Screening Type 2 Ethertype Register (index = 0) 0 0x14A4 32 read-write n 0x0 0x0 COMPVAL Ethertype Compare Value 0 16 ST2ER[2] Screening Type 2 Ethertype Register (index = 0) 0 0x1B8C 32 read-write n 0x0 0x0 COMPVAL Ethertype Compare Value 0 16 ST2ER[3] Screening Type 2 Ethertype Register (index = 0) 0 0x2278 32 read-write n 0x0 0x0 COMPVAL Ethertype Compare Value 0 16 ST2RPQ0 Screening Type 2 Register Priority Queue (index = 0) 0x540 32 read-write n COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 read-write COMPAE Compare A Enable 18 1 read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 read-write COMPBE Compare B Enable 24 1 read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 read-write COMPCE Compare C Enable 30 1 read-write ETHE EtherType Enable 12 1 read-write I2ETH Index of Screening Type 2 EtherType register x 9 3 read-write QNB Queue Number (0-2) 0 3 read-write VLANE VLAN Enable 8 1 read-write VLANP VLAN Priority 4 3 read-write ST2RPQ1 Screening Type 2 Register Priority Queue (index = 0) 0x544 32 read-write n COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 read-write COMPAE Compare A Enable 18 1 read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 read-write COMPBE Compare B Enable 24 1 read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 read-write COMPCE Compare C Enable 30 1 read-write ETHE EtherType Enable 12 1 read-write I2ETH Index of Screening Type 2 EtherType register x 9 3 read-write QNB Queue Number (0-2) 0 3 read-write VLANE VLAN Enable 8 1 read-write VLANP VLAN Priority 4 3 read-write ST2RPQ2 Screening Type 2 Register Priority Queue (index = 0) 0x548 32 read-write n COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 read-write COMPAE Compare A Enable 18 1 read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 read-write COMPBE Compare B Enable 24 1 read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 read-write COMPCE Compare C Enable 30 1 read-write ETHE EtherType Enable 12 1 read-write I2ETH Index of Screening Type 2 EtherType register x 9 3 read-write QNB Queue Number (0-2) 0 3 read-write VLANE VLAN Enable 8 1 read-write VLANP VLAN Priority 4 3 read-write ST2RPQ3 Screening Type 2 Register Priority Queue (index = 0) 0x54C 32 read-write n COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 read-write COMPAE Compare A Enable 18 1 read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 read-write COMPBE Compare B Enable 24 1 read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 read-write COMPCE Compare C Enable 30 1 read-write ETHE EtherType Enable 12 1 read-write I2ETH Index of Screening Type 2 EtherType register x 9 3 read-write QNB Queue Number (0-2) 0 3 read-write VLANE VLAN Enable 8 1 read-write VLANP VLAN Priority 4 3 read-write ST2RPQ4 Screening Type 2 Register Priority Queue (index = 0) 0x550 32 read-write n COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 read-write COMPAE Compare A Enable 18 1 read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 read-write COMPBE Compare B Enable 24 1 read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 read-write COMPCE Compare C Enable 30 1 read-write ETHE EtherType Enable 12 1 read-write I2ETH Index of Screening Type 2 EtherType register x 9 3 read-write QNB Queue Number (0-2) 0 3 read-write VLANE VLAN Enable 8 1 read-write VLANP VLAN Priority 4 3 read-write ST2RPQ5 Screening Type 2 Register Priority Queue (index = 0) 0x554 32 read-write n COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 read-write COMPAE Compare A Enable 18 1 read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 read-write COMPBE Compare B Enable 24 1 read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 read-write COMPCE Compare C Enable 30 1 read-write ETHE EtherType Enable 12 1 read-write I2ETH Index of Screening Type 2 EtherType register x 9 3 read-write QNB Queue Number (0-2) 0 3 read-write VLANE VLAN Enable 8 1 read-write VLANP VLAN Priority 4 3 read-write ST2RPQ6 Screening Type 2 Register Priority Queue (index = 0) 0x558 32 read-write n COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 read-write COMPAE Compare A Enable 18 1 read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 read-write COMPBE Compare B Enable 24 1 read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 read-write COMPCE Compare C Enable 30 1 read-write ETHE EtherType Enable 12 1 read-write I2ETH Index of Screening Type 2 EtherType register x 9 3 read-write QNB Queue Number (0-2) 0 3 read-write VLANE VLAN Enable 8 1 read-write VLANP VLAN Priority 4 3 read-write ST2RPQ7 Screening Type 2 Register Priority Queue (index = 0) 0x55C 32 read-write n COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 read-write COMPAE Compare A Enable 18 1 read-write COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 read-write COMPBE Compare B Enable 24 1 read-write COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 read-write COMPCE Compare C Enable 30 1 read-write ETHE EtherType Enable 12 1 read-write I2ETH Index of Screening Type 2 EtherType register x 9 3 read-write QNB Queue Number (0-2) 0 3 read-write VLANE VLAN Enable 8 1 read-write VLANP VLAN Priority 4 3 read-write ST2RPQ[0] Screening Type 2 Register Priority Queue (index = 0) 0 0xA80 32 read-write n 0x0 0x0 COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 COMPAE Compare A Enable 18 1 COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 COMPBE Compare B Enable 24 1 COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 COMPCE Compare C Enable 30 1 ETHE EtherType Enable 12 1 I2ETH Index of Screening Type 2 EtherType register x 9 3 QNB Queue Number (0-2) 0 3 VLANE VLAN Enable 8 1 VLANP VLAN Priority 4 3 ST2RPQ[1] Screening Type 2 Register Priority Queue (index = 0) 0 0xFC4 32 read-write n 0x0 0x0 COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 COMPAE Compare A Enable 18 1 COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 COMPBE Compare B Enable 24 1 COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 COMPCE Compare C Enable 30 1 ETHE EtherType Enable 12 1 I2ETH Index of Screening Type 2 EtherType register x 9 3 QNB Queue Number (0-2) 0 3 VLANE VLAN Enable 8 1 VLANP VLAN Priority 4 3 ST2RPQ[2] Screening Type 2 Register Priority Queue (index = 0) 0 0x150C 32 read-write n 0x0 0x0 COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 COMPAE Compare A Enable 18 1 COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 COMPBE Compare B Enable 24 1 COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 COMPCE Compare C Enable 30 1 ETHE EtherType Enable 12 1 I2ETH Index of Screening Type 2 EtherType register x 9 3 QNB Queue Number (0-2) 0 3 VLANE VLAN Enable 8 1 VLANP VLAN Priority 4 3 ST2RPQ[3] Screening Type 2 Register Priority Queue (index = 0) 0 0x1A58 32 read-write n 0x0 0x0 COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 COMPAE Compare A Enable 18 1 COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 COMPBE Compare B Enable 24 1 COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 COMPCE Compare C Enable 30 1 ETHE EtherType Enable 12 1 I2ETH Index of Screening Type 2 EtherType register x 9 3 QNB Queue Number (0-2) 0 3 VLANE VLAN Enable 8 1 VLANP VLAN Priority 4 3 ST2RPQ[4] Screening Type 2 Register Priority Queue (index = 0) 0 0x1FA8 32 read-write n 0x0 0x0 COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 COMPAE Compare A Enable 18 1 COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 COMPBE Compare B Enable 24 1 COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 COMPCE Compare C Enable 30 1 ETHE EtherType Enable 12 1 I2ETH Index of Screening Type 2 EtherType register x 9 3 QNB Queue Number (0-2) 0 3 VLANE VLAN Enable 8 1 VLANP VLAN Priority 4 3 ST2RPQ[5] Screening Type 2 Register Priority Queue (index = 0) 0 0x24FC 32 read-write n 0x0 0x0 COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 COMPAE Compare A Enable 18 1 COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 COMPBE Compare B Enable 24 1 COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 COMPCE Compare C Enable 30 1 ETHE EtherType Enable 12 1 I2ETH Index of Screening Type 2 EtherType register x 9 3 QNB Queue Number (0-2) 0 3 VLANE VLAN Enable 8 1 VLANP VLAN Priority 4 3 ST2RPQ[6] Screening Type 2 Register Priority Queue (index = 0) 0 0x2A54 32 read-write n 0x0 0x0 COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 COMPAE Compare A Enable 18 1 COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 COMPBE Compare B Enable 24 1 COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 COMPCE Compare C Enable 30 1 ETHE EtherType Enable 12 1 I2ETH Index of Screening Type 2 EtherType register x 9 3 QNB Queue Number (0-2) 0 3 VLANE VLAN Enable 8 1 VLANP VLAN Priority 4 3 ST2RPQ[7] Screening Type 2 Register Priority Queue (index = 0) 0 0x2FB0 32 read-write n 0x0 0x0 COMPA Index of Screening Type 2 Compare Word 0/Word 1 register x 13 5 COMPAE Compare A Enable 18 1 COMPB Index of Screening Type 2 Compare Word 0/Word 1 register x 19 5 COMPBE Compare B Enable 24 1 COMPC Index of Screening Type 2 Compare Word 0/Word 1 register x 25 5 COMPCE Compare C Enable 30 1 ETHE EtherType Enable 12 1 I2ETH Index of Screening Type 2 EtherType register x 9 3 QNB Queue Number (0-2) 0 3 VLANE VLAN Enable 8 1 VLANP VLAN Priority 4 3 SVLAN Stacked VLAN Register 0xC0 32 read-write n 0x0 0x0 ESVLAN Enable Stacked VLAN Processing Mode 31 1 VLAN_TYPE User Defined VLAN_TYPE Field 0 16 TA 1588 Timer Adjust Register 0x1D8 32 write-only n 0x0 0x0 ADJ Adjust 1588 Timer 31 1 ITDT Increment/Decrement 0 30 TBFR1023 512 to 1023 Byte Frames Received Register 0x178 32 read-only n 0x0 0x0 NFRX 512 to 1023 Byte Frames Received without Error 0 32 TBFR127 65 to 127 Byte Frames Received Register 0x16C 32 read-only n 0x0 0x0 NFRX 65 to 127 Byte Frames Received without Error 0 32 TBFR1518 1024 to 1518 Byte Frames Received Register 0x17C 32 read-only n 0x0 0x0 NFRX 1024 to 1518 Byte Frames Received without Error 0 32 TBFR255 128 to 255 Byte Frames Received Register 0x170 32 read-only n 0x0 0x0 NFRX 128 to 255 Byte Frames Received without Error 0 32 TBFR511 256 to 511 Byte Frames Received Register 0x174 32 read-only n 0x0 0x0 NFRX 256 to 511 Byte Frames Received without Error 0 32 TBFT1023 512 to 1023 Byte Frames Transmitted Register 0x128 32 read-only n 0x0 0x0 NFTX 512 to 1023 Byte Frames Transmitted without Error 0 32 TBFT127 65 to 127 Byte Frames Transmitted Register 0x11C 32 read-only n 0x0 0x0 NFTX 65 to 127 Byte Frames Transmitted without Error 0 32 TBFT1518 1024 to 1518 Byte Frames Transmitted Register 0x12C 32 read-only n 0x0 0x0 NFTX 1024 to 1518 Byte Frames Transmitted without Error 0 32 TBFT255 128 to 255 Byte Frames Transmitted Register 0x120 32 read-only n 0x0 0x0 NFTX 128 to 255 Byte Frames Transmitted without Error 0 32 TBFT511 256 to 511 Byte Frames Transmitted Register 0x124 32 read-only n 0x0 0x0 NFTX 256 to 511 Byte Frames Transmitted without Error 0 32 TBQB Transmit Buffer Queue Base Address Register 0x1C 32 read-write n 0x0 0x0 ADDR Transmit Buffer Queue Base Address 2 30 TBQBAPQ0 Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0x440 32 read-write n TXBQBA Transmit Buffer Queue Base Address 2 30 read-write TBQBAPQ1 Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0x444 32 read-write n TXBQBA Transmit Buffer Queue Base Address 2 30 read-write TBQBAPQ[0] Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 0x878 32 read-write n 0x0 0x0 TXBQBA Transmit Buffer Queue Base Address 2 30 TBQBAPQ[1] Transmit Buffer Queue Base Address Register Priority Queue (index = 1) 0 0xCB8 32 read-write n 0x0 0x0 TXBQBA Transmit Buffer Queue Base Address 2 30 TCE TCP Checksum Errors Register 0x1AC 32 read-only n 0x0 0x0 TCKER TCP Checksum Errors 0 8 TI 1588 Timer Increment Register 0x1DC 32 read-write n 0x0 0x0 ACNS Alternative Count Nanoseconds 8 8 CNS Count Nanoseconds 0 8 NIT Number of Increments 16 8 TIDM1 Type ID Match 1 Register 0xA8 32 read-write n 0x0 0x0 ENID1 Enable Copying of TID Matched Frames 31 1 TID Type ID Match 1 0 16 TIDM2 Type ID Match 2 Register 0xAC 32 read-write n 0x0 0x0 ENID2 Enable Copying of TID Matched Frames 31 1 TID Type ID Match 2 0 16 TIDM3 Type ID Match 3 Register 0xB0 32 read-write n 0x0 0x0 ENID3 Enable Copying of TID Matched Frames 31 1 TID Type ID Match 3 0 16 TIDM4 Type ID Match 4 Register 0xB4 32 read-write n 0x0 0x0 ENID4 Enable Copying of TID Matched Frames 31 1 TID Type ID Match 4 0 16 TISUBN 1588 Timer Increment Sub-nanoseconds Register 0x1BC 32 read-write n 0x0 0x0 LSBTIR Lower Significant Bits of Timer Increment Register 0 16 TMXBFR 1519 to Maximum Byte Frames Received Register 0x180 32 read-only n 0x0 0x0 NFRX 1519 to Maximum Byte Frames Received without Error 0 32 TN 1588 Timer Nanoseconds Register 0x1D4 32 read-write n 0x0 0x0 TNS Timer Count in Nanoseconds 0 30 TPFCP Transmit PFC Pause Register 0xC4 32 read-write n 0x0 0x0 PEV Priority Enable Vector 0 8 PQ Pause Quantum 8 8 TPQ Transmit Pause Quantum Register 0x3C 32 read-write n 0x0 0x0 TPQ Transmit Pause Quantum 0 16 TPSF TX Partial Store and Forward Register 0x40 32 read-write n 0x0 0x0 ENTXP Enable TX Partial Store and Forward Operation 31 1 TPB1ADR Transmit Partial Store and Forward Address 0 12 TSH 1588 Timer Seconds High Register 0x1C0 32 read-write n 0x0 0x0 TCS Timer Count in Seconds 0 16 TSL 1588 Timer Seconds Low Register 0x1D0 32 read-write n 0x0 0x0 TCS Timer Count in Seconds 0 32 TSR Transmit Status Register 0x14 32 read-write n 0x0 0x0 COL Collision Occurred 1 1 HRESP HRESP Not OK 8 1 RLE Retry Limit Exceeded 2 1 TFC Transmit Frame Corruption Due to AHB Error 4 1 TXCOMP Transmit Complete 5 1 TXGO Transmit Go 3 1 UBR Used Bit Read 0 1 TUR Transmit Underruns Register 0x134 32 read-only n 0x0 0x0 TXUNR Transmit Underruns 0 10 UCE UDP Checksum Errors Register 0x1B0 32 read-only n 0x0 0x0 UCKER UDP Checksum Errors 0 8 UFR Undersize Frames Received Register 0x184 32 read-only n 0x0 0x0 UFRX Undersize Frames Received 0 10 UR User Register 0xC 32 read-write n 0x0 0x0 RMII Reduced MII Mode 0 1 WOL Wake on LAN Register 0xB8 32 read-write n 0x0 0x0 ARP ARP Request IP Address 17 1 IP ARP Request IP Address 0 16 MAG Magic Packet Event Enable 16 1 MTI Multicast Hash Event Enable 19 1 SA1 Specific Address Register 1 Event Enable 18 1 GPBR General Purpose Backup Registers GPBR 0x0 0x0 0x20 registers n SYS_GPBR[0] General Purpose Backup Register 0 0x0 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR[1] General Purpose Backup Register 0 0x4 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR[2] General Purpose Backup Register 0 0xC 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR[3] General Purpose Backup Register 0 0x18 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR[4] General Purpose Backup Register 0 0x28 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR[5] General Purpose Backup Register 0 0x3C 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR[6] General Purpose Backup Register 0 0x54 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 SYS_GPBR[7] General Purpose Backup Register 0 0x70 32 read-write n 0x0 0x0 GPBR_VALUE Value of GPBR x 0 32 HSMCI High Speed MultiMedia Card Interface HSMCI 0x0 0x0 0x4000 registers n 0x0 0x4000 registers n HSMCI 18 ARGR Argument Register 0x10 32 read-write n 0x0 0x0 ARG Command Argument 0 32 BLKR Block Register 0x18 32 read-write n 0x0 0x0 BCNT MMC/SDIO Block Count - SDIO Byte Count 0 16 BLKLEN Data Block Length 16 16 CFG Configuration Register 0x54 32 read-write n 0x0 0x0 FERRCTRL Flow Error flag reset control mode 4 1 FIFOMODE HSMCI Internal FIFO control mode 0 1 HSMODE High Speed Mode 8 1 LSYNC Synchronize on the last block 12 1 CMDR Command Register 0x14 32 write-only n 0x0 0x0 ATACS ATA with Command Completion Signal 26 1 ATACSSelect NORMAL Normal operation mode. 0 COMPLETION This bit indicates that a completion signal is expected within a programmed amount of time (HSMCI_CSTOR). 1 BOOT_ACK Boot Operation Acknowledge 27 1 CMDNB Command Number 0 6 IOSPCMD SDIO Special Command 24 2 IOSPCMDSelect STD Not an SDIO Special Command 0 SUSPEND SDIO Suspend Command 1 RESUME SDIO Resume Command 2 MAXLAT Max Latency for Command to Response 12 1 MAXLATSelect _5 5-cycle max latency. 0 _64 64-cycle max latency. 1 OPDCMD Open Drain Command 11 1 OPDCMDSelect PUSHPULL Push pull command. 0 OPENDRAIN Open drain command. 1 RSPTYP Response Type 6 2 RSPTYPSelect NORESP No response 0 _48_BIT 48-bit response 1 _136_BIT 136-bit response 2 R1B R1b response type 3 SPCMD Special Command 8 3 SPCMDSelect STD Not a special CMD. 0 INIT Initialization CMD: 74 clock cycles for initialization sequence. 1 SYNC Synchronized CMD: Wait for the end of the current data block transfer before sending the pending command. 2 CE_ATA CE-ATA Completion Signal disable Command. The host cancels the ability for the device to return a command completion signal on the command line. 3 IT_CMD Interrupt command: Corresponds to the Interrupt Mode (CMD40). 4 IT_RESP Interrupt response: Corresponds to the Interrupt Mode (CMD40). 5 BOR Boot Operation Request. Start a boot operation mode, the host processor can read boot data from the MMC device directly. 6 EBO End Boot Operation. This command allows the host processor to terminate the boot operation mode. 7 TRCMD Transfer Command 16 2 TRCMDSelect NO_DATA No data transfer 0 START_DATA Start data transfer 1 STOP_DATA Stop data transfer 2 TRDIR Transfer Direction 18 1 TRDIRSelect WRITE Write. 0 READ Read. 1 TRTYP Transfer Type 19 3 TRTYPSelect SINGLE MMC/SD Card Single Block 0 MULTIPLE MMC/SD Card Multiple Block 1 STREAM MMC Stream 2 BYTE SDIO Byte 4 BLOCK SDIO Block 5 CR Control Register 0x0 32 write-only n 0x0 0x0 MCIDIS Multi-Media Interface Disable 1 1 MCIEN Multi-Media Interface Enable 0 1 PWSDIS Power Save Mode Disable 3 1 PWSEN Power Save Mode Enable 2 1 SWRST Software Reset 7 1 CSTOR Completion Signal Timeout Register 0x1C 32 read-write n 0x0 0x0 CSTOCYC Completion Signal Timeout Cycle Number 0 4 CSTOMUL Completion Signal Timeout Multiplier 4 3 CSTOMULSelect _1 CSTOCYC x 1 0 _16 CSTOCYC x 16 1 _128 CSTOCYC x 128 2 _256 CSTOCYC x 256 3 _1024 CSTOCYC x 1024 4 _4096 CSTOCYC x 4096 5 _65536 CSTOCYC x 65536 6 _1048576 CSTOCYC x 1048576 7 DMA DMA Configuration Register 0x50 32 read-write n 0x0 0x0 CHKSIZE DMA Channel Read and Write Chunk Size 4 3 CHKSIZESelect _1 1 data available 0 _2 2 data available 1 _4 4 data available 2 _8 8 data available 3 _16 16 data available 4 DMAEN DMA Hardware Handshaking Enable 8 1 DTOR Data Timeout Register 0x8 32 read-write n 0x0 0x0 DTOCYC Data Timeout Cycle Number 0 4 DTOMUL Data Timeout Multiplier 4 3 DTOMULSelect _1 DTOCYC 0 _16 DTOCYC x 16 1 _128 DTOCYC x 128 2 _256 DTOCYC x 256 3 _1024 DTOCYC x 1024 4 _4096 DTOCYC x 4096 5 _65536 DTOCYC x 65536 6 _1048576 DTOCYC x 1048576 7 FIFO0 FIFO Memory Aperture0 0x200 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO1 FIFO Memory Aperture0 0x204 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO10 FIFO Memory Aperture0 0x228 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO100 FIFO Memory Aperture0 0x390 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO101 FIFO Memory Aperture0 0x394 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO102 FIFO Memory Aperture0 0x398 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO103 FIFO Memory Aperture0 0x39C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO104 FIFO Memory Aperture0 0x3A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO105 FIFO Memory Aperture0 0x3A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO106 FIFO Memory Aperture0 0x3A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO107 FIFO Memory Aperture0 0x3AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO108 FIFO Memory Aperture0 0x3B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO109 FIFO Memory Aperture0 0x3B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO11 FIFO Memory Aperture0 0x22C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO110 FIFO Memory Aperture0 0x3B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO111 FIFO Memory Aperture0 0x3BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO112 FIFO Memory Aperture0 0x3C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO113 FIFO Memory Aperture0 0x3C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO114 FIFO Memory Aperture0 0x3C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO115 FIFO Memory Aperture0 0x3CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO116 FIFO Memory Aperture0 0x3D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO117 FIFO Memory Aperture0 0x3D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO118 FIFO Memory Aperture0 0x3D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO119 FIFO Memory Aperture0 0x3DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO12 FIFO Memory Aperture0 0x230 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO120 FIFO Memory Aperture0 0x3E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO121 FIFO Memory Aperture0 0x3E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO122 FIFO Memory Aperture0 0x3E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO123 FIFO Memory Aperture0 0x3EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO124 FIFO Memory Aperture0 0x3F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO125 FIFO Memory Aperture0 0x3F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO126 FIFO Memory Aperture0 0x3F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO127 FIFO Memory Aperture0 0x3FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO128 FIFO Memory Aperture0 0x400 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO129 FIFO Memory Aperture0 0x404 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO13 FIFO Memory Aperture0 0x234 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO130 FIFO Memory Aperture0 0x408 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO131 FIFO Memory Aperture0 0x40C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO132 FIFO Memory Aperture0 0x410 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO133 FIFO Memory Aperture0 0x414 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO134 FIFO Memory Aperture0 0x418 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO135 FIFO Memory Aperture0 0x41C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO136 FIFO Memory Aperture0 0x420 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO137 FIFO Memory Aperture0 0x424 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO138 FIFO Memory Aperture0 0x428 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO139 FIFO Memory Aperture0 0x42C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO14 FIFO Memory Aperture0 0x238 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO140 FIFO Memory Aperture0 0x430 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO141 FIFO Memory Aperture0 0x434 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO142 FIFO Memory Aperture0 0x438 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO143 FIFO Memory Aperture0 0x43C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO144 FIFO Memory Aperture0 0x440 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO145 FIFO Memory Aperture0 0x444 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO146 FIFO Memory Aperture0 0x448 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO147 FIFO Memory Aperture0 0x44C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO148 FIFO Memory Aperture0 0x450 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO149 FIFO Memory Aperture0 0x454 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO15 FIFO Memory Aperture0 0x23C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO150 FIFO Memory Aperture0 0x458 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO151 FIFO Memory Aperture0 0x45C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO152 FIFO Memory Aperture0 0x460 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO153 FIFO Memory Aperture0 0x464 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO154 FIFO Memory Aperture0 0x468 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO155 FIFO Memory Aperture0 0x46C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO156 FIFO Memory Aperture0 0x470 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO157 FIFO Memory Aperture0 0x474 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO158 FIFO Memory Aperture0 0x478 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO159 FIFO Memory Aperture0 0x47C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO16 FIFO Memory Aperture0 0x240 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO160 FIFO Memory Aperture0 0x480 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO161 FIFO Memory Aperture0 0x484 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO162 FIFO Memory Aperture0 0x488 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO163 FIFO Memory Aperture0 0x48C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO164 FIFO Memory Aperture0 0x490 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO165 FIFO Memory Aperture0 0x494 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO166 FIFO Memory Aperture0 0x498 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO167 FIFO Memory Aperture0 0x49C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO168 FIFO Memory Aperture0 0x4A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO169 FIFO Memory Aperture0 0x4A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO17 FIFO Memory Aperture0 0x244 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO170 FIFO Memory Aperture0 0x4A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO171 FIFO Memory Aperture0 0x4AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO172 FIFO Memory Aperture0 0x4B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO173 FIFO Memory Aperture0 0x4B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO174 FIFO Memory Aperture0 0x4B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO175 FIFO Memory Aperture0 0x4BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO176 FIFO Memory Aperture0 0x4C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO177 FIFO Memory Aperture0 0x4C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO178 FIFO Memory Aperture0 0x4C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO179 FIFO Memory Aperture0 0x4CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO18 FIFO Memory Aperture0 0x248 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO180 FIFO Memory Aperture0 0x4D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO181 FIFO Memory Aperture0 0x4D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO182 FIFO Memory Aperture0 0x4D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO183 FIFO Memory Aperture0 0x4DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO184 FIFO Memory Aperture0 0x4E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO185 FIFO Memory Aperture0 0x4E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO186 FIFO Memory Aperture0 0x4E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO187 FIFO Memory Aperture0 0x4EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO188 FIFO Memory Aperture0 0x4F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO189 FIFO Memory Aperture0 0x4F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO19 FIFO Memory Aperture0 0x24C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO190 FIFO Memory Aperture0 0x4F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO191 FIFO Memory Aperture0 0x4FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO192 FIFO Memory Aperture0 0x500 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO193 FIFO Memory Aperture0 0x504 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO194 FIFO Memory Aperture0 0x508 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO195 FIFO Memory Aperture0 0x50C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO196 FIFO Memory Aperture0 0x510 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO197 FIFO Memory Aperture0 0x514 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO198 FIFO Memory Aperture0 0x518 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO199 FIFO Memory Aperture0 0x51C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO2 FIFO Memory Aperture0 0x208 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO20 FIFO Memory Aperture0 0x250 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO200 FIFO Memory Aperture0 0x520 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO201 FIFO Memory Aperture0 0x524 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO202 FIFO Memory Aperture0 0x528 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO203 FIFO Memory Aperture0 0x52C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO204 FIFO Memory Aperture0 0x530 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO205 FIFO Memory Aperture0 0x534 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO206 FIFO Memory Aperture0 0x538 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO207 FIFO Memory Aperture0 0x53C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO208 FIFO Memory Aperture0 0x540 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO209 FIFO Memory Aperture0 0x544 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO21 FIFO Memory Aperture0 0x254 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO210 FIFO Memory Aperture0 0x548 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO211 FIFO Memory Aperture0 0x54C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO212 FIFO Memory Aperture0 0x550 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO213 FIFO Memory Aperture0 0x554 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO214 FIFO Memory Aperture0 0x558 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO215 FIFO Memory Aperture0 0x55C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO216 FIFO Memory Aperture0 0x560 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO217 FIFO Memory Aperture0 0x564 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO218 FIFO Memory Aperture0 0x568 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO219 FIFO Memory Aperture0 0x56C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO22 FIFO Memory Aperture0 0x258 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO220 FIFO Memory Aperture0 0x570 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO221 FIFO Memory Aperture0 0x574 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO222 FIFO Memory Aperture0 0x578 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO223 FIFO Memory Aperture0 0x57C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO224 FIFO Memory Aperture0 0x580 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO225 FIFO Memory Aperture0 0x584 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO226 FIFO Memory Aperture0 0x588 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO227 FIFO Memory Aperture0 0x58C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO228 FIFO Memory Aperture0 0x590 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO229 FIFO Memory Aperture0 0x594 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO23 FIFO Memory Aperture0 0x25C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO230 FIFO Memory Aperture0 0x598 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO231 FIFO Memory Aperture0 0x59C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO232 FIFO Memory Aperture0 0x5A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO233 FIFO Memory Aperture0 0x5A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO234 FIFO Memory Aperture0 0x5A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO235 FIFO Memory Aperture0 0x5AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO236 FIFO Memory Aperture0 0x5B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO237 FIFO Memory Aperture0 0x5B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO238 FIFO Memory Aperture0 0x5B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO239 FIFO Memory Aperture0 0x5BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO24 FIFO Memory Aperture0 0x260 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO240 FIFO Memory Aperture0 0x5C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO241 FIFO Memory Aperture0 0x5C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO242 FIFO Memory Aperture0 0x5C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO243 FIFO Memory Aperture0 0x5CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO244 FIFO Memory Aperture0 0x5D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO245 FIFO Memory Aperture0 0x5D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO246 FIFO Memory Aperture0 0x5D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO247 FIFO Memory Aperture0 0x5DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO248 FIFO Memory Aperture0 0x5E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO249 FIFO Memory Aperture0 0x5E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO25 FIFO Memory Aperture0 0x264 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO250 FIFO Memory Aperture0 0x5E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO251 FIFO Memory Aperture0 0x5EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO252 FIFO Memory Aperture0 0x5F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO253 FIFO Memory Aperture0 0x5F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO254 FIFO Memory Aperture0 0x5F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO255 FIFO Memory Aperture0 0x5FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO26 FIFO Memory Aperture0 0x268 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO27 FIFO Memory Aperture0 0x26C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO28 FIFO Memory Aperture0 0x270 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO29 FIFO Memory Aperture0 0x274 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO3 FIFO Memory Aperture0 0x20C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO30 FIFO Memory Aperture0 0x278 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO31 FIFO Memory Aperture0 0x27C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO32 FIFO Memory Aperture0 0x280 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO33 FIFO Memory Aperture0 0x284 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO34 FIFO Memory Aperture0 0x288 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO35 FIFO Memory Aperture0 0x28C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO36 FIFO Memory Aperture0 0x290 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO37 FIFO Memory Aperture0 0x294 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO38 FIFO Memory Aperture0 0x298 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO39 FIFO Memory Aperture0 0x29C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO4 FIFO Memory Aperture0 0x210 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO40 FIFO Memory Aperture0 0x2A0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO41 FIFO Memory Aperture0 0x2A4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO42 FIFO Memory Aperture0 0x2A8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO43 FIFO Memory Aperture0 0x2AC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO44 FIFO Memory Aperture0 0x2B0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO45 FIFO Memory Aperture0 0x2B4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO46 FIFO Memory Aperture0 0x2B8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO47 FIFO Memory Aperture0 0x2BC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO48 FIFO Memory Aperture0 0x2C0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO49 FIFO Memory Aperture0 0x2C4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO5 FIFO Memory Aperture0 0x214 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO50 FIFO Memory Aperture0 0x2C8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO51 FIFO Memory Aperture0 0x2CC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO52 FIFO Memory Aperture0 0x2D0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO53 FIFO Memory Aperture0 0x2D4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO54 FIFO Memory Aperture0 0x2D8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO55 FIFO Memory Aperture0 0x2DC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO56 FIFO Memory Aperture0 0x2E0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO57 FIFO Memory Aperture0 0x2E4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO58 FIFO Memory Aperture0 0x2E8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO59 FIFO Memory Aperture0 0x2EC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO6 FIFO Memory Aperture0 0x218 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO60 FIFO Memory Aperture0 0x2F0 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO61 FIFO Memory Aperture0 0x2F4 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO62 FIFO Memory Aperture0 0x2F8 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO63 FIFO Memory Aperture0 0x2FC 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO64 FIFO Memory Aperture0 0x300 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO65 FIFO Memory Aperture0 0x304 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO66 FIFO Memory Aperture0 0x308 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO67 FIFO Memory Aperture0 0x30C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO68 FIFO Memory Aperture0 0x310 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO69 FIFO Memory Aperture0 0x314 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO7 FIFO Memory Aperture0 0x21C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO70 FIFO Memory Aperture0 0x318 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO71 FIFO Memory Aperture0 0x31C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO72 FIFO Memory Aperture0 0x320 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO73 FIFO Memory Aperture0 0x324 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO74 FIFO Memory Aperture0 0x328 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO75 FIFO Memory Aperture0 0x32C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO76 FIFO Memory Aperture0 0x330 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO77 FIFO Memory Aperture0 0x334 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO78 FIFO Memory Aperture0 0x338 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO79 FIFO Memory Aperture0 0x33C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO8 FIFO Memory Aperture0 0x220 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO80 FIFO Memory Aperture0 0x340 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO81 FIFO Memory Aperture0 0x344 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO82 FIFO Memory Aperture0 0x348 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO83 FIFO Memory Aperture0 0x34C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO84 FIFO Memory Aperture0 0x350 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO85 FIFO Memory Aperture0 0x354 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO86 FIFO Memory Aperture0 0x358 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO87 FIFO Memory Aperture0 0x35C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO88 FIFO Memory Aperture0 0x360 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO89 FIFO Memory Aperture0 0x364 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO9 FIFO Memory Aperture0 0x224 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO90 FIFO Memory Aperture0 0x368 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO91 FIFO Memory Aperture0 0x36C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO92 FIFO Memory Aperture0 0x370 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO93 FIFO Memory Aperture0 0x374 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO94 FIFO Memory Aperture0 0x378 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO95 FIFO Memory Aperture0 0x37C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO96 FIFO Memory Aperture0 0x380 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO97 FIFO Memory Aperture0 0x384 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO98 FIFO Memory Aperture0 0x388 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO99 FIFO Memory Aperture0 0x38C 32 read-write n DATA Data to Read or Data to Write 0 32 read-write FIFO[0] FIFO Memory Aperture0 0 0x400 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[100] FIFO Memory Aperture0 0 0x11AE8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[101] FIFO Memory Aperture0 0 0x11E7C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[102] FIFO Memory Aperture0 0 0x12214 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[103] FIFO Memory Aperture0 0 0x125B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[104] FIFO Memory Aperture0 0 0x12950 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[105] FIFO Memory Aperture0 0 0x12CF4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[106] FIFO Memory Aperture0 0 0x1309C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[107] FIFO Memory Aperture0 0 0x13448 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[108] FIFO Memory Aperture0 0 0x137F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[109] FIFO Memory Aperture0 0 0x13BAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[10] FIFO Memory Aperture0 0 0x18DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[110] FIFO Memory Aperture0 0 0x13F64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[111] FIFO Memory Aperture0 0 0x14320 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[112] FIFO Memory Aperture0 0 0x146E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[113] FIFO Memory Aperture0 0 0x14AA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[114] FIFO Memory Aperture0 0 0x14E6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[115] FIFO Memory Aperture0 0 0x15238 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[116] FIFO Memory Aperture0 0 0x15608 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[117] FIFO Memory Aperture0 0 0x159DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[118] FIFO Memory Aperture0 0 0x15DB4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[119] FIFO Memory Aperture0 0 0x16190 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[11] FIFO Memory Aperture0 0 0x1B08 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[120] FIFO Memory Aperture0 0 0x16570 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[121] FIFO Memory Aperture0 0 0x16954 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[122] FIFO Memory Aperture0 0 0x16D3C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[123] FIFO Memory Aperture0 0 0x17128 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[124] FIFO Memory Aperture0 0 0x17518 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[125] FIFO Memory Aperture0 0 0x1790C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[126] FIFO Memory Aperture0 0 0x17D04 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[127] FIFO Memory Aperture0 0 0x18100 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[128] FIFO Memory Aperture0 0 0x18500 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[129] FIFO Memory Aperture0 0 0x18904 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[12] FIFO Memory Aperture0 0 0x1D38 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[130] FIFO Memory Aperture0 0 0x18D0C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[131] FIFO Memory Aperture0 0 0x19118 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[132] FIFO Memory Aperture0 0 0x19528 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[133] FIFO Memory Aperture0 0 0x1993C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[134] FIFO Memory Aperture0 0 0x19D54 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[135] FIFO Memory Aperture0 0 0x1A170 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[136] FIFO Memory Aperture0 0 0x1A590 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[137] FIFO Memory Aperture0 0 0x1A9B4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[138] FIFO Memory Aperture0 0 0x1ADDC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[139] FIFO Memory Aperture0 0 0x1B208 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[13] FIFO Memory Aperture0 0 0x1F6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[140] FIFO Memory Aperture0 0 0x1B638 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[141] FIFO Memory Aperture0 0 0x1BA6C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[142] FIFO Memory Aperture0 0 0x1BEA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[143] FIFO Memory Aperture0 0 0x1C2E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[144] FIFO Memory Aperture0 0 0x1C720 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[145] FIFO Memory Aperture0 0 0x1CB64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[146] FIFO Memory Aperture0 0 0x1CFAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[147] FIFO Memory Aperture0 0 0x1D3F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[148] FIFO Memory Aperture0 0 0x1D848 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[149] FIFO Memory Aperture0 0 0x1DC9C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[14] FIFO Memory Aperture0 0 0x21A4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[150] FIFO Memory Aperture0 0 0x1E0F4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[151] FIFO Memory Aperture0 0 0x1E550 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[152] FIFO Memory Aperture0 0 0x1E9B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[153] FIFO Memory Aperture0 0 0x1EE14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[154] FIFO Memory Aperture0 0 0x1F27C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[155] FIFO Memory Aperture0 0 0x1F6E8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[156] FIFO Memory Aperture0 0 0x1FB58 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[157] FIFO Memory Aperture0 0 0x1FFCC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[158] FIFO Memory Aperture0 0 0x20444 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[159] FIFO Memory Aperture0 0 0x208C0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[15] FIFO Memory Aperture0 0 0x23E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[160] FIFO Memory Aperture0 0 0x20D40 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[161] FIFO Memory Aperture0 0 0x211C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[162] FIFO Memory Aperture0 0 0x2164C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[163] FIFO Memory Aperture0 0 0x21AD8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[164] FIFO Memory Aperture0 0 0x21F68 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[165] FIFO Memory Aperture0 0 0x223FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[166] FIFO Memory Aperture0 0 0x22894 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[167] FIFO Memory Aperture0 0 0x22D30 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[168] FIFO Memory Aperture0 0 0x231D0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[169] FIFO Memory Aperture0 0 0x23674 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[16] FIFO Memory Aperture0 0 0x2620 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[170] FIFO Memory Aperture0 0 0x23B1C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[171] FIFO Memory Aperture0 0 0x23FC8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[172] FIFO Memory Aperture0 0 0x24478 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[173] FIFO Memory Aperture0 0 0x2492C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[174] FIFO Memory Aperture0 0 0x24DE4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[175] FIFO Memory Aperture0 0 0x252A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[176] FIFO Memory Aperture0 0 0x25760 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[177] FIFO Memory Aperture0 0 0x25C24 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[178] FIFO Memory Aperture0 0 0x260EC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[179] FIFO Memory Aperture0 0 0x265B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[17] FIFO Memory Aperture0 0 0x2864 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[180] FIFO Memory Aperture0 0 0x26A88 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[181] FIFO Memory Aperture0 0 0x26F5C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[182] FIFO Memory Aperture0 0 0x27434 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[183] FIFO Memory Aperture0 0 0x27910 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[184] FIFO Memory Aperture0 0 0x27DF0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[185] FIFO Memory Aperture0 0 0x282D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[186] FIFO Memory Aperture0 0 0x287BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[187] FIFO Memory Aperture0 0 0x28CA8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[188] FIFO Memory Aperture0 0 0x29198 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[189] FIFO Memory Aperture0 0 0x2968C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[18] FIFO Memory Aperture0 0 0x2AAC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[190] FIFO Memory Aperture0 0 0x29B84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[191] FIFO Memory Aperture0 0 0x2A080 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[192] FIFO Memory Aperture0 0 0x2A580 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[193] FIFO Memory Aperture0 0 0x2AA84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[194] FIFO Memory Aperture0 0 0x2AF8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[195] FIFO Memory Aperture0 0 0x2B498 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[196] FIFO Memory Aperture0 0 0x2B9A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[197] FIFO Memory Aperture0 0 0x2BEBC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[198] FIFO Memory Aperture0 0 0x2C3D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[199] FIFO Memory Aperture0 0 0x2C8F0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[19] FIFO Memory Aperture0 0 0x2CF8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[1] FIFO Memory Aperture0 0 0x604 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[200] FIFO Memory Aperture0 0 0x2CE10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[201] FIFO Memory Aperture0 0 0x2D334 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[202] FIFO Memory Aperture0 0 0x2D85C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[203] FIFO Memory Aperture0 0 0x2DD88 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[204] FIFO Memory Aperture0 0 0x2E2B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[205] FIFO Memory Aperture0 0 0x2E7EC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[206] FIFO Memory Aperture0 0 0x2ED24 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[207] FIFO Memory Aperture0 0 0x2F260 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[208] FIFO Memory Aperture0 0 0x2F7A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[209] FIFO Memory Aperture0 0 0x2FCE4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[20] FIFO Memory Aperture0 0 0x2F48 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[210] FIFO Memory Aperture0 0 0x3022C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[211] FIFO Memory Aperture0 0 0x30778 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[212] FIFO Memory Aperture0 0 0x30CC8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[213] FIFO Memory Aperture0 0 0x3121C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[214] FIFO Memory Aperture0 0 0x31774 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[215] FIFO Memory Aperture0 0 0x31CD0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[216] FIFO Memory Aperture0 0 0x32230 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[217] FIFO Memory Aperture0 0 0x32794 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[218] FIFO Memory Aperture0 0 0x32CFC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[219] FIFO Memory Aperture0 0 0x33268 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[21] FIFO Memory Aperture0 0 0x319C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[220] FIFO Memory Aperture0 0 0x337D8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[221] FIFO Memory Aperture0 0 0x33D4C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[222] FIFO Memory Aperture0 0 0x342C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[223] FIFO Memory Aperture0 0 0x34840 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[224] FIFO Memory Aperture0 0 0x34DC0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[225] FIFO Memory Aperture0 0 0x35344 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[226] FIFO Memory Aperture0 0 0x358CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[227] FIFO Memory Aperture0 0 0x35E58 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[228] FIFO Memory Aperture0 0 0x363E8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[229] FIFO Memory Aperture0 0 0x3697C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[22] FIFO Memory Aperture0 0 0x33F4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[230] FIFO Memory Aperture0 0 0x36F14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[231] FIFO Memory Aperture0 0 0x374B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[232] FIFO Memory Aperture0 0 0x37A50 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[233] FIFO Memory Aperture0 0 0x37FF4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[234] FIFO Memory Aperture0 0 0x3859C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[235] FIFO Memory Aperture0 0 0x38B48 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[236] FIFO Memory Aperture0 0 0x390F8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[237] FIFO Memory Aperture0 0 0x396AC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[238] FIFO Memory Aperture0 0 0x39C64 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[239] FIFO Memory Aperture0 0 0x3A220 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[23] FIFO Memory Aperture0 0 0x3650 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[240] FIFO Memory Aperture0 0 0x3A7E0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[241] FIFO Memory Aperture0 0 0x3ADA4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[242] FIFO Memory Aperture0 0 0x3B36C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[243] FIFO Memory Aperture0 0 0x3B938 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[244] FIFO Memory Aperture0 0 0x3BF08 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[245] FIFO Memory Aperture0 0 0x3C4DC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[246] FIFO Memory Aperture0 0 0x3CAB4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[247] FIFO Memory Aperture0 0 0x3D090 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[248] FIFO Memory Aperture0 0 0x3D670 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[249] FIFO Memory Aperture0 0 0x3DC54 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[24] FIFO Memory Aperture0 0 0x38B0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[250] FIFO Memory Aperture0 0 0x3E23C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[251] FIFO Memory Aperture0 0 0x3E828 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[252] FIFO Memory Aperture0 0 0x3EE18 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[253] FIFO Memory Aperture0 0 0x3F40C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[254] FIFO Memory Aperture0 0 0x3FA04 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[255] FIFO Memory Aperture0 0 0x40000 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[25] FIFO Memory Aperture0 0 0x3B14 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[26] FIFO Memory Aperture0 0 0x3D7C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[27] FIFO Memory Aperture0 0 0x3FE8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[28] FIFO Memory Aperture0 0 0x4258 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[29] FIFO Memory Aperture0 0 0x44CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[2] FIFO Memory Aperture0 0 0x80C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[30] FIFO Memory Aperture0 0 0x4744 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[31] FIFO Memory Aperture0 0 0x49C0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[32] FIFO Memory Aperture0 0 0x4C40 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[33] FIFO Memory Aperture0 0 0x4EC4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[34] FIFO Memory Aperture0 0 0x514C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[35] FIFO Memory Aperture0 0 0x53D8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[36] FIFO Memory Aperture0 0 0x5668 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[37] FIFO Memory Aperture0 0 0x58FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[38] FIFO Memory Aperture0 0 0x5B94 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[39] FIFO Memory Aperture0 0 0x5E30 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[3] FIFO Memory Aperture0 0 0xA18 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[40] FIFO Memory Aperture0 0 0x60D0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[41] FIFO Memory Aperture0 0 0x6374 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[42] FIFO Memory Aperture0 0 0x661C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[43] FIFO Memory Aperture0 0 0x68C8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[44] FIFO Memory Aperture0 0 0x6B78 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[45] FIFO Memory Aperture0 0 0x6E2C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[46] FIFO Memory Aperture0 0 0x70E4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[47] FIFO Memory Aperture0 0 0x73A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[48] FIFO Memory Aperture0 0 0x7660 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[49] FIFO Memory Aperture0 0 0x7924 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[4] FIFO Memory Aperture0 0 0xC28 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[50] FIFO Memory Aperture0 0 0x7BEC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[51] FIFO Memory Aperture0 0 0x7EB8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[52] FIFO Memory Aperture0 0 0x8188 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[53] FIFO Memory Aperture0 0 0x845C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[54] FIFO Memory Aperture0 0 0x8734 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[55] FIFO Memory Aperture0 0 0x8A10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[56] FIFO Memory Aperture0 0 0x8CF0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[57] FIFO Memory Aperture0 0 0x8FD4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[58] FIFO Memory Aperture0 0 0x92BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[59] FIFO Memory Aperture0 0 0x95A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[5] FIFO Memory Aperture0 0 0xE3C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[60] FIFO Memory Aperture0 0 0x9898 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[61] FIFO Memory Aperture0 0 0x9B8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[62] FIFO Memory Aperture0 0 0x9E84 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[63] FIFO Memory Aperture0 0 0xA180 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[64] FIFO Memory Aperture0 0 0xA480 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[65] FIFO Memory Aperture0 0 0xA784 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[66] FIFO Memory Aperture0 0 0xAA8C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[67] FIFO Memory Aperture0 0 0xAD98 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[68] FIFO Memory Aperture0 0 0xB0A8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[69] FIFO Memory Aperture0 0 0xB3BC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[6] FIFO Memory Aperture0 0 0x1054 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[70] FIFO Memory Aperture0 0 0xB6D4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[71] FIFO Memory Aperture0 0 0xB9F0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[72] FIFO Memory Aperture0 0 0xBD10 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[73] FIFO Memory Aperture0 0 0xC034 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[74] FIFO Memory Aperture0 0 0xC35C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[75] FIFO Memory Aperture0 0 0xC688 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[76] FIFO Memory Aperture0 0 0xC9B8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[77] FIFO Memory Aperture0 0 0xCCEC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[78] FIFO Memory Aperture0 0 0xD024 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[79] FIFO Memory Aperture0 0 0xD360 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[7] FIFO Memory Aperture0 0 0x1270 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[80] FIFO Memory Aperture0 0 0xD6A0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[81] FIFO Memory Aperture0 0 0xD9E4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[82] FIFO Memory Aperture0 0 0xDD2C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[83] FIFO Memory Aperture0 0 0xE078 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[84] FIFO Memory Aperture0 0 0xE3C8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[85] FIFO Memory Aperture0 0 0xE71C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[86] FIFO Memory Aperture0 0 0xEA74 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[87] FIFO Memory Aperture0 0 0xEDD0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[88] FIFO Memory Aperture0 0 0xF130 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[89] FIFO Memory Aperture0 0 0xF494 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[8] FIFO Memory Aperture0 0 0x1490 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[90] FIFO Memory Aperture0 0 0xF7FC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[91] FIFO Memory Aperture0 0 0xFB68 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[92] FIFO Memory Aperture0 0 0xFED8 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[93] FIFO Memory Aperture0 0 0x1024C 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[94] FIFO Memory Aperture0 0 0x105C4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[95] FIFO Memory Aperture0 0 0x10940 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[96] FIFO Memory Aperture0 0 0x10CC0 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[97] FIFO Memory Aperture0 0 0x11044 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[98] FIFO Memory Aperture0 0 0x113CC 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[99] FIFO Memory Aperture0 0 0x11758 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 FIFO[9] FIFO Memory Aperture0 0 0x16B4 32 read-write n 0x0 0x0 DATA Data to Read or Data to Write 0 32 IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 ACKRCV Boot Acknowledge Interrupt Disable 28 1 ACKRCVE Boot Acknowledge Error Interrupt Disable 29 1 BLKE Data Block Ended Interrupt Disable 3 1 BLKOVRE DMA Block Overrun Error Interrupt Disable 24 1 CMDRDY Command Ready Interrupt Disable 0 1 CSRCV Completion Signal received interrupt Disable 13 1 CSTOE Completion Signal Time out Error Interrupt Disable 23 1 DCRCE Data CRC Error Interrupt Disable 21 1 DTIP Data Transfer in Progress Interrupt Disable 4 1 DTOE Data Time-out Error Interrupt Disable 22 1 FIFOEMPTY FIFO empty Interrupt Disable 26 1 NOTBUSY Data Not Busy Interrupt Disable 5 1 OVRE Overrun Interrupt Disable 30 1 RCRCE Response CRC Error Interrupt Disable 18 1 RDIRE Response Direction Error Interrupt Disable 17 1 RENDE Response End Bit Error Interrupt Disable 19 1 RINDE Response Index Error Interrupt Disable 16 1 RTOE Response Time-out Error Interrupt Disable 20 1 RXRDY Receiver Ready Interrupt Disable 1 1 SDIOIRQA SDIO Interrupt for Slot A Interrupt Disable 8 1 SDIOWAIT SDIO Read Wait Operation Status Interrupt Disable 12 1 TXRDY Transmit Ready Interrupt Disable 2 1 UNRE Underrun Interrupt Disable 31 1 XFRDONE Transfer Done Interrupt Disable 27 1 IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 ACKRCV Boot Acknowledge Interrupt Enable 28 1 ACKRCVE Boot Acknowledge Error Interrupt Enable 29 1 BLKE Data Block Ended Interrupt Enable 3 1 BLKOVRE DMA Block Overrun Error Interrupt Enable 24 1 CMDRDY Command Ready Interrupt Enable 0 1 CSRCV Completion Signal Received Interrupt Enable 13 1 CSTOE Completion Signal Timeout Error Interrupt Enable 23 1 DCRCE Data CRC Error Interrupt Enable 21 1 DTIP Data Transfer in Progress Interrupt Enable 4 1 DTOE Data Time-out Error Interrupt Enable 22 1 FIFOEMPTY FIFO empty Interrupt enable 26 1 NOTBUSY Data Not Busy Interrupt Enable 5 1 OVRE Overrun Interrupt Enable 30 1 RCRCE Response CRC Error Interrupt Enable 18 1 RDIRE Response Direction Error Interrupt Enable 17 1 RENDE Response End Bit Error Interrupt Enable 19 1 RINDE Response Index Error Interrupt Enable 16 1 RTOE Response Time-out Error Interrupt Enable 20 1 RXRDY Receiver Ready Interrupt Enable 1 1 SDIOIRQA SDIO Interrupt for Slot A Interrupt Enable 8 1 SDIOWAIT SDIO Read Wait Operation Status Interrupt Enable 12 1 TXRDY Transmit Ready Interrupt Enable 2 1 UNRE Underrun Interrupt Enable 31 1 XFRDONE Transfer Done Interrupt enable 27 1 IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 ACKRCV Boot Operation Acknowledge Received Interrupt Mask 28 1 ACKRCVE Boot Operation Acknowledge Error Interrupt Mask 29 1 BLKE Data Block Ended Interrupt Mask 3 1 BLKOVRE DMA Block Overrun Error Interrupt Mask 24 1 CMDRDY Command Ready Interrupt Mask 0 1 CSRCV Completion Signal Received Interrupt Mask 13 1 CSTOE Completion Signal Time-out Error Interrupt Mask 23 1 DCRCE Data CRC Error Interrupt Mask 21 1 DTIP Data Transfer in Progress Interrupt Mask 4 1 DTOE Data Time-out Error Interrupt Mask 22 1 FIFOEMPTY FIFO Empty Interrupt Mask 26 1 NOTBUSY Data Not Busy Interrupt Mask 5 1 OVRE Overrun Interrupt Mask 30 1 RCRCE Response CRC Error Interrupt Mask 18 1 RDIRE Response Direction Error Interrupt Mask 17 1 RENDE Response End Bit Error Interrupt Mask 19 1 RINDE Response Index Error Interrupt Mask 16 1 RTOE Response Time-out Error Interrupt Mask 20 1 RXRDY Receiver Ready Interrupt Mask 1 1 SDIOIRQA SDIO Interrupt for Slot A Interrupt Mask 8 1 SDIOWAIT SDIO Read Wait Operation Status Interrupt Mask 12 1 TXRDY Transmit Ready Interrupt Mask 2 1 UNRE Underrun Interrupt Mask 31 1 XFRDONE Transfer Done Interrupt Mask 27 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 CLKDIV Clock Divider 0 8 CLKODD Clock divider is odd 16 1 FBYTE Force Byte Transfer 13 1 PADV Padding Value 14 1 PWSDIV Power Saving Divider 8 3 RDPROOF Read Proof Enable 11 1 WRPROOF Write Proof Enable 12 1 RDR Receive Data Register 0x30 32 read-only n 0x0 0x0 DATA Data to Read 0 32 RSPR0 Response Register 0x20 32 read-only n RSP Response 0 32 read-only RSPR1 Response Register 0x24 32 read-only n RSP Response 0 32 read-only RSPR2 Response Register 0x28 32 read-only n RSP Response 0 32 read-only RSPR3 Response Register 0x2C 32 read-only n RSP Response 0 32 read-only RSPR[0] Response Register 0 0x40 32 read-only n 0x0 0x0 RSP Response 0 32 RSPR[1] Response Register 0 0x64 32 read-only n 0x0 0x0 RSP Response 0 32 RSPR[2] Response Register 0 0x8C 32 read-only n 0x0 0x0 RSP Response 0 32 RSPR[3] Response Register 0 0xB8 32 read-only n 0x0 0x0 RSP Response 0 32 SDCR SD/SDIO Card Register 0xC 32 read-write n 0x0 0x0 SDCBUS SDCard/SDIO Bus Width 6 2 SDCBUSSelect _1 1 bit 0 _4 4 bits 2 _8 8 bits 3 SDCSEL SDCard/SDIO Slot 0 2 SDCSELSelect SLOTA Slot A is selected. 0 SR Status Register 0x40 32 read-only n 0x0 0x0 ACKRCV Boot Operation Acknowledge Received (cleared on read) 28 1 ACKRCVE Boot Operation Acknowledge Error (cleared on read) 29 1 BLKE Data Block Ended (cleared on read) 3 1 BLKOVRE DMA Block Overrun Error (cleared on read) 24 1 CMDRDY Command Ready (cleared by writing in HSMCI_CMDR) 0 1 CSRCV CE-ATA Completion Signal Received (cleared on read) 13 1 CSTOE Completion Signal Time-out Error (cleared on read) 23 1 DCRCE Data CRC Error (cleared on read) 21 1 DTIP Data Transfer in Progress (cleared at the end of CRC16 calculation) 4 1 DTOE Data Time-out Error (cleared on read) 22 1 FIFOEMPTY FIFO empty flag 26 1 NOTBUSY HSMCI Not Busy 5 1 OVRE Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) 30 1 RCRCE Response CRC Error (cleared by writing in HSMCI_CMDR) 18 1 RDIRE Response Direction Error (cleared by writing in HSMCI_CMDR) 17 1 RENDE Response End Bit Error (cleared by writing in HSMCI_CMDR) 19 1 RINDE Response Index Error (cleared by writing in HSMCI_CMDR) 16 1 RTOE Response Time-out Error (cleared by writing in HSMCI_CMDR) 20 1 RXRDY Receiver Ready (cleared by reading HSMCI_RDR) 1 1 SDIOIRQA SDIO Interrupt for Slot A (cleared on read) 8 1 SDIOWAIT SDIO Read Wait Operation Status 12 1 TXRDY Transmit Ready (cleared by writing in HSMCI_TDR) 2 1 UNRE Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL = 0) 31 1 XFRDONE Transfer Done flag 27 1 TDR Transmit Data Register 0x34 32 write-only n 0x0 0x0 DATA Data to Write 0 32 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protect Enable 0 1 WPKEY Write Protect Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5063497 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 ICM Integrity Check Monitor ICM 0x0 0x0 0x58 registers n ICM 32 CFG Configuration Register 0x0 32 read-write n 0x0 0x0 ASCD Automatic Switch To Compare Digest 8 1 BBC Bus Burden Control 4 4 DUALBUFF Dual Input Buffer 9 1 EOMDIS End of Monitoring Disable 1 1 SLBDIS Secondary List Branching Disable 2 1 UALGO User SHA Algorithm 13 3 UALGOSelect SHA1 SHA1 algorithm processed 0 SHA256 SHA256 algorithm processed 1 SHA224 SHA224 algorithm processed 4 UIHASH User Initial Hash Value 12 1 WBDIS Write Back Disable 0 1 CTRL Control Register 0x4 32 write-only n 0x0 0x0 DISABLE ICM Disable Register 1 1 ENABLE ICM Enable 0 1 REHASH Recompute Internal Hash 4 4 RMDIS Region Monitoring Disable 8 4 RMEN Region Monitoring Enable 12 4 SWRST Software Reset 2 1 DSCR Region Descriptor Area Start Address Register 0x30 32 read-write n 0x0 0x0 DASA Descriptor Area Start Address 6 26 HASH Region Hash Area Start Address Register 0x34 32 read-write n 0x0 0x0 HASA Hash Area Start Address 7 25 IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 RBE Region Bus Error Interrupt Disable 8 4 RDM Region Digest Mismatch Interrupt Disable 4 4 REC Region End bit Condition detected Interrupt Disable 16 4 RHC Region Hash Completed Interrupt Disable 0 4 RSU Region Status Updated Interrupt Disable 20 4 RWC Region Wrap Condition Detected Interrupt Disable 12 4 URAD Undefined Register Access Detection Interrupt Disable 24 1 IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 RBE Region Bus Error Interrupt Enable 8 4 RDM Region Digest Mismatch Interrupt Enable 4 4 REC Region End bit Condition Detected Interrupt Enable 16 4 RHC Region Hash Completed Interrupt Enable 0 4 RSU Region Status Updated Interrupt Disable 20 4 RWC Region Wrap Condition detected Interrupt Enable 12 4 URAD Undefined Register Access Detection Interrupt Enable 24 1 IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 RBE Region Bus Error Interrupt Mask 8 4 RDM Region Digest Mismatch Interrupt Mask 4 4 REC Region End bit Condition Detected Interrupt Mask 16 4 RHC Region Hash Completed Interrupt Mask 0 4 RSU Region Status Updated Interrupt Mask 20 4 RWC Region Wrap Condition Detected Interrupt Mask 12 4 URAD Undefined Register Access Detection Interrupt Mask 24 1 ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 RBE Region Bus Error 8 4 RDM Region Digest Mismatch 4 4 REC Region End bit Condition Detected 16 4 RHC Region Hash Completed 0 4 RSU Region Status Updated Detected 20 4 RWC Region Wrap Condition Detected 12 4 URAD Undefined Register Access Detection Status 24 1 SR Status Register 0x8 32 read-only n 0x0 0x0 ENABLE ICM Controller Enable Register 0 1 RAWRMDIS Region Monitoring Disabled Raw Status 8 4 RMDIS Region Monitoring Disabled Status 12 4 UASR Undefined Access Status Register 0x20 32 read-only n 0x0 0x0 URAT Undefined Register Access Trace 0 3 URATSelect UNSPEC_STRUCT_MEMBER Unspecified structure member set to one detected when the descriptor is loaded. 0 ICM_CFG_MODIFIED ICM_CFG modified during active monitoring. 1 ICM_DSCR_MODIFIED ICM_DSCR modified during active monitoring. 2 ICM_HASH_MODIFIED ICM_HASH modified during active monitoring 3 READ_ACCESS Write-only register read access 4 UIHVAL0 User Initial Hash Value 0 Register 0x38 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL1 User Initial Hash Value 0 Register 0x3C 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL2 User Initial Hash Value 0 Register 0x40 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL3 User Initial Hash Value 0 Register 0x44 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL4 User Initial Hash Value 0 Register 0x48 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL5 User Initial Hash Value 0 Register 0x4C 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL6 User Initial Hash Value 0 Register 0x50 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL7 User Initial Hash Value 0 Register 0x54 32 write-only n VAL Initial Hash Value 0 32 write-only UIHVAL[0] User Initial Hash Value 0 Register 0 0x70 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[1] User Initial Hash Value 0 Register 0 0xAC 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[2] User Initial Hash Value 0 Register 0 0xEC 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[3] User Initial Hash Value 0 Register 0 0x130 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[4] User Initial Hash Value 0 Register 0 0x178 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[5] User Initial Hash Value 0 Register 0 0x1C4 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[6] User Initial Hash Value 0 Register 0 0x214 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 UIHVAL[7] User Initial Hash Value 0 Register 0 0x268 32 write-only n 0x0 0x0 VAL Initial Hash Value 0 32 ISI Image Sensor Interface ISI 0x0 0x0 0x4000 registers n ISI 59 CFG1 ISI Configuration 1 Register 0x0 32 read-write n 0x0 0x0 CRC_SYNC Embedded Synchronization Correction 7 1 DISCR Disable Codec Request 11 1 EMB_SYNC Embedded Synchronization 6 1 FRATE Frame Rate [0..7] 8 3 FULL Full Mode is Allowed 12 1 GRAYLE Grayscale Little Endian 5 1 HSYNC_POL Horizontal Synchronization Polarity 2 1 PIXCLK_POL Pixel Clock Polarity 4 1 SFD Start of Frame Delay 24 8 SLD Start of Line Delay 16 8 THMASK Threshold Mask 13 2 THMASKSelect BEATS_4 Only 4 beats AHB burst allowed 0 BEATS_8 Only 4 and 8 beats AHB burst allowed 1 BEATS_16 4, 8 and 16 beats AHB burst allowed 2 VSYNC_POL Vertical Synchronization Polarity 3 1 CFG2 ISI Configuration 2 Register 0x4 32 read-write n 0x0 0x0 COL_SPACE Color Space for the Image Data 15 1 GRAYSCALE Grayscale Mode Format Enable 13 1 GS_MODE Grayscale Pixel Format Mode 11 1 IM_HSIZE Horizontal Size of the Image Sensor [0..2047] 16 11 IM_VSIZE Vertical Size of the Image Sensor [0..2047] 0 11 RGB_CFG RGB Pixel Mapping Configuration 30 2 RGB_CFGSelect DEFAULT Byte 0 R/G(MSB)Byte 1 G(LSB)/BByte 2 R/G(MSB)Byte 3 G(LSB)/B 0 MODE1 Byte 0 B/G(MSB)Byte 1 G(LSB)/RByte 2 B/G(MSB)Byte 3 G(LSB)/R 1 MODE2 Byte 0 G(LSB)/RByte 1 B/G(MSB)Byte 2 G(LSB)/RByte 3 B/G(MSB) 2 MODE3 Byte 0 G(LSB)/BByte 1 R/G(MSB)Byte 2 G(LSB)/BByte 3 R/G(MSB) 3 RGB_MODE RGB Input Mode 12 1 RGB_SWAP RGB Format Swap Mode 14 1 YCC_SWAP YCrCb Format Swap Mode 28 2 YCC_SWAPSelect DEFAULT Byte 0 Cb(i)Byte 1 Y(i)Byte 2 Cr(i)Byte 3 Y(i+1) 0 MODE1 Byte 0 Cr(i)Byte 1 Y(i)Byte 2 Cb(i)Byte 3 Y(i+1) 1 MODE2 Byte 0 Y(i)Byte 1 Cb(i)Byte 2 Y(i+1)Byte 3 Cr(i) 2 MODE3 Byte 0 Y(i)Byte 1 Cr(i)Byte 2 Y(i+1)Byte 3 Cb(i) 3 CR ISI Control Register 0x24 32 write-only n 0x0 0x0 ISI_CDC ISI Codec Request 8 1 ISI_DIS ISI Module Disable Request 1 1 ISI_EN ISI Module Enable Request 0 1 ISI_SRST ISI Software Reset Request 2 1 DMA_CHDR DMA Channel Disable Register 0x3C 32 write-only n 0x0 0x0 C_CH_DIS Codec Channel Disable Request 1 1 P_CH_DIS Preview Channel Disable Request 0 1 DMA_CHER DMA Channel Enable Register 0x38 32 write-only n 0x0 0x0 C_CH_EN Codec Channel Enable 1 1 P_CH_EN Preview Channel Enable 0 1 DMA_CHSR DMA Channel Status Register 0x40 32 read-only n 0x0 0x0 C_CH_S Code DMA Channel Status 1 1 P_CH_S Preview DMA Channel Status 0 1 DMA_C_ADDR DMA Codec Base Address Register 0x50 32 read-write n 0x0 0x0 C_ADDR Codec Image Base Address 2 30 DMA_C_CTRL DMA Codec Control Register 0x54 32 read-write n 0x0 0x0 C_DONE Codec Transfer Done 3 1 C_FETCH Descriptor Fetch Control Bit 0 1 C_IEN Transfer Done Flag Control 2 1 C_WB Descriptor Writeback Control Bit 1 1 DMA_C_DSCR DMA Codec Descriptor Address Register 0x58 32 read-write n 0x0 0x0 C_DSCR Codec Descriptor Base Address 2 30 DMA_P_ADDR DMA Preview Base Address Register 0x44 32 read-write n 0x0 0x0 P_ADDR Preview Image Base Address 2 30 DMA_P_CTRL DMA Preview Control Register 0x48 32 read-write n 0x0 0x0 P_DONE Preview Transfer Done 3 1 P_FETCH Descriptor Fetch Control Bit 0 1 P_IEN Transfer Done Flag Control 2 1 P_WB Descriptor Writeback Control Bit 1 1 DMA_P_DSCR DMA Preview Descriptor Address Register 0x4C 32 read-write n 0x0 0x0 P_DSCR Preview Descriptor Base Address 2 30 IDR ISI Interrupt Disable Register 0x30 32 write-only n 0x0 0x0 CRC_ERR Embedded Synchronization CRC Error Interrupt Disable 26 1 CXFR_DONE Codec DMA Transfer Done Interrupt Disable 17 1 C_OVR Codec Datapath Overflow Interrupt Disable 25 1 DIS_DONE Disable Done Interrupt Disable 1 1 FR_OVR Frame Rate Overflow Interrupt Disable 27 1 PXFR_DONE Preview DMA Transfer Done Interrupt Disable 16 1 P_OVR Preview Datapath Overflow Interrupt Disable 24 1 SRST Software Reset Interrupt Disable 2 1 VSYNC Vertical Synchronization Interrupt Disable 10 1 IER ISI Interrupt Enable Register 0x2C 32 write-only n 0x0 0x0 CRC_ERR Embedded Synchronization CRC Error Interrupt Enable 26 1 CXFR_DONE Codec DMA Transfer Done Interrupt Enable 17 1 C_OVR Codec Datapath Overflow Interrupt Enable 25 1 DIS_DONE Disable Done Interrupt Enable 1 1 FR_OVR Frame Rate Overflow Interrupt Enable 27 1 PXFR_DONE Preview DMA Transfer Done Interrupt Enable 16 1 P_OVR Preview Datapath Overflow Interrupt Enable 24 1 SRST Software Reset Interrupt Enable 2 1 VSYNC Vertical Synchronization Interrupt Enable 10 1 IMR ISI Interrupt Mask Register 0x34 32 read-only n 0x0 0x0 CRC_ERR CRC Synchronization Error 26 1 CXFR_DONE Codec DMA Transfer Completed 17 1 C_OVR Codec FIFO Overflow 25 1 DIS_DONE Module Disable Operation Completed 1 1 FR_OVR Frame Rate Overrun 27 1 PXFR_DONE Preview DMA Transfer Completed 16 1 P_OVR Preview FIFO Overflow 24 1 SRST Software Reset Completed 2 1 VSYNC Vertical Synchronization 10 1 PDECF ISI Preview Decimation Factor Register 0xC 32 read-write n 0x0 0x0 DEC_FACTOR Decimation Factor 0 8 PSIZE ISI Preview Size Register 0x8 32 read-write n 0x0 0x0 PREV_HSIZE Horizontal Size for the Preview Path 16 10 PREV_VSIZE Vertical Size for the Preview Path 0 10 R2Y_SET0 ISI Color Space Conversion RGB To YCrCb Set 0 Register 0x18 32 read-write n 0x0 0x0 C0 Color Space Conversion Matrix Coefficient C0 0 7 C1 Color Space Conversion Matrix Coefficient C1 8 7 C2 Color Space Conversion Matrix Coefficient C2 16 7 Roff Color Space Conversion Red Component Offset 24 1 R2Y_SET1 ISI Color Space Conversion RGB To YCrCb Set 1 Register 0x1C 32 read-write n 0x0 0x0 C3 Color Space Conversion Matrix Coefficient C3 0 7 C4 Color Space Conversion Matrix Coefficient C4 8 7 C5 Color Space Conversion Matrix Coefficient C5 16 7 Goff Color Space Conversion Green Component Offset 24 1 R2Y_SET2 ISI Color Space Conversion RGB To YCrCb Set 2 Register 0x20 32 read-write n 0x0 0x0 Boff Color Space Conversion Blue Component Offset 24 1 C6 Color Space Conversion Matrix Coefficient C6 0 7 C7 Color Space Conversion Matrix Coefficient C7 8 7 C8 Color Space Conversion Matrix Coefficient C8 16 7 SR ISI Status Register 0x28 32 read-only n 0x0 0x0 CDC_PND Pending Codec Request 8 1 CRC_ERR CRC Synchronization Error (cleared on read) 26 1 CXFR_DONE Codec DMA Transfer has Terminated (cleared on read) 17 1 C_OVR Codec Datapath Overflow (cleared on read) 25 1 DIS_DONE Module Disable Request has Terminated (cleared on read) 1 1 ENABLE Module Enable 0 1 FR_OVR Frame Rate Overrun (cleared on read) 27 1 PXFR_DONE Preview DMA Transfer has Terminated (cleared on read) 16 1 P_OVR Preview Datapath Overflow (cleared on read) 24 1 SIP Synchronization in Progress 19 1 SRST Module Software Reset Request has Terminated (cleared on read) 2 1 VSYNC Vertical Synchronization (cleared on read) 10 1 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key Password 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 4805449 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 Y2R_SET0 ISI Color Space Conversion YCrCb To RGB Set 0 Register 0x10 32 read-write n 0x0 0x0 C0 Color Space Conversion Matrix Coefficient C0 0 8 C1 Color Space Conversion Matrix Coefficient C1 8 8 C2 Color Space Conversion Matrix Coefficient C2 16 8 C3 Color Space Conversion Matrix Coefficient C3 24 8 Y2R_SET1 ISI Color Space Conversion YCrCb To RGB Set 1 Register 0x14 32 read-write n 0x0 0x0 C4 Color Space Conversion Matrix Coefficient C4 0 9 Cboff Color Space Conversion Blue Chrominance Default Offset 14 1 Croff Color Space Conversion Red Chrominance Default Offset 13 1 Yoff Color Space Conversion Luminance Default Offset 12 1 LOCKBIT LOCKBIT 0x0 0x0 0x4 registers n WORD0 Lock Bits Word 0 0x0 32 read-write n 0x0 0x0 LOCK_REGION_0 Lock Region 0 0 1 LOCK_REGION_1 Lock Region 1 1 1 LOCK_REGION_10 Lock Region 10 10 1 LOCK_REGION_11 Lock Region 11 11 1 LOCK_REGION_12 Lock Region 12 12 1 LOCK_REGION_13 Lock Region 13 13 1 LOCK_REGION_14 Lock Region 14 14 1 LOCK_REGION_15 Lock Region 15 15 1 LOCK_REGION_16 Lock Region 16 16 1 LOCK_REGION_17 Lock Region 17 17 1 LOCK_REGION_18 Lock Region 18 18 1 LOCK_REGION_19 Lock Region 19 19 1 LOCK_REGION_2 Lock Region 2 2 1 LOCK_REGION_20 Lock Region 20 20 1 LOCK_REGION_21 Lock Region 21 21 1 LOCK_REGION_22 Lock Region 22 22 1 LOCK_REGION_23 Lock Region 23 23 1 LOCK_REGION_24 Lock Region 24 24 1 LOCK_REGION_25 Lock Region 25 25 1 LOCK_REGION_26 Lock Region 26 26 1 LOCK_REGION_27 Lock Region 27 27 1 LOCK_REGION_28 Lock Region 28 28 1 LOCK_REGION_29 Lock Region 29 29 1 LOCK_REGION_3 Lock Region 3 3 1 LOCK_REGION_30 Lock Region 30 30 1 LOCK_REGION_31 Lock Region 31 31 1 LOCK_REGION_4 Lock Region 4 4 1 LOCK_REGION_5 Lock Region 5 5 1 LOCK_REGION_6 Lock Region 6 6 1 LOCK_REGION_7 Lock Region 7 7 1 LOCK_REGION_8 Lock Region 8 8 1 LOCK_REGION_9 Lock Region 9 9 1 MATRIX AHB Bus Matrix MATRIX 0x0 0x0 0x4000 registers n CCFG_CAN0 CAN0 Configuration Register 0x110 32 read-write n 0x0 0x0 CAN0DMABA CAN0 DMA Base Address 16 16 CCFG_SMCNFCS SMC NAND Flash Chip Select Configuration Register 0x124 32 read-write n 0x0 0x0 SDRAMEN SDRAM Enable 4 1 SMC_NFCS0 SMC NAND Flash Chip Select 0 Assignment 0 1 SMC_NFCS1 SMC NAND Flash Chip Select 1 Assignment 1 1 SMC_NFCS2 SMC NAND Flash Chip Select 2 Assignment 2 1 SMC_NFCS3 SMC NAND Flash Chip Select 3 Assignment 3 1 CCFG_SYSIO System I/O and CAN1 Configuration Register 0x114 32 read-write n 0x0 0x0 CAN1DMABA CAN1 DMA Base Address 16 16 SYSIO12 PB12 or ERASE Assignment 12 1 SYSIO4 PB4 or TDI Assignment 4 1 SYSIO5 PB5 or TDO/TRACESWO Assignment 5 1 SYSIO6 PB6 or TMS/SWDIO Assignment 6 1 SYSIO7 PB7 or TCK/SWCLK Assignment 7 1 MCFG0 Master Configuration Register 0 0x0 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG1 Master Configuration Register 1 0x4 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG10 Master Configuration Register 10 0x28 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG11 Master Configuration Register 11 0x2C 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG2 Master Configuration Register 2 0x8 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG3 Master Configuration Register 3 0xC 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG4 Master Configuration Register 4 0x10 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG5 Master Configuration Register 5 0x14 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG6 Master Configuration Register 6 0x18 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG8 Master Configuration Register 8 0x20 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG9 Master Configuration Register 9 0x24 32 read-write n 0x0 ULBT Undefined Length Burst Type 0 3 read-write UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0x0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 0x1 4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 0x2 8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 0x3 16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 0x4 32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 0x5 64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 0x6 128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 0x7 MCFG[0] Master Configuration Register 0 0x0 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[10] Master Configuration Register 0 0xDC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[11] Master Configuration Register 0 0x108 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[1] Master Configuration Register 0 0x4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[2] Master Configuration Register 0 0xC 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[3] Master Configuration Register 0 0x18 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[4] Master Configuration Register 0 0x28 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[5] Master Configuration Register 0 0x3C 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[6] Master Configuration Register 0 0x54 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[7] Master Configuration Register 0 0x70 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[8] Master Configuration Register 0 0x90 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MCFG[9] Master Configuration Register 0 0xB4 32 read-write n 0x0 0x0 ULBT Undefined Length Burst Type 0 3 ULBTSelect UNLTD_LENGTH Unlimited Length Burst-No predicted end of burst is generated, therefore INCR bursts coming from this master can only be broken if the Slave Slot Cycle Limit is reached. If the Slot Cycle Limit is not reached, the burst is normally completed by the master, at the latest, on the next AHB 1-Kbyte address boundary, allowing up to 256-beat word bursts or 128-beat double-word bursts.This value should not be used in the very particular case of a master capable of performing back-to-back undefined length bursts on a single slave, since this could indefinitely freeze the slave arbitration and thus prevent another master from accessing this slave. 0 SINGLE_ACCESS Single Access-The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst or bursts sequence. 1 _4BEAT_BURST 4-beat Burst-The undefined length burst or bursts sequence is split into 4-beat bursts or less, allowing re-arbitration every 4 beats. 2 _8BEAT_BURST 8-beat Burst-The undefined length burst or bursts sequence is split into 8-beat bursts or less, allowing re-arbitration every 8 beats. 3 _16BEAT_BURST 16-beat Burst-The undefined length burst or bursts sequence is split into 16-beat bursts or less, allowing re-arbitration every 16 beats. 4 _32BEAT_BURST 32-beat Burst -The undefined length burst or bursts sequence is split into 32-beat bursts or less, allowing re-arbitration every 32 beats. 5 _64BEAT_BURST 64-beat Burst-The undefined length burst or bursts sequence is split into 64-beat bursts or less, allowing re-arbitration every 64 beats. 6 _128BEAT_BURST 128-beat Burst-The undefined length burst or bursts sequence is split into 128-beat bursts or less, allowing re-arbitration every 128 beats. 7 MRCR Master Remap Control Register 0x100 32 read-write n 0x0 0x0 RCB0 Remap Command Bit for Master 0 0 1 RCB1 Remap Command Bit for Master 1 1 1 RCB10 Remap Command Bit for Master 10 10 1 RCB11 Remap Command Bit for Master 11 11 1 RCB2 Remap Command Bit for Master 2 2 1 RCB3 Remap Command Bit for Master 3 3 1 RCB4 Remap Command Bit for Master 4 4 1 RCB5 Remap Command Bit for Master 5 5 1 RCB6 Remap Command Bit for Master 6 6 1 RCB8 Remap Command Bit for Master 8 8 1 RCB9 Remap Command Bit for Master 9 9 1 PRAS0 Priority Register A for Slave 0 0x80 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRAS1 Priority Register A for Slave 1 0x88 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRAS2 Priority Register A for Slave 2 0x90 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRAS3 Priority Register A for Slave 3 0x98 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRAS4 Priority Register A for Slave 4 0xA0 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRAS5 Priority Register A for Slave 5 0xA8 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRAS6 Priority Register A for Slave 6 0xB0 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRAS7 Priority Register A for Slave 7 0xB8 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRAS8 Priority Register A for Slave 8 0xC0 32 read-write n 0x0 M0PR Master 0 Priority 0 2 read-write M1PR Master 1 Priority 4 2 read-write M2PR Master 2 Priority 8 2 read-write M3PR Master 3 Priority 12 2 read-write M4PR Master 4 Priority 16 2 read-write M5PR Master 5 Priority 20 2 read-write M6PR Master 6 Priority 24 2 read-write PRBS0 Priority Register B for Slave 0 0x84 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS1 Priority Register B for Slave 1 0x8C 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS2 Priority Register B for Slave 2 0x94 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS3 Priority Register B for Slave 3 0x9C 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS4 Priority Register B for Slave 4 0xA4 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS5 Priority Register B for Slave 5 0xAC 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS6 Priority Register B for Slave 6 0xB4 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS7 Priority Register B for Slave 7 0xBC 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PRBS8 Priority Register B for Slave 8 0xC4 32 read-write n 0x0 M10PR Master 10 Priority 8 2 read-write M11PR Master 11 Priority 12 2 read-write M8PR Master 8 Priority 0 2 read-write M9PR Master 9 Priority 4 2 read-write PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x80 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x84 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 PR[1]-MATRIX_PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x108 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[1]-MATRIX_PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x10C 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x198 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x19C 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x230 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x234 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x2D0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x2D4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x378 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x37C 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 PR[6]-MATRIX_PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x428 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[6]-MATRIX_PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x42C 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 PR[7]-MATRIX_PR[6]-MATRIX_PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x4E0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[7]-MATRIX_PR[6]-MATRIX_PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x4E4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 PR[8]-MATRIX_PR[7]-MATRIX_PR[6]-MATRIX_PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRAS Priority Register A for Slave 0 0x5A0 32 read-write n 0x0 0x0 M0PR Master 0 Priority 0 2 M1PR Master 1 Priority 4 2 M2PR Master 2 Priority 8 2 M3PR Master 3 Priority 12 2 M4PR Master 4 Priority 16 2 M5PR Master 5 Priority 20 2 M6PR Master 6 Priority 24 2 PR[8]-MATRIX_PR[7]-MATRIX_PR[6]-MATRIX_PR[5]-MATRIX_PR[4]-MATRIX_PR[3]-MATRIX_PR[2]-MATRIX_PR[1]-MATRIX_PR[0]-MATRIX_PRBS Priority Register B for Slave 0 0x5A4 32 read-write n 0x0 0x0 M10PR Master 10 Priority 8 2 M11PR Master 11 Priority 12 2 M8PR Master 8 Priority 0 2 M9PR Master 9 Priority 4 2 SCFG0 Slave Configuration Register 0x40 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG1 Slave Configuration Register 0x44 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG2 Slave Configuration Register 0x48 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG3 Slave Configuration Register 0x4C 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG4 Slave Configuration Register 0x50 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG5 Slave Configuration Register 0x54 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG6 Slave Configuration Register 0x58 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG7 Slave Configuration Register 0x5C 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG8 Slave Configuration Register 0x60 32 read-write n DEFMSTR_TYPE Default Master Type 16 2 read-write NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0x0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 0x1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 0x2 FIXED_DEFMSTR Fixed Default Master 18 4 read-write SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 read-write SCFG[0] Slave Configuration Register 0 0x80 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG[1] Slave Configuration Register 0 0xC4 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG[2] Slave Configuration Register 0 0x10C 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG[3] Slave Configuration Register 0 0x158 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG[4] Slave Configuration Register 0 0x1A8 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG[5] Slave Configuration Register 0 0x1FC 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG[6] Slave Configuration Register 0 0x254 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG[7] Slave Configuration Register 0 0x2B0 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 SCFG[8] Slave Configuration Register 0 0x310 32 read-write n 0x0 0x0 DEFMSTR_TYPE Default Master Type 16 2 DEFMSTR_TYPESelect NONE No Default Master-At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters.This results in a one clock cycle latency for the first access of a burst transfer or for a single access. 0 LAST Last Default Master-At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it.This results in not having one clock cycle latency when the last master tries to access the slave again. 1 FIXED Fixed Default Master-At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field.This results in not having one clock cycle latency when the fixed master tries to access the slave again. 2 FIXED_DEFMSTR Fixed Default Master 18 4 SLOT_CYCLE Maximum Bus Grant Duration for Masters 0 9 WPMR Write Protection Mode Register 0x1E4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5062996 WPSR Write Protection Status Register 0x1E8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 MCAN0 Controller Area Network 0 MCAN 0x0 0x0 0xFC registers n MCAN0_INT0 35 MCAN0 35 MCAN0_INT1 36 BTP Bit Timing and Prescaler Register 0x1C 32 read-write n 0x0 BRP Baud Rate Prescaler 16 10 read-write SJW (Re) Synchronization Jump Width 0 4 read-write TSEG1 Time Segment Before Sample Point 8 6 read-write TSEG2 Time Segment After Sample Point 4 4 read-write CCCR CC Control Register 0x18 32 read-write n 0x0 ASM Restricted Operation Mode (read/write, write protection against '1') 2 1 read-write NORMAL Normal CAN operation. 0 RESTRICTED Restricted operation mode active. 1 CCE Configuration Change Enable (read/write, write protection) 1 1 read-write PROTECTED The processor has no write access to the protected configuration registers. 0 CONFIGURABLE The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). 1 CME CAN Mode Enable (read/write, write protection) 8 2 read-write ISO11898_1 CAN operation according to ISO11898-1 enabled 0 FD CAN FD operation enabled 1 CMR CAN Mode Request (read/write) 10 2 read-write NO_CHANGE No mode change 0x0 FD Request CAN FD operation 0x1 FD_BITRATE_SWITCH Request CAN FD operation with bit rate switching 0x2 ISO11898_1 Request CAN operation according ISO11898-1 0x3 CSA Clock Stop Acknowledge (read-only) 3 1 read-write CSR Clock Stop Request (read/write) 4 1 read-write NO_CLOCK_STOP No clock stop is requested. 0 CLOCK_STOP Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. 1 DAR Disable Automatic Retransmission (read/write, write protection) 6 1 read-write AUTO_RETX Automatic retransmission of messages not transmitted successfully enabled. 0 NO_AUTO_RETX Automatic retransmission disabled. 1 FDBS CAN FD Bit Rate Switching (read-only) 13 1 read-write FDO CAN FD Operation (read-only) 12 1 read-write INIT Initialization (read/write) 0 1 read-write DISABLED Normal operation. 0 ENABLED Initialization is started. 1 MON Bus Monitoring Mode (read/write, write protection against '1') 5 1 read-write DISABLED Bus Monitoring mode is disabled. 0 ENABLED Bus Monitoring mode is enabled. 1 TEST Test Mode Enable (read/write, write protection against '1') 7 1 read-write DISABLED Normal operation, MCAN_TEST register holds reset values. 0 ENABLED Test mode, write access to MCAN_TEST register enabled. 1 TXP Transmit Pause (read/write, write protection) 14 1 read-write CUST Customer Register 0x8 32 read-write n 0x0 CSV Customer-specific Value 0 32 read-write ECR Error Counter Register 0x40 32 read-only n 0x0 CEL CAN Error Logging (cleared on read) 16 8 read-only REC Receive Error Counter 8 7 read-only RP Receive Error Passive 15 1 read-only TEC Transmit Error Counter 0 8 read-only FBTP Fast Bit Timing and Prescaler Register 0xC 32 read-write n 0x0 FBRP Fast Baud Rate Prescaler 16 5 read-write FSJW Fast (Re) Synchronization Jump Width 0 2 read-write FTSEG1 Fast Time Segment Before Sample Point 8 4 read-write FTSEG2 Fast Time Segment After Sample Point 4 3 read-write TDC Transceiver Delay Compensation 23 1 read-write DISABLED Transceiver Delay Compensation disabled. 0 ENABLED Transceiver Delay Compensation enabled. 1 TDCO Transceiver Delay Compensation Offset 24 5 read-write GFC Global Filter Configuration Register 0x80 32 read-write n 0x0 ANFE Accept Non-matching Frames Extended 2 2 read-write RX_FIFO_0 Message stored in Receive FIFO 0 0 RX_FIFO_1 Message stored in Receive FIFO 1 1 ANFS Accept Non-matching Frames Standard 4 2 read-write RX_FIFO_0 Message stored in Receive FIFO 0 0 RX_FIFO_1 Message stored in Receive FIFO 1 1 RRFE Reject Remote Frames Extended 0 1 read-write FILTER Filter remote frames with 29-bit extended IDs. 0 REJECT Reject all remote frames with 29-bit extended IDs. 1 RRFS Reject Remote Frames Standard 1 1 read-write FILTER Filter remote frames with 11-bit standard IDs. 0 REJECT Reject all remote frames with 11-bit standard IDs. 1 HPMS High Priority Message Status Register 0x94 32 read-only n 0x0 BIDX Buffer Index 0 6 read-only FIDX Filter Index 8 7 read-only FLST Filter List 15 1 read-only MSI Message Storage Indicator 6 2 read-only NO_FIFO_SEL No FIFO selected. 0x0 LOST FIFO message. 0x1 FIFO_0 Message stored in FIFO 0. 0x2 FIFO_1 Message stored in FIFO 1. 0x3 IE Interrupt Enable Register 0x54 32 read-write n 0x0 ACKEE Acknowledge Error Interrupt Enable 29 1 read-write BEE Bit Error Interrupt Enable 28 1 read-write BOE Bus_Off Status Interrupt Enable 25 1 read-write CRCEE CRC Error Interrupt Enable 27 1 read-write DRXE Message stored to Dedicated Receive Buffer Interrupt Enable 19 1 read-write ELOE Error Logging Overflow Interrupt Enable 22 1 read-write EPE Error Passive Interrupt Enable 23 1 read-write EWE Warning Status Interrupt Enable 24 1 read-write FOEE Format Error Interrupt Enable 30 1 read-write HPME High Priority Message Interrupt Enable 8 1 read-write MRAFE Message RAM Access Failure Interrupt Enable 17 1 read-write RF0FE Receive FIFO 0 Full Interrupt Enable 2 1 read-write RF0LE Receive FIFO 0 Message Lost Interrupt Enable 3 1 read-write RF0NE Receive FIFO 0 New Message Interrupt Enable 0 1 read-write RF0WE Receive FIFO 0 Watermark Reached Interrupt Enable 1 1 read-write RF1FE Receive FIFO 1 Full Interrupt Enable 6 1 read-write RF1LE Receive FIFO 1 Message Lost Interrupt Enable 7 1 read-write RF1NE Receive FIFO 1 New Message Interrupt Enable 4 1 read-write RF1WE Receive FIFO 1 Watermark Reached Interrupt Enable 5 1 read-write STEE Stuff Error Interrupt Enable 31 1 read-write TCE Transmission Completed Interrupt Enable 9 1 read-write TCFE Transmission Cancellation Finished Interrupt Enable 10 1 read-write TEFFE Tx Event FIFO Full Interrupt Enable 14 1 read-write TEFLE Tx Event FIFO Event Lost Interrupt Enable 15 1 read-write TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 read-write TFEE Tx FIFO Empty Interrupt Enable 11 1 read-write TOOE Timeout Occurred Interrupt Enable 18 1 read-write TSWE Timestamp Wraparound Interrupt Enable 16 1 read-write WDIE Watchdog Interrupt Enable 26 1 read-write ILE Interrupt Line Enable Register 0x5C 32 read-write n 0x0 EINT0 Enable Interrupt Line 0 0 1 read-write EINT1 Enable Interrupt Line 1 1 1 read-write ILS Interrupt Line Select Register 0x58 32 read-write n 0x0 ACKEL Acknowledge Error Interrupt Line 29 1 read-write BEL Bit Error Interrupt Line 28 1 read-write BOL Bus_Off Status Interrupt Line 25 1 read-write CRCEL CRC Error Interrupt Line 27 1 read-write DRXL Message stored to Dedicated Receive Buffer Interrupt Line 19 1 read-write ELOL Error Logging Overflow Interrupt Line 22 1 read-write EPL Error Passive Interrupt Line 23 1 read-write EWL Warning Status Interrupt Line 24 1 read-write FOEL Format Error Interrupt Line 30 1 read-write HPML High Priority Message Interrupt Line 8 1 read-write MRAFL Message RAM Access Failure Interrupt Line 17 1 read-write RF0FL Receive FIFO 0 Full Interrupt Line 2 1 read-write RF0LL Receive FIFO 0 Message Lost Interrupt Line 3 1 read-write RF0NL Receive FIFO 0 New Message Interrupt Line 0 1 read-write RF0WL Receive FIFO 0 Watermark Reached Interrupt Line 1 1 read-write RF1FL Receive FIFO 1 Full Interrupt Line 6 1 read-write RF1LL Receive FIFO 1 Message Lost Interrupt Line 7 1 read-write RF1NL Receive FIFO 1 New Message Interrupt Line 4 1 read-write RF1WL Receive FIFO 1 Watermark Reached Interrupt Line 5 1 read-write STEL Stuff Error Interrupt Line 31 1 read-write TCFL Transmission Cancellation Finished Interrupt Line 10 1 read-write TCL Transmission Completed Interrupt Line 9 1 read-write TEFFL Tx Event FIFO Full Interrupt Line 14 1 read-write TEFLL Tx Event FIFO Event Lost Interrupt Line 15 1 read-write TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 read-write TFEL Tx FIFO Empty Interrupt Line 11 1 read-write TOOL Timeout Occurred Interrupt Line 18 1 read-write TSWL Timestamp Wraparound Interrupt Line 16 1 read-write WDIL Watchdog Interrupt Line 26 1 read-write IR Interrupt Register 0x50 32 read-write n 0x0 ACKE Acknowledge Error 29 1 read-write BE Bit Error 28 1 read-write BO Bus_Off Status 25 1 read-write CRCE CRC Error 27 1 read-write DRX Message stored to Dedicated Receive Buffer 19 1 read-write ELO Error Logging Overflow 22 1 read-write EP Error Passive 23 1 read-write EW Warning Status 24 1 read-write FOE Format Error 30 1 read-write HPM High Priority Message 8 1 read-write MRAF Message RAM Access Failure 17 1 read-write RF0F Receive FIFO 0 Full 2 1 read-write RF0L Receive FIFO 0 Message Lost 3 1 read-write RF0N Receive FIFO 0 New Message 0 1 read-write RF0W Receive FIFO 0 Watermark Reached 1 1 read-write RF1F Receive FIFO 1 Full 6 1 read-write RF1L Receive FIFO 1 Message Lost 7 1 read-write RF1N Receive FIFO 1 New Message 4 1 read-write RF1W Receive FIFO 1 Watermark Reached 5 1 read-write STE Stuff Error 31 1 read-write TC Transmission Completed 9 1 read-write TCF Transmission Cancellation Finished 10 1 read-write TEFF Tx Event FIFO Full 14 1 read-write TEFL Tx Event FIFO Element Lost 15 1 read-write TEFN Tx Event FIFO New Entry 12 1 read-write TEFW Tx Event FIFO Watermark Reached 13 1 read-write TFE Tx FIFO Empty 11 1 read-write TOO Timeout Occurred 18 1 read-write TSW Timestamp Wraparound 16 1 read-write WDI Watchdog Interrupt 26 1 read-write MCAN_MCAN_BTP Bit Timing and Prescaler Register 0x1C 32 read-write n 0x0 0x0 BRP Baud Rate Prescaler 16 10 SJW (Re) Synchronization Jump Width 0 4 TSEG1 Time Segment Before Sample Point 8 6 TSEG2 Time Segment After Sample Point 4 4 MCAN_MCAN_CCCR CC Control Register 0x18 32 read-write n 0x0 0x0 ASM Restricted Operation Mode (read/write, write protection against '1') 2 1 ASMSelect NORMAL Normal CAN operation. 0 RESTRICTED Restricted operation mode active. 1 CCE Configuration Change Enable (read/write, write protection) 1 1 CCESelect PROTECTED The processor has no write access to the protected configuration registers. 0 CONFIGURABLE The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). 1 CME CAN Mode Enable (read/write, write protection) 8 2 CMESelect ISO11898_1 CAN operation according to ISO11898-1 enabled 0 FD CAN FD operation enabled 1 CMR CAN Mode Request (read/write) 10 2 CMRSelect NO_CHANGE No mode change 0 FD Request CAN FD operation 1 FD_BITRATE_SWITCH Request CAN FD operation with bit rate switching 2 ISO11898_1 Request CAN operation according ISO11898-1 3 CSA Clock Stop Acknowledge (read-only) 3 1 CSR Clock Stop Request (read/write) 4 1 CSRSelect NO_CLOCK_STOP No clock stop is requested. 0 CLOCK_STOP Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. 1 DAR Disable Automatic Retransmission (read/write, write protection) 6 1 DARSelect AUTO_RETX Automatic retransmission of messages not transmitted successfully enabled. 0 NO_AUTO_RETX Automatic retransmission disabled. 1 FDBS CAN FD Bit Rate Switching (read-only) 13 1 FDO CAN FD Operation (read-only) 12 1 INIT Initialization (read/write) 0 1 INITSelect DISABLED Normal operation. 0 ENABLED Initialization is started. 1 MON Bus Monitoring Mode (read/write, write protection against '1') 5 1 MONSelect DISABLED Bus Monitoring mode is disabled. 0 ENABLED Bus Monitoring mode is enabled. 1 TEST Test Mode Enable (read/write, write protection against '1') 7 1 TESTSelect DISABLED Normal operation, MCAN_TEST register holds reset values. 0 ENABLED Test mode, write access to MCAN_TEST register enabled. 1 TXP Transmit Pause (read/write, write protection) 14 1 MCAN_MCAN_CUST Customer Register 0x8 32 read-write n 0x0 0x0 CSV Customer-specific Value 0 32 MCAN_MCAN_ECR Error Counter Register 0x40 32 read-only n 0x0 0x0 CEL CAN Error Logging (cleared on read) 16 8 REC Receive Error Counter 8 7 RP Receive Error Passive 15 1 TEC Transmit Error Counter 0 8 MCAN_MCAN_FBTP Fast Bit Timing and Prescaler Register 0xC 32 read-write n 0x0 0x0 FBRP Fast Baud Rate Prescaler 16 5 FSJW Fast (Re) Synchronization Jump Width 0 2 FTSEG1 Fast Time Segment Before Sample Point 8 4 FTSEG2 Fast Time Segment After Sample Point 4 3 TDC Transceiver Delay Compensation 23 1 TDCSelect DISABLED Transceiver Delay Compensation disabled. 0 ENABLED Transceiver Delay Compensation enabled. 1 TDCO Transceiver Delay Compensation Offset 24 5 MCAN_MCAN_GFC Global Filter Configuration Register 0x80 32 read-write n 0x0 0x0 ANFE Accept Non-matching Frames Extended 2 2 ANFESelect RX_FIFO_0 Message stored in Receive FIFO 0 0 RX_FIFO_1 Message stored in Receive FIFO 1 1 ANFS Accept Non-matching Frames Standard 4 2 ANFSSelect RX_FIFO_0 Message stored in Receive FIFO 0 0 RX_FIFO_1 Message stored in Receive FIFO 1 1 RRFE Reject Remote Frames Extended 0 1 RRFESelect FILTER Filter remote frames with 29-bit extended IDs. 0 REJECT Reject all remote frames with 29-bit extended IDs. 1 RRFS Reject Remote Frames Standard 1 1 RRFSSelect FILTER Filter remote frames with 11-bit standard IDs. 0 REJECT Reject all remote frames with 11-bit standard IDs. 1 MCAN_MCAN_HPMS High Priority Message Status Register 0x94 32 read-only n 0x0 0x0 BIDX Buffer Index 0 6 FIDX Filter Index 8 7 FLST Filter List 15 1 MSI Message Storage Indicator 6 2 MSISelect NO_FIFO_SEL No FIFO selected. 0 LOST FIFO message. 1 FIFO_0 Message stored in FIFO 0. 2 FIFO_1 Message stored in FIFO 1. 3 MCAN_MCAN_IE Interrupt Enable Register 0x54 32 read-write n 0x0 0x0 ACKEE Acknowledge Error Interrupt Enable 29 1 BEE Bit Error Interrupt Enable 28 1 BOE Bus_Off Status Interrupt Enable 25 1 CRCEE CRC Error Interrupt Enable 27 1 DRXE Message stored to Dedicated Receive Buffer Interrupt Enable 19 1 ELOE Error Logging Overflow Interrupt Enable 22 1 EPE Error Passive Interrupt Enable 23 1 EWE Warning Status Interrupt Enable 24 1 FOEE Format Error Interrupt Enable 30 1 HPME High Priority Message Interrupt Enable 8 1 MRAFE Message RAM Access Failure Interrupt Enable 17 1 RF0FE Receive FIFO 0 Full Interrupt Enable 2 1 RF0LE Receive FIFO 0 Message Lost Interrupt Enable 3 1 RF0NE Receive FIFO 0 New Message Interrupt Enable 0 1 RF0WE Receive FIFO 0 Watermark Reached Interrupt Enable 1 1 RF1FE Receive FIFO 1 Full Interrupt Enable 6 1 RF1LE Receive FIFO 1 Message Lost Interrupt Enable 7 1 RF1NE Receive FIFO 1 New Message Interrupt Enable 4 1 RF1WE Receive FIFO 1 Watermark Reached Interrupt Enable 5 1 STEE Stuff Error Interrupt Enable 31 1 TCE Transmission Completed Interrupt Enable 9 1 TCFE Transmission Cancellation Finished Interrupt Enable 10 1 TEFFE Tx Event FIFO Full Interrupt Enable 14 1 TEFLE Tx Event FIFO Event Lost Interrupt Enable 15 1 TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 TFEE Tx FIFO Empty Interrupt Enable 11 1 TOOE Timeout Occurred Interrupt Enable 18 1 TSWE Timestamp Wraparound Interrupt Enable 16 1 WDIE Watchdog Interrupt Enable 26 1 MCAN_MCAN_ILE Interrupt Line Enable Register 0x5C 32 read-write n 0x0 0x0 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 MCAN_MCAN_ILS Interrupt Line Select Register 0x58 32 read-write n 0x0 0x0 ACKEL Acknowledge Error Interrupt Line 29 1 BEL Bit Error Interrupt Line 28 1 BOL Bus_Off Status Interrupt Line 25 1 CRCEL CRC Error Interrupt Line 27 1 DRXL Message stored to Dedicated Receive Buffer Interrupt Line 19 1 ELOL Error Logging Overflow Interrupt Line 22 1 EPL Error Passive Interrupt Line 23 1 EWL Warning Status Interrupt Line 24 1 FOEL Format Error Interrupt Line 30 1 HPML High Priority Message Interrupt Line 8 1 MRAFL Message RAM Access Failure Interrupt Line 17 1 RF0FL Receive FIFO 0 Full Interrupt Line 2 1 RF0LL Receive FIFO 0 Message Lost Interrupt Line 3 1 RF0NL Receive FIFO 0 New Message Interrupt Line 0 1 RF0WL Receive FIFO 0 Watermark Reached Interrupt Line 1 1 RF1FL Receive FIFO 1 Full Interrupt Line 6 1 RF1LL Receive FIFO 1 Message Lost Interrupt Line 7 1 RF1NL Receive FIFO 1 New Message Interrupt Line 4 1 RF1WL Receive FIFO 1 Watermark Reached Interrupt Line 5 1 STEL Stuff Error Interrupt Line 31 1 TCFL Transmission Cancellation Finished Interrupt Line 10 1 TCL Transmission Completed Interrupt Line 9 1 TEFFL Tx Event FIFO Full Interrupt Line 14 1 TEFLL Tx Event FIFO Event Lost Interrupt Line 15 1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 TFEL Tx FIFO Empty Interrupt Line 11 1 TOOL Timeout Occurred Interrupt Line 18 1 TSWL Timestamp Wraparound Interrupt Line 16 1 WDIL Watchdog Interrupt Line 26 1 MCAN_MCAN_IR Interrupt Register 0x50 32 read-write n 0x0 0x0 ACKE Acknowledge Error 29 1 BE Bit Error 28 1 BO Bus_Off Status 25 1 CRCE CRC Error 27 1 DRX Message stored to Dedicated Receive Buffer 19 1 ELO Error Logging Overflow 22 1 EP Error Passive 23 1 EW Warning Status 24 1 FOE Format Error 30 1 HPM High Priority Message 8 1 MRAF Message RAM Access Failure 17 1 RF0F Receive FIFO 0 Full 2 1 RF0L Receive FIFO 0 Message Lost 3 1 RF0N Receive FIFO 0 New Message 0 1 RF0W Receive FIFO 0 Watermark Reached 1 1 RF1F Receive FIFO 1 Full 6 1 RF1L Receive FIFO 1 Message Lost 7 1 RF1N Receive FIFO 1 New Message 4 1 RF1W Receive FIFO 1 Watermark Reached 5 1 STE Stuff Error 31 1 TC Transmission Completed 9 1 TCF Transmission Cancellation Finished 10 1 TEFF Tx Event FIFO Full 14 1 TEFL Tx Event FIFO Element Lost 15 1 TEFN Tx Event FIFO New Entry 12 1 TEFW Tx Event FIFO Watermark Reached 13 1 TFE Tx FIFO Empty 11 1 TOO Timeout Occurred 18 1 TSW Timestamp Wraparound 16 1 WDI Watchdog Interrupt 26 1 MCAN_MCAN_NDAT1 New Data 1 Register 0x98 32 read-write n 0x0 0x0 ND0 New Data 0 1 ND1 New Data 1 1 ND10 New Data 10 1 ND11 New Data 11 1 ND12 New Data 12 1 ND13 New Data 13 1 ND14 New Data 14 1 ND15 New Data 15 1 ND16 New Data 16 1 ND17 New Data 17 1 ND18 New Data 18 1 ND19 New Data 19 1 ND2 New Data 2 1 ND20 New Data 20 1 ND21 New Data 21 1 ND22 New Data 22 1 ND23 New Data 23 1 ND24 New Data 24 1 ND25 New Data 25 1 ND26 New Data 26 1 ND27 New Data 27 1 ND28 New Data 28 1 ND29 New Data 29 1 ND3 New Data 3 1 ND30 New Data 30 1 ND31 New Data 31 1 ND4 New Data 4 1 ND5 New Data 5 1 ND6 New Data 6 1 ND7 New Data 7 1 ND8 New Data 8 1 ND9 New Data 9 1 MCAN_MCAN_NDAT2 New Data 2 Register 0x9C 32 read-write n 0x0 0x0 ND32 New Data 0 1 ND33 New Data 1 1 ND34 New Data 2 1 ND35 New Data 3 1 ND36 New Data 4 1 ND37 New Data 5 1 ND38 New Data 6 1 ND39 New Data 7 1 ND40 New Data 8 1 ND41 New Data 9 1 ND42 New Data 10 1 ND43 New Data 11 1 ND44 New Data 12 1 ND45 New Data 13 1 ND46 New Data 14 1 ND47 New Data 15 1 ND48 New Data 16 1 ND49 New Data 17 1 ND50 New Data 18 1 ND51 New Data 19 1 ND52 New Data 20 1 ND53 New Data 21 1 ND54 New Data 22 1 ND55 New Data 23 1 ND56 New Data 24 1 ND57 New Data 25 1 ND58 New Data 26 1 ND59 New Data 27 1 ND60 New Data 28 1 ND61 New Data 29 1 ND62 New Data 30 1 ND63 New Data 31 1 MCAN_MCAN_PSR Protocol Status Register 0x44 32 read-only n 0x0 0x0 ACT Activity 3 2 ACTSelect SYNCHRONIZING Node is synchronizing on CAN communication 0 IDLE Node is neither receiver nor transmitter 1 RECEIVER Node is operating as receiver 2 TRANSMITTER Node is operating as transmitter 3 BO Bus_Off Status 7 1 EP Error Passive 5 1 EW Warning Status 6 1 FLEC Fast Last Error Code (set to 111 on read) 8 3 LEC Last Error Code (set to 111 on read) 0 3 LECSelect NO_ERROR No error occurred since LEC has been reset by successful reception or transmission. 0 STUFF_ERROR More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 1 FORM_ERROR A fixed format part of a received frame has the wrong format. 2 ACK_ERROR The message transmitted by the MCAN was not acknowledged by another node. 3 BIT1_ERROR During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 4 BIT0_ERROR During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 5 CRC_ERROR The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 6 NO_CHANGE Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. 7 RBRS BRS Flag of Last Received CAN FD Message (cleared on read) 12 1 REDL Received a CAN FD Message (cleared on read) 13 1 RESI ESI Flag of Last Received CAN FD Message (cleared on read) 11 1 MCAN_MCAN_RWD RAM Watchdog Register 0x14 32 read-write n 0x0 0x0 WDC Watchdog Configuration (read/write) 0 8 WDV Watchdog Value (read-only) 8 8 MCAN_MCAN_RXBC Receive Rx Buffer Configuration Register 0xAC 32 read-write n 0x0 0x0 RBSA Receive Buffer Start Address 2 14 MCAN_MCAN_RXESC Receive Buffer / FIFO Element Size Configuration Register 0xBC 32 read-write n 0x0 0x0 F0DS Receive FIFO 0 Data Field Size 0 3 F0DSSelect _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 F1DS Receive FIFO 1 Data Field Size 4 3 F1DSSelect _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 RBDS Receive Buffer Data Field Size 8 3 RBDSSelect _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 MCAN_MCAN_RXF0A Receive FIFO 0 Acknowledge Register 0xA8 32 read-write n 0x0 0x0 F0AI Receive FIFO 0 Acknowledge Index 0 6 MCAN_MCAN_RXF0C Receive FIFO 0 Configuration Register 0xA0 32 read-write n 0x0 0x0 F0OM FIFO 0 Operation Mode 31 1 F0S Receive FIFO 0 Start Address 16 7 F0SA Receive FIFO 0 Start Address 2 14 F0WM Receive FIFO 0 Watermark 24 7 MCAN_MCAN_RXF0S Receive FIFO 0 Status Register 0xA4 32 read-only n 0x0 0x0 F0F Receive FIFO 0 Fill Level 24 1 F0FL Receive FIFO 0 Fill Level 0 7 F0GI Receive FIFO 0 Get Index 8 6 F0PI Receive FIFO 0 Put Index 16 6 RF0L Receive FIFO 0 Message Lost 25 1 MCAN_MCAN_RXF1A Receive FIFO 1 Acknowledge Register 0xB8 32 read-write n 0x0 0x0 F1AI Receive FIFO 1 Acknowledge Index 0 6 MCAN_MCAN_RXF1C Receive FIFO 1 Configuration Register 0xB0 32 read-write n 0x0 0x0 F1OM FIFO 1 Operation Mode 31 1 F1S Receive FIFO 1 Start Address 16 7 F1SA Receive FIFO 1 Start Address 2 14 F1WM Receive FIFO 1 Watermark 24 7 MCAN_MCAN_RXF1S Receive FIFO 1 Status Register 0xB4 32 read-only n 0x0 0x0 DMS Debug Message Status 30 2 DMSSelect IDLE Idle state, wait for reception of debug messages, DMA request is cleared. 0 MSG_A Debug message A received. 1 MSG_AB Debug messages A, B received. 2 MSG_ABC Debug messages A, B, C received, DMA request is set. 3 F1F Receive FIFO 1 Fill Level 24 1 F1FL Receive FIFO 1 Fill Level 0 7 F1GI Receive FIFO 1 Get Index 8 6 F1PI Receive FIFO 1 Put Index 16 6 RF1L Receive FIFO 1 Message Lost 25 1 MCAN_MCAN_SIDFC Standard ID Filter Configuration Register 0x84 32 read-write n 0x0 0x0 FLSSA Filter List Standard Start Address 2 14 LSS List Size Standard 16 8 MCAN_MCAN_TEST Test Register 0x10 32 read-write n 0x0 0x0 LBCK Loop Back Mode (read/write) 4 1 LBCKSelect DISABLED Reset value. Loop Back mode is disabled. 0 ENABLED Loop Back mode is enabled (see Section 1.5.1.9). 1 RX Receive Pin (read-only) 7 1 TDCV Transceiver Delay Compensation Value (read-only) 8 6 TX Control of Transmit Pin (read/write) 5 2 TXSelect RESET Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. 0 SAMPLE_POINT_MONITORING Sample Point can be monitored at pin CANTX. 1 DOMINANT Dominant ('0') level at pin CANTX. 2 RECESSIVE Recessive ('1') at pin CANTX. 3 MCAN_MCAN_TOCC Timeout Counter Configuration Register 0x28 32 read-write n 0x0 0x0 ETOC Enable Timeout Counter 0 1 ETOCSelect NO_TIMEOUT Timeout Counter disabled. 0 TOS_CONTROLLED Timeout Counter enabled. 1 TOP Timeout Period 16 16 TOS Timeout Select 1 2 TOSSelect CONTINUOUS Continuous operation 0 TX_EV_TIMEOUT Timeout controlled by Tx Event FIFO 1 RX0_EV_TIMEOUT Timeout controlled by Receive FIFO 0 2 RX1_EV_TIMEOUT Timeout controlled by Receive FIFO 1 3 MCAN_MCAN_TOCV Timeout Counter Value Register 0x2C 32 read-write n 0x0 0x0 TOC Timeout Counter (cleared on write) 0 16 MCAN_MCAN_TSCC Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 0x0 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSSSelect ALWAYS_0 Timestamp counter value always 0x0000 0 TCP_INC Timestamp counter value incremented according to TCP 1 EXT_TIMESTAMP External timestamp counter value used 2 MCAN_MCAN_TSCV Timestamp Counter Value Register 0x24 32 read-write n 0x0 0x0 TSC Timestamp Counter (cleared on write) 0 16 MCAN_MCAN_TXBAR Transmit Buffer Add Request Register 0xD0 32 read-write n 0x0 0x0 AR0 Add Request for Transmit Buffer 0 0 1 AR1 Add Request for Transmit Buffer 1 1 1 AR10 Add Request for Transmit Buffer 10 10 1 AR11 Add Request for Transmit Buffer 11 11 1 AR12 Add Request for Transmit Buffer 12 12 1 AR13 Add Request for Transmit Buffer 13 13 1 AR14 Add Request for Transmit Buffer 14 14 1 AR15 Add Request for Transmit Buffer 15 15 1 AR16 Add Request for Transmit Buffer 16 16 1 AR17 Add Request for Transmit Buffer 17 17 1 AR18 Add Request for Transmit Buffer 18 18 1 AR19 Add Request for Transmit Buffer 19 19 1 AR2 Add Request for Transmit Buffer 2 2 1 AR20 Add Request for Transmit Buffer 20 20 1 AR21 Add Request for Transmit Buffer 21 21 1 AR22 Add Request for Transmit Buffer 22 22 1 AR23 Add Request for Transmit Buffer 23 23 1 AR24 Add Request for Transmit Buffer 24 24 1 AR25 Add Request for Transmit Buffer 25 25 1 AR26 Add Request for Transmit Buffer 26 26 1 AR27 Add Request for Transmit Buffer 27 27 1 AR28 Add Request for Transmit Buffer 28 28 1 AR29 Add Request for Transmit Buffer 29 29 1 AR3 Add Request for Transmit Buffer 3 3 1 AR30 Add Request for Transmit Buffer 30 30 1 AR31 Add Request for Transmit Buffer 31 31 1 AR4 Add Request for Transmit Buffer 4 4 1 AR5 Add Request for Transmit Buffer 5 5 1 AR6 Add Request for Transmit Buffer 6 6 1 AR7 Add Request for Transmit Buffer 7 7 1 AR8 Add Request for Transmit Buffer 8 8 1 AR9 Add Request for Transmit Buffer 9 9 1 MCAN_MCAN_TXBC Transmit Buffer Configuration Register 0xC0 32 read-write n 0x0 0x0 NDTB Number of Dedicated Transmit Buffers 16 6 TBSA Tx Buffers Start Address 2 14 TFQM Tx FIFO/Queue Mode 30 1 TFQS Transmit FIFO/Queue Size 24 6 MCAN_MCAN_TXBCF Transmit Buffer Cancellation Finished Register 0xDC 32 read-only n 0x0 0x0 CF0 Cancellation Finished for Transmit Buffer 0 0 1 CF1 Cancellation Finished for Transmit Buffer 1 1 1 CF10 Cancellation Finished for Transmit Buffer 10 10 1 CF11 Cancellation Finished for Transmit Buffer 11 11 1 CF12 Cancellation Finished for Transmit Buffer 12 12 1 CF13 Cancellation Finished for Transmit Buffer 13 13 1 CF14 Cancellation Finished for Transmit Buffer 14 14 1 CF15 Cancellation Finished for Transmit Buffer 15 15 1 CF16 Cancellation Finished for Transmit Buffer 16 16 1 CF17 Cancellation Finished for Transmit Buffer 17 17 1 CF18 Cancellation Finished for Transmit Buffer 18 18 1 CF19 Cancellation Finished for Transmit Buffer 19 19 1 CF2 Cancellation Finished for Transmit Buffer 2 2 1 CF20 Cancellation Finished for Transmit Buffer 20 20 1 CF21 Cancellation Finished for Transmit Buffer 21 21 1 CF22 Cancellation Finished for Transmit Buffer 22 22 1 CF23 Cancellation Finished for Transmit Buffer 23 23 1 CF24 Cancellation Finished for Transmit Buffer 24 24 1 CF25 Cancellation Finished for Transmit Buffer 25 25 1 CF26 Cancellation Finished for Transmit Buffer 26 26 1 CF27 Cancellation Finished for Transmit Buffer 27 27 1 CF28 Cancellation Finished for Transmit Buffer 28 28 1 CF29 Cancellation Finished for Transmit Buffer 29 29 1 CF3 Cancellation Finished for Transmit Buffer 3 3 1 CF30 Cancellation Finished for Transmit Buffer 30 30 1 CF31 Cancellation Finished for Transmit Buffer 31 31 1 CF4 Cancellation Finished for Transmit Buffer 4 4 1 CF5 Cancellation Finished for Transmit Buffer 5 5 1 CF6 Cancellation Finished for Transmit Buffer 6 6 1 CF7 Cancellation Finished for Transmit Buffer 7 7 1 CF8 Cancellation Finished for Transmit Buffer 8 8 1 CF9 Cancellation Finished for Transmit Buffer 9 9 1 MCAN_MCAN_TXBCIE Transmit Buffer Cancellation Finished Interrupt Enable Register 0xE4 32 read-write n 0x0 0x0 CFIE0 Cancellation Finished Interrupt Enable for Transmit Buffer 0 0 1 CFIE1 Cancellation Finished Interrupt Enable for Transmit Buffer 1 1 1 CFIE10 Cancellation Finished Interrupt Enable for Transmit Buffer 10 10 1 CFIE11 Cancellation Finished Interrupt Enable for Transmit Buffer 11 11 1 CFIE12 Cancellation Finished Interrupt Enable for Transmit Buffer 12 12 1 CFIE13 Cancellation Finished Interrupt Enable for Transmit Buffer 13 13 1 CFIE14 Cancellation Finished Interrupt Enable for Transmit Buffer 14 14 1 CFIE15 Cancellation Finished Interrupt Enable for Transmit Buffer 15 15 1 CFIE16 Cancellation Finished Interrupt Enable for Transmit Buffer 16 16 1 CFIE17 Cancellation Finished Interrupt Enable for Transmit Buffer 17 17 1 CFIE18 Cancellation Finished Interrupt Enable for Transmit Buffer 18 18 1 CFIE19 Cancellation Finished Interrupt Enable for Transmit Buffer 19 19 1 CFIE2 Cancellation Finished Interrupt Enable for Transmit Buffer 2 2 1 CFIE20 Cancellation Finished Interrupt Enable for Transmit Buffer 20 20 1 CFIE21 Cancellation Finished Interrupt Enable for Transmit Buffer 21 21 1 CFIE22 Cancellation Finished Interrupt Enable for Transmit Buffer 22 22 1 CFIE23 Cancellation Finished Interrupt Enable for Transmit Buffer 23 23 1 CFIE24 Cancellation Finished Interrupt Enable for Transmit Buffer 24 24 1 CFIE25 Cancellation Finished Interrupt Enable for Transmit Buffer 25 25 1 CFIE26 Cancellation Finished Interrupt Enable for Transmit Buffer 26 26 1 CFIE27 Cancellation Finished Interrupt Enable for Transmit Buffer 27 27 1 CFIE28 Cancellation Finished Interrupt Enable for Transmit Buffer 28 28 1 CFIE29 Cancellation Finished Interrupt Enable for Transmit Buffer 29 29 1 CFIE3 Cancellation Finished Interrupt Enable for Transmit Buffer 3 3 1 CFIE30 Cancellation Finished Interrupt Enable for Transmit Buffer 30 30 1 CFIE31 Cancellation Finished Interrupt Enable for Transmit Buffer 31 31 1 CFIE4 Cancellation Finished Interrupt Enable for Transmit Buffer 4 4 1 CFIE5 Cancellation Finished Interrupt Enable for Transmit Buffer 5 5 1 CFIE6 Cancellation Finished Interrupt Enable for Transmit Buffer 6 6 1 CFIE7 Cancellation Finished Interrupt Enable for Transmit Buffer 7 7 1 CFIE8 Cancellation Finished Interrupt Enable for Transmit Buffer 8 8 1 CFIE9 Cancellation Finished Interrupt Enable for Transmit Buffer 9 9 1 MCAN_MCAN_TXBCR Transmit Buffer Cancellation Request Register 0xD4 32 read-write n 0x0 0x0 CR0 Cancellation Request for Transmit Buffer 0 0 1 CR1 Cancellation Request for Transmit Buffer 1 1 1 CR10 Cancellation Request for Transmit Buffer 10 10 1 CR11 Cancellation Request for Transmit Buffer 11 11 1 CR12 Cancellation Request for Transmit Buffer 12 12 1 CR13 Cancellation Request for Transmit Buffer 13 13 1 CR14 Cancellation Request for Transmit Buffer 14 14 1 CR15 Cancellation Request for Transmit Buffer 15 15 1 CR16 Cancellation Request for Transmit Buffer 16 16 1 CR17 Cancellation Request for Transmit Buffer 17 17 1 CR18 Cancellation Request for Transmit Buffer 18 18 1 CR19 Cancellation Request for Transmit Buffer 19 19 1 CR2 Cancellation Request for Transmit Buffer 2 2 1 CR20 Cancellation Request for Transmit Buffer 20 20 1 CR21 Cancellation Request for Transmit Buffer 21 21 1 CR22 Cancellation Request for Transmit Buffer 22 22 1 CR23 Cancellation Request for Transmit Buffer 23 23 1 CR24 Cancellation Request for Transmit Buffer 24 24 1 CR25 Cancellation Request for Transmit Buffer 25 25 1 CR26 Cancellation Request for Transmit Buffer 26 26 1 CR27 Cancellation Request for Transmit Buffer 27 27 1 CR28 Cancellation Request for Transmit Buffer 28 28 1 CR29 Cancellation Request for Transmit Buffer 29 29 1 CR3 Cancellation Request for Transmit Buffer 3 3 1 CR30 Cancellation Request for Transmit Buffer 30 30 1 CR31 Cancellation Request for Transmit Buffer 31 31 1 CR4 Cancellation Request for Transmit Buffer 4 4 1 CR5 Cancellation Request for Transmit Buffer 5 5 1 CR6 Cancellation Request for Transmit Buffer 6 6 1 CR7 Cancellation Request for Transmit Buffer 7 7 1 CR8 Cancellation Request for Transmit Buffer 8 8 1 CR9 Cancellation Request for Transmit Buffer 9 9 1 MCAN_MCAN_TXBRP Transmit Buffer Request Pending Register 0xCC 32 read-only n 0x0 0x0 TRP0 Transmission Request Pending for Buffer 0 0 1 TRP1 Transmission Request Pending for Buffer 1 1 1 TRP10 Transmission Request Pending for Buffer 10 10 1 TRP11 Transmission Request Pending for Buffer 11 11 1 TRP12 Transmission Request Pending for Buffer 12 12 1 TRP13 Transmission Request Pending for Buffer 13 13 1 TRP14 Transmission Request Pending for Buffer 14 14 1 TRP15 Transmission Request Pending for Buffer 15 15 1 TRP16 Transmission Request Pending for Buffer 16 16 1 TRP17 Transmission Request Pending for Buffer 17 17 1 TRP18 Transmission Request Pending for Buffer 18 18 1 TRP19 Transmission Request Pending for Buffer 19 19 1 TRP2 Transmission Request Pending for Buffer 2 2 1 TRP20 Transmission Request Pending for Buffer 20 20 1 TRP21 Transmission Request Pending for Buffer 21 21 1 TRP22 Transmission Request Pending for Buffer 22 22 1 TRP23 Transmission Request Pending for Buffer 23 23 1 TRP24 Transmission Request Pending for Buffer 24 24 1 TRP25 Transmission Request Pending for Buffer 25 25 1 TRP26 Transmission Request Pending for Buffer 26 26 1 TRP27 Transmission Request Pending for Buffer 27 27 1 TRP28 Transmission Request Pending for Buffer 28 28 1 TRP29 Transmission Request Pending for Buffer 29 29 1 TRP3 Transmission Request Pending for Buffer 3 3 1 TRP30 Transmission Request Pending for Buffer 30 30 1 TRP31 Transmission Request Pending for Buffer 31 31 1 TRP4 Transmission Request Pending for Buffer 4 4 1 TRP5 Transmission Request Pending for Buffer 5 5 1 TRP6 Transmission Request Pending for Buffer 6 6 1 TRP7 Transmission Request Pending for Buffer 7 7 1 TRP8 Transmission Request Pending for Buffer 8 8 1 TRP9 Transmission Request Pending for Buffer 9 9 1 MCAN_MCAN_TXBTIE Transmit Buffer Transmission Interrupt Enable Register 0xE0 32 read-write n 0x0 0x0 TIE0 Transmission Interrupt Enable for Buffer 0 0 1 TIE1 Transmission Interrupt Enable for Buffer 1 1 1 TIE10 Transmission Interrupt Enable for Buffer 10 10 1 TIE11 Transmission Interrupt Enable for Buffer 11 11 1 TIE12 Transmission Interrupt Enable for Buffer 12 12 1 TIE13 Transmission Interrupt Enable for Buffer 13 13 1 TIE14 Transmission Interrupt Enable for Buffer 14 14 1 TIE15 Transmission Interrupt Enable for Buffer 15 15 1 TIE16 Transmission Interrupt Enable for Buffer 16 16 1 TIE17 Transmission Interrupt Enable for Buffer 17 17 1 TIE18 Transmission Interrupt Enable for Buffer 18 18 1 TIE19 Transmission Interrupt Enable for Buffer 19 19 1 TIE2 Transmission Interrupt Enable for Buffer 2 2 1 TIE20 Transmission Interrupt Enable for Buffer 20 20 1 TIE21 Transmission Interrupt Enable for Buffer 21 21 1 TIE22 Transmission Interrupt Enable for Buffer 22 22 1 TIE23 Transmission Interrupt Enable for Buffer 23 23 1 TIE24 Transmission Interrupt Enable for Buffer 24 24 1 TIE25 Transmission Interrupt Enable for Buffer 25 25 1 TIE26 Transmission Interrupt Enable for Buffer 26 26 1 TIE27 Transmission Interrupt Enable for Buffer 27 27 1 TIE28 Transmission Interrupt Enable for Buffer 28 28 1 TIE29 Transmission Interrupt Enable for Buffer 29 29 1 TIE3 Transmission Interrupt Enable for Buffer 3 3 1 TIE30 Transmission Interrupt Enable for Buffer 30 30 1 TIE31 Transmission Interrupt Enable for Buffer 31 31 1 TIE4 Transmission Interrupt Enable for Buffer 4 4 1 TIE5 Transmission Interrupt Enable for Buffer 5 5 1 TIE6 Transmission Interrupt Enable for Buffer 6 6 1 TIE7 Transmission Interrupt Enable for Buffer 7 7 1 TIE8 Transmission Interrupt Enable for Buffer 8 8 1 TIE9 Transmission Interrupt Enable for Buffer 9 9 1 MCAN_MCAN_TXBTO Transmit Buffer Transmission Occurred Register 0xD8 32 read-only n 0x0 0x0 TO0 Transmission Occurred for Buffer 0 0 1 TO1 Transmission Occurred for Buffer 1 1 1 TO10 Transmission Occurred for Buffer 10 10 1 TO11 Transmission Occurred for Buffer 11 11 1 TO12 Transmission Occurred for Buffer 12 12 1 TO13 Transmission Occurred for Buffer 13 13 1 TO14 Transmission Occurred for Buffer 14 14 1 TO15 Transmission Occurred for Buffer 15 15 1 TO16 Transmission Occurred for Buffer 16 16 1 TO17 Transmission Occurred for Buffer 17 17 1 TO18 Transmission Occurred for Buffer 18 18 1 TO19 Transmission Occurred for Buffer 19 19 1 TO2 Transmission Occurred for Buffer 2 2 1 TO20 Transmission Occurred for Buffer 20 20 1 TO21 Transmission Occurred for Buffer 21 21 1 TO22 Transmission Occurred for Buffer 22 22 1 TO23 Transmission Occurred for Buffer 23 23 1 TO24 Transmission Occurred for Buffer 24 24 1 TO25 Transmission Occurred for Buffer 25 25 1 TO26 Transmission Occurred for Buffer 26 26 1 TO27 Transmission Occurred for Buffer 27 27 1 TO28 Transmission Occurred for Buffer 28 28 1 TO29 Transmission Occurred for Buffer 29 29 1 TO3 Transmission Occurred for Buffer 3 3 1 TO30 Transmission Occurred for Buffer 30 30 1 TO31 Transmission Occurred for Buffer 31 31 1 TO4 Transmission Occurred for Buffer 4 4 1 TO5 Transmission Occurred for Buffer 5 5 1 TO6 Transmission Occurred for Buffer 6 6 1 TO7 Transmission Occurred for Buffer 7 7 1 TO8 Transmission Occurred for Buffer 8 8 1 TO9 Transmission Occurred for Buffer 9 9 1 MCAN_MCAN_TXEFA Transmit Event FIFO Acknowledge Register 0xF8 32 read-write n 0x0 0x0 EFAI Event FIFO Acknowledge Index 0 5 MCAN_MCAN_TXEFC Transmit Event FIFO Configuration Register 0xF0 32 read-write n 0x0 0x0 EFS Event FIFO Size 16 6 EFSA Event FIFO Start Address 2 14 EFWM Event FIFO Watermark 24 6 MCAN_MCAN_TXEFS Transmit Event FIFO Status Register 0xF4 32 read-only n 0x0 0x0 EFF Event FIFO Full 24 1 EFFL Event FIFO Fill Level 0 6 EFGI Event FIFO Get Index 8 5 EFPI Event FIFO Put Index 16 5 TEFL Tx Event FIFO Element Lost 25 1 MCAN_MCAN_TXESC Transmit Buffer Element Size Configuration Register 0xC8 32 read-write n 0x0 0x0 TBDS Tx Buffer Data Field Size 0 3 TBDSSelect _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48- byte data field 6 _64_BYTE 64-byte data field 7 MCAN_MCAN_TXFQS Transmit FIFO/Queue Status Register 0xC4 32 read-only n 0x0 0x0 TFFL Tx FIFO Free Level 0 6 TFGI Tx FIFO Get Index 8 5 TFQF Tx FIFO/Queue Full 21 1 TFQPI Tx FIFO/Queue Put Index 16 5 MCAN_MCAN_XIDAM Extended ID AND Mask Register 0x90 32 read-write n 0x0 0x0 EIDM Extended ID Mask 0 29 MCAN_MCAN_XIDFC Extended ID Filter Configuration Register 0x88 32 read-write n 0x0 0x0 FLESA Filter List Extended Start Address 2 14 LSE List Size Extended 16 7 NDAT1 New Data 1 Register 0x98 32 read-write n 0x0 ND0 New Data 0 1 read-write ND1 New Data 1 1 read-write ND10 New Data 10 1 read-write ND11 New Data 11 1 read-write ND12 New Data 12 1 read-write ND13 New Data 13 1 read-write ND14 New Data 14 1 read-write ND15 New Data 15 1 read-write ND16 New Data 16 1 read-write ND17 New Data 17 1 read-write ND18 New Data 18 1 read-write ND19 New Data 19 1 read-write ND2 New Data 2 1 read-write ND20 New Data 20 1 read-write ND21 New Data 21 1 read-write ND22 New Data 22 1 read-write ND23 New Data 23 1 read-write ND24 New Data 24 1 read-write ND25 New Data 25 1 read-write ND26 New Data 26 1 read-write ND27 New Data 27 1 read-write ND28 New Data 28 1 read-write ND29 New Data 29 1 read-write ND3 New Data 3 1 read-write ND30 New Data 30 1 read-write ND31 New Data 31 1 read-write ND4 New Data 4 1 read-write ND5 New Data 5 1 read-write ND6 New Data 6 1 read-write ND7 New Data 7 1 read-write ND8 New Data 8 1 read-write ND9 New Data 9 1 read-write NDAT2 New Data 2 Register 0x9C 32 read-write n 0x0 ND32 New Data 0 1 read-write ND33 New Data 1 1 read-write ND34 New Data 2 1 read-write ND35 New Data 3 1 read-write ND36 New Data 4 1 read-write ND37 New Data 5 1 read-write ND38 New Data 6 1 read-write ND39 New Data 7 1 read-write ND40 New Data 8 1 read-write ND41 New Data 9 1 read-write ND42 New Data 10 1 read-write ND43 New Data 11 1 read-write ND44 New Data 12 1 read-write ND45 New Data 13 1 read-write ND46 New Data 14 1 read-write ND47 New Data 15 1 read-write ND48 New Data 16 1 read-write ND49 New Data 17 1 read-write ND50 New Data 18 1 read-write ND51 New Data 19 1 read-write ND52 New Data 20 1 read-write ND53 New Data 21 1 read-write ND54 New Data 22 1 read-write ND55 New Data 23 1 read-write ND56 New Data 24 1 read-write ND57 New Data 25 1 read-write ND58 New Data 26 1 read-write ND59 New Data 27 1 read-write ND60 New Data 28 1 read-write ND61 New Data 29 1 read-write ND62 New Data 30 1 read-write ND63 New Data 31 1 read-write PSR Protocol Status Register 0x44 32 read-only n 0x0 ACT Activity 3 2 read-only SYNCHRONIZING Node is synchronizing on CAN communication 0x0 IDLE Node is neither receiver nor transmitter 0x1 RECEIVER Node is operating as receiver 0x2 TRANSMITTER Node is operating as transmitter 0x3 BO Bus_Off Status 7 1 read-only EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only FLEC Fast Last Error Code (set to 111 on read) 8 3 read-only LEC Last Error Code (set to 111 on read) 0 3 read-only NO_ERROR No error occurred since LEC has been reset by successful reception or transmission. 0x0 STUFF_ERROR More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 FORM_ERROR A fixed format part of a received frame has the wrong format. 0x2 ACK_ERROR The message transmitted by the MCAN was not acknowledged by another node. 0x3 BIT1_ERROR During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 0x4 BIT0_ERROR During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 0x5 CRC_ERROR The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 0x6 NO_CHANGE Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. 0x7 RBRS BRS Flag of Last Received CAN FD Message (cleared on read) 12 1 read-only REDL Received a CAN FD Message (cleared on read) 13 1 read-only RESI ESI Flag of Last Received CAN FD Message (cleared on read) 11 1 read-only RWD RAM Watchdog Register 0x14 32 read-write n 0x0 WDC Watchdog Configuration (read/write) 0 8 read-write WDV Watchdog Value (read-only) 8 8 read-write RXBC Receive Rx Buffer Configuration Register 0xAC 32 read-write n 0x0 RBSA Receive Buffer Start Address 2 14 read-write RXESC Receive Buffer / FIFO Element Size Configuration Register 0xBC 32 read-write n 0x0 F0DS Receive FIFO 0 Data Field Size 0 3 read-write 8_BYTE 8-byte data field 0x0 12_BYTE 12-byte data field 0x1 16_BYTE 16-byte data field 0x2 20_BYTE 20-byte data field 0x3 24_BYTE 24-byte data field 0x4 32_BYTE 32-byte data field 0x5 48_BYTE 48-byte data field 0x6 64_BYTE 64-byte data field 0x7 F1DS Receive FIFO 1 Data Field Size 4 3 read-write 8_BYTE 8-byte data field 0x0 12_BYTE 12-byte data field 0x1 16_BYTE 16-byte data field 0x2 20_BYTE 20-byte data field 0x3 24_BYTE 24-byte data field 0x4 32_BYTE 32-byte data field 0x5 48_BYTE 48-byte data field 0x6 64_BYTE 64-byte data field 0x7 RBDS Receive Buffer Data Field Size 8 3 read-write 8_BYTE 8-byte data field 0x0 12_BYTE 12-byte data field 0x1 16_BYTE 16-byte data field 0x2 20_BYTE 20-byte data field 0x3 24_BYTE 24-byte data field 0x4 32_BYTE 32-byte data field 0x5 48_BYTE 48-byte data field 0x6 64_BYTE 64-byte data field 0x7 RXF0A Receive FIFO 0 Acknowledge Register 0xA8 32 read-write n 0x0 F0AI Receive FIFO 0 Acknowledge Index 0 6 read-write RXF0C Receive FIFO 0 Configuration Register 0xA0 32 read-write n 0x0 F0OM FIFO 0 Operation Mode 31 1 read-write F0S Receive FIFO 0 Start Address 16 7 read-write F0SA Receive FIFO 0 Start Address 2 14 read-write F0WM Receive FIFO 0 Watermark 24 7 read-write RXF0S Receive FIFO 0 Status Register 0xA4 32 read-only n 0x0 F0F Receive FIFO 0 Fill Level 24 1 read-only F0FL Receive FIFO 0 Fill Level 0 7 read-only F0GI Receive FIFO 0 Get Index 8 6 read-only F0PI Receive FIFO 0 Put Index 16 6 read-only RF0L Receive FIFO 0 Message Lost 25 1 read-only RXF1A Receive FIFO 1 Acknowledge Register 0xB8 32 read-write n 0x0 F1AI Receive FIFO 1 Acknowledge Index 0 6 read-write RXF1C Receive FIFO 1 Configuration Register 0xB0 32 read-write n 0x0 F1OM FIFO 1 Operation Mode 31 1 read-write F1S Receive FIFO 1 Start Address 16 7 read-write F1SA Receive FIFO 1 Start Address 2 14 read-write F1WM Receive FIFO 1 Watermark 24 7 read-write RXF1S Receive FIFO 1 Status Register 0xB4 32 read-only n 0x0 DMS Debug Message Status 30 2 read-only IDLE Idle state, wait for reception of debug messages, DMA request is cleared. 0x0 MSG_A Debug message A received. 0x1 MSG_AB Debug messages A, B received. 0x2 MSG_ABC Debug messages A, B, C received, DMA request is set. 0x3 F1F Receive FIFO 1 Fill Level 24 1 read-only F1FL Receive FIFO 1 Fill Level 0 7 read-only F1GI Receive FIFO 1 Get Index 8 6 read-only F1PI Receive FIFO 1 Put Index 16 6 read-only RF1L Receive FIFO 1 Message Lost 25 1 read-only SIDFC Standard ID Filter Configuration Register 0x84 32 read-write n 0x0 FLSSA Filter List Standard Start Address 2 14 read-write LSS List Size Standard 16 8 read-write TEST Test Register 0x10 32 read-write n LBCK Loop Back Mode (read/write) 4 1 read-write DISABLED Reset value. Loop Back mode is disabled. 0 ENABLED Loop Back mode is enabled (see Section 1.5.1.9). 1 RX Receive Pin (read-only) 7 1 read-write TDCV Transceiver Delay Compensation Value (read-only) 8 6 read-write TX Control of Transmit Pin (read/write) 5 2 read-write RESET Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. 0x0 SAMPLE_POINT_MONITORING Sample Point can be monitored at pin CANTX. 0x1 DOMINANT Dominant ('0') level at pin CANTX. 0x2 RECESSIVE Recessive ('1') at pin CANTX. 0x3 TOCC Timeout Counter Configuration Register 0x28 32 read-write n 0x0 ETOC Enable Timeout Counter 0 1 read-write NO_TIMEOUT Timeout Counter disabled. 0 TOS_CONTROLLED Timeout Counter enabled. 1 TOP Timeout Period 16 16 read-write TOS Timeout Select 1 2 read-write CONTINUOUS Continuous operation 0x0 TX_EV_TIMEOUT Timeout controlled by Tx Event FIFO 0x1 RX0_EV_TIMEOUT Timeout controlled by Receive FIFO 0 0x2 RX1_EV_TIMEOUT Timeout controlled by Receive FIFO 1 0x3 TOCV Timeout Counter Value Register 0x2C 32 read-write n 0x0 TOC Timeout Counter (cleared on write) 0 16 read-write TSCC Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 TCP Timestamp Counter Prescaler 16 4 read-write TSS Timestamp Select 0 2 read-write ALWAYS_0 Timestamp counter value always 0x0000 0x0 TCP_INC Timestamp counter value incremented according to TCP 0x1 EXT_TIMESTAMP External timestamp counter value used 0x2 TSCV Timestamp Counter Value Register 0x24 32 read-write n 0x0 TSC Timestamp Counter (cleared on write) 0 16 read-write TXBAR Transmit Buffer Add Request Register 0xD0 32 read-write n 0x0 AR0 Add Request for Transmit Buffer 0 0 1 read-write AR1 Add Request for Transmit Buffer 1 1 1 read-write AR10 Add Request for Transmit Buffer 10 10 1 read-write AR11 Add Request for Transmit Buffer 11 11 1 read-write AR12 Add Request for Transmit Buffer 12 12 1 read-write AR13 Add Request for Transmit Buffer 13 13 1 read-write AR14 Add Request for Transmit Buffer 14 14 1 read-write AR15 Add Request for Transmit Buffer 15 15 1 read-write AR16 Add Request for Transmit Buffer 16 16 1 read-write AR17 Add Request for Transmit Buffer 17 17 1 read-write AR18 Add Request for Transmit Buffer 18 18 1 read-write AR19 Add Request for Transmit Buffer 19 19 1 read-write AR2 Add Request for Transmit Buffer 2 2 1 read-write AR20 Add Request for Transmit Buffer 20 20 1 read-write AR21 Add Request for Transmit Buffer 21 21 1 read-write AR22 Add Request for Transmit Buffer 22 22 1 read-write AR23 Add Request for Transmit Buffer 23 23 1 read-write AR24 Add Request for Transmit Buffer 24 24 1 read-write AR25 Add Request for Transmit Buffer 25 25 1 read-write AR26 Add Request for Transmit Buffer 26 26 1 read-write AR27 Add Request for Transmit Buffer 27 27 1 read-write AR28 Add Request for Transmit Buffer 28 28 1 read-write AR29 Add Request for Transmit Buffer 29 29 1 read-write AR3 Add Request for Transmit Buffer 3 3 1 read-write AR30 Add Request for Transmit Buffer 30 30 1 read-write AR31 Add Request for Transmit Buffer 31 31 1 read-write AR4 Add Request for Transmit Buffer 4 4 1 read-write AR5 Add Request for Transmit Buffer 5 5 1 read-write AR6 Add Request for Transmit Buffer 6 6 1 read-write AR7 Add Request for Transmit Buffer 7 7 1 read-write AR8 Add Request for Transmit Buffer 8 8 1 read-write AR9 Add Request for Transmit Buffer 9 9 1 read-write TXBC Transmit Buffer Configuration Register 0xC0 32 read-write n 0x0 NDTB Number of Dedicated Transmit Buffers 16 6 read-write TBSA Tx Buffers Start Address 2 14 read-write TFQM Tx FIFO/Queue Mode 30 1 read-write TFQS Transmit FIFO/Queue Size 24 6 read-write TXBCF Transmit Buffer Cancellation Finished Register 0xDC 32 read-only n 0x0 CF0 Cancellation Finished for Transmit Buffer 0 0 1 read-only CF1 Cancellation Finished for Transmit Buffer 1 1 1 read-only CF10 Cancellation Finished for Transmit Buffer 10 10 1 read-only CF11 Cancellation Finished for Transmit Buffer 11 11 1 read-only CF12 Cancellation Finished for Transmit Buffer 12 12 1 read-only CF13 Cancellation Finished for Transmit Buffer 13 13 1 read-only CF14 Cancellation Finished for Transmit Buffer 14 14 1 read-only CF15 Cancellation Finished for Transmit Buffer 15 15 1 read-only CF16 Cancellation Finished for Transmit Buffer 16 16 1 read-only CF17 Cancellation Finished for Transmit Buffer 17 17 1 read-only CF18 Cancellation Finished for Transmit Buffer 18 18 1 read-only CF19 Cancellation Finished for Transmit Buffer 19 19 1 read-only CF2 Cancellation Finished for Transmit Buffer 2 2 1 read-only CF20 Cancellation Finished for Transmit Buffer 20 20 1 read-only CF21 Cancellation Finished for Transmit Buffer 21 21 1 read-only CF22 Cancellation Finished for Transmit Buffer 22 22 1 read-only CF23 Cancellation Finished for Transmit Buffer 23 23 1 read-only CF24 Cancellation Finished for Transmit Buffer 24 24 1 read-only CF25 Cancellation Finished for Transmit Buffer 25 25 1 read-only CF26 Cancellation Finished for Transmit Buffer 26 26 1 read-only CF27 Cancellation Finished for Transmit Buffer 27 27 1 read-only CF28 Cancellation Finished for Transmit Buffer 28 28 1 read-only CF29 Cancellation Finished for Transmit Buffer 29 29 1 read-only CF3 Cancellation Finished for Transmit Buffer 3 3 1 read-only CF30 Cancellation Finished for Transmit Buffer 30 30 1 read-only CF31 Cancellation Finished for Transmit Buffer 31 31 1 read-only CF4 Cancellation Finished for Transmit Buffer 4 4 1 read-only CF5 Cancellation Finished for Transmit Buffer 5 5 1 read-only CF6 Cancellation Finished for Transmit Buffer 6 6 1 read-only CF7 Cancellation Finished for Transmit Buffer 7 7 1 read-only CF8 Cancellation Finished for Transmit Buffer 8 8 1 read-only CF9 Cancellation Finished for Transmit Buffer 9 9 1 read-only TXBCIE Transmit Buffer Cancellation Finished Interrupt Enable Register 0xE4 32 read-write n 0x0 CFIE0 Cancellation Finished Interrupt Enable for Transmit Buffer 0 0 1 read-write CFIE1 Cancellation Finished Interrupt Enable for Transmit Buffer 1 1 1 read-write CFIE10 Cancellation Finished Interrupt Enable for Transmit Buffer 10 10 1 read-write CFIE11 Cancellation Finished Interrupt Enable for Transmit Buffer 11 11 1 read-write CFIE12 Cancellation Finished Interrupt Enable for Transmit Buffer 12 12 1 read-write CFIE13 Cancellation Finished Interrupt Enable for Transmit Buffer 13 13 1 read-write CFIE14 Cancellation Finished Interrupt Enable for Transmit Buffer 14 14 1 read-write CFIE15 Cancellation Finished Interrupt Enable for Transmit Buffer 15 15 1 read-write CFIE16 Cancellation Finished Interrupt Enable for Transmit Buffer 16 16 1 read-write CFIE17 Cancellation Finished Interrupt Enable for Transmit Buffer 17 17 1 read-write CFIE18 Cancellation Finished Interrupt Enable for Transmit Buffer 18 18 1 read-write CFIE19 Cancellation Finished Interrupt Enable for Transmit Buffer 19 19 1 read-write CFIE2 Cancellation Finished Interrupt Enable for Transmit Buffer 2 2 1 read-write CFIE20 Cancellation Finished Interrupt Enable for Transmit Buffer 20 20 1 read-write CFIE21 Cancellation Finished Interrupt Enable for Transmit Buffer 21 21 1 read-write CFIE22 Cancellation Finished Interrupt Enable for Transmit Buffer 22 22 1 read-write CFIE23 Cancellation Finished Interrupt Enable for Transmit Buffer 23 23 1 read-write CFIE24 Cancellation Finished Interrupt Enable for Transmit Buffer 24 24 1 read-write CFIE25 Cancellation Finished Interrupt Enable for Transmit Buffer 25 25 1 read-write CFIE26 Cancellation Finished Interrupt Enable for Transmit Buffer 26 26 1 read-write CFIE27 Cancellation Finished Interrupt Enable for Transmit Buffer 27 27 1 read-write CFIE28 Cancellation Finished Interrupt Enable for Transmit Buffer 28 28 1 read-write CFIE29 Cancellation Finished Interrupt Enable for Transmit Buffer 29 29 1 read-write CFIE3 Cancellation Finished Interrupt Enable for Transmit Buffer 3 3 1 read-write CFIE30 Cancellation Finished Interrupt Enable for Transmit Buffer 30 30 1 read-write CFIE31 Cancellation Finished Interrupt Enable for Transmit Buffer 31 31 1 read-write CFIE4 Cancellation Finished Interrupt Enable for Transmit Buffer 4 4 1 read-write CFIE5 Cancellation Finished Interrupt Enable for Transmit Buffer 5 5 1 read-write CFIE6 Cancellation Finished Interrupt Enable for Transmit Buffer 6 6 1 read-write CFIE7 Cancellation Finished Interrupt Enable for Transmit Buffer 7 7 1 read-write CFIE8 Cancellation Finished Interrupt Enable for Transmit Buffer 8 8 1 read-write CFIE9 Cancellation Finished Interrupt Enable for Transmit Buffer 9 9 1 read-write TXBCR Transmit Buffer Cancellation Request Register 0xD4 32 read-write n 0x0 CR0 Cancellation Request for Transmit Buffer 0 0 1 read-write CR1 Cancellation Request for Transmit Buffer 1 1 1 read-write CR10 Cancellation Request for Transmit Buffer 10 10 1 read-write CR11 Cancellation Request for Transmit Buffer 11 11 1 read-write CR12 Cancellation Request for Transmit Buffer 12 12 1 read-write CR13 Cancellation Request for Transmit Buffer 13 13 1 read-write CR14 Cancellation Request for Transmit Buffer 14 14 1 read-write CR15 Cancellation Request for Transmit Buffer 15 15 1 read-write CR16 Cancellation Request for Transmit Buffer 16 16 1 read-write CR17 Cancellation Request for Transmit Buffer 17 17 1 read-write CR18 Cancellation Request for Transmit Buffer 18 18 1 read-write CR19 Cancellation Request for Transmit Buffer 19 19 1 read-write CR2 Cancellation Request for Transmit Buffer 2 2 1 read-write CR20 Cancellation Request for Transmit Buffer 20 20 1 read-write CR21 Cancellation Request for Transmit Buffer 21 21 1 read-write CR22 Cancellation Request for Transmit Buffer 22 22 1 read-write CR23 Cancellation Request for Transmit Buffer 23 23 1 read-write CR24 Cancellation Request for Transmit Buffer 24 24 1 read-write CR25 Cancellation Request for Transmit Buffer 25 25 1 read-write CR26 Cancellation Request for Transmit Buffer 26 26 1 read-write CR27 Cancellation Request for Transmit Buffer 27 27 1 read-write CR28 Cancellation Request for Transmit Buffer 28 28 1 read-write CR29 Cancellation Request for Transmit Buffer 29 29 1 read-write CR3 Cancellation Request for Transmit Buffer 3 3 1 read-write CR30 Cancellation Request for Transmit Buffer 30 30 1 read-write CR31 Cancellation Request for Transmit Buffer 31 31 1 read-write CR4 Cancellation Request for Transmit Buffer 4 4 1 read-write CR5 Cancellation Request for Transmit Buffer 5 5 1 read-write CR6 Cancellation Request for Transmit Buffer 6 6 1 read-write CR7 Cancellation Request for Transmit Buffer 7 7 1 read-write CR8 Cancellation Request for Transmit Buffer 8 8 1 read-write CR9 Cancellation Request for Transmit Buffer 9 9 1 read-write TXBRP Transmit Buffer Request Pending Register 0xCC 32 read-only n 0x0 TRP0 Transmission Request Pending for Buffer 0 0 1 read-only TRP1 Transmission Request Pending for Buffer 1 1 1 read-only TRP10 Transmission Request Pending for Buffer 10 10 1 read-only TRP11 Transmission Request Pending for Buffer 11 11 1 read-only TRP12 Transmission Request Pending for Buffer 12 12 1 read-only TRP13 Transmission Request Pending for Buffer 13 13 1 read-only TRP14 Transmission Request Pending for Buffer 14 14 1 read-only TRP15 Transmission Request Pending for Buffer 15 15 1 read-only TRP16 Transmission Request Pending for Buffer 16 16 1 read-only TRP17 Transmission Request Pending for Buffer 17 17 1 read-only TRP18 Transmission Request Pending for Buffer 18 18 1 read-only TRP19 Transmission Request Pending for Buffer 19 19 1 read-only TRP2 Transmission Request Pending for Buffer 2 2 1 read-only TRP20 Transmission Request Pending for Buffer 20 20 1 read-only TRP21 Transmission Request Pending for Buffer 21 21 1 read-only TRP22 Transmission Request Pending for Buffer 22 22 1 read-only TRP23 Transmission Request Pending for Buffer 23 23 1 read-only TRP24 Transmission Request Pending for Buffer 24 24 1 read-only TRP25 Transmission Request Pending for Buffer 25 25 1 read-only TRP26 Transmission Request Pending for Buffer 26 26 1 read-only TRP27 Transmission Request Pending for Buffer 27 27 1 read-only TRP28 Transmission Request Pending for Buffer 28 28 1 read-only TRP29 Transmission Request Pending for Buffer 29 29 1 read-only TRP3 Transmission Request Pending for Buffer 3 3 1 read-only TRP30 Transmission Request Pending for Buffer 30 30 1 read-only TRP31 Transmission Request Pending for Buffer 31 31 1 read-only TRP4 Transmission Request Pending for Buffer 4 4 1 read-only TRP5 Transmission Request Pending for Buffer 5 5 1 read-only TRP6 Transmission Request Pending for Buffer 6 6 1 read-only TRP7 Transmission Request Pending for Buffer 7 7 1 read-only TRP8 Transmission Request Pending for Buffer 8 8 1 read-only TRP9 Transmission Request Pending for Buffer 9 9 1 read-only TXBTIE Transmit Buffer Transmission Interrupt Enable Register 0xE0 32 read-write n 0x0 TIE0 Transmission Interrupt Enable for Buffer 0 0 1 read-write TIE1 Transmission Interrupt Enable for Buffer 1 1 1 read-write TIE10 Transmission Interrupt Enable for Buffer 10 10 1 read-write TIE11 Transmission Interrupt Enable for Buffer 11 11 1 read-write TIE12 Transmission Interrupt Enable for Buffer 12 12 1 read-write TIE13 Transmission Interrupt Enable for Buffer 13 13 1 read-write TIE14 Transmission Interrupt Enable for Buffer 14 14 1 read-write TIE15 Transmission Interrupt Enable for Buffer 15 15 1 read-write TIE16 Transmission Interrupt Enable for Buffer 16 16 1 read-write TIE17 Transmission Interrupt Enable for Buffer 17 17 1 read-write TIE18 Transmission Interrupt Enable for Buffer 18 18 1 read-write TIE19 Transmission Interrupt Enable for Buffer 19 19 1 read-write TIE2 Transmission Interrupt Enable for Buffer 2 2 1 read-write TIE20 Transmission Interrupt Enable for Buffer 20 20 1 read-write TIE21 Transmission Interrupt Enable for Buffer 21 21 1 read-write TIE22 Transmission Interrupt Enable for Buffer 22 22 1 read-write TIE23 Transmission Interrupt Enable for Buffer 23 23 1 read-write TIE24 Transmission Interrupt Enable for Buffer 24 24 1 read-write TIE25 Transmission Interrupt Enable for Buffer 25 25 1 read-write TIE26 Transmission Interrupt Enable for Buffer 26 26 1 read-write TIE27 Transmission Interrupt Enable for Buffer 27 27 1 read-write TIE28 Transmission Interrupt Enable for Buffer 28 28 1 read-write TIE29 Transmission Interrupt Enable for Buffer 29 29 1 read-write TIE3 Transmission Interrupt Enable for Buffer 3 3 1 read-write TIE30 Transmission Interrupt Enable for Buffer 30 30 1 read-write TIE31 Transmission Interrupt Enable for Buffer 31 31 1 read-write TIE4 Transmission Interrupt Enable for Buffer 4 4 1 read-write TIE5 Transmission Interrupt Enable for Buffer 5 5 1 read-write TIE6 Transmission Interrupt Enable for Buffer 6 6 1 read-write TIE7 Transmission Interrupt Enable for Buffer 7 7 1 read-write TIE8 Transmission Interrupt Enable for Buffer 8 8 1 read-write TIE9 Transmission Interrupt Enable for Buffer 9 9 1 read-write TXBTO Transmit Buffer Transmission Occurred Register 0xD8 32 read-only n 0x0 TO0 Transmission Occurred for Buffer 0 0 1 read-only TO1 Transmission Occurred for Buffer 1 1 1 read-only TO10 Transmission Occurred for Buffer 10 10 1 read-only TO11 Transmission Occurred for Buffer 11 11 1 read-only TO12 Transmission Occurred for Buffer 12 12 1 read-only TO13 Transmission Occurred for Buffer 13 13 1 read-only TO14 Transmission Occurred for Buffer 14 14 1 read-only TO15 Transmission Occurred for Buffer 15 15 1 read-only TO16 Transmission Occurred for Buffer 16 16 1 read-only TO17 Transmission Occurred for Buffer 17 17 1 read-only TO18 Transmission Occurred for Buffer 18 18 1 read-only TO19 Transmission Occurred for Buffer 19 19 1 read-only TO2 Transmission Occurred for Buffer 2 2 1 read-only TO20 Transmission Occurred for Buffer 20 20 1 read-only TO21 Transmission Occurred for Buffer 21 21 1 read-only TO22 Transmission Occurred for Buffer 22 22 1 read-only TO23 Transmission Occurred for Buffer 23 23 1 read-only TO24 Transmission Occurred for Buffer 24 24 1 read-only TO25 Transmission Occurred for Buffer 25 25 1 read-only TO26 Transmission Occurred for Buffer 26 26 1 read-only TO27 Transmission Occurred for Buffer 27 27 1 read-only TO28 Transmission Occurred for Buffer 28 28 1 read-only TO29 Transmission Occurred for Buffer 29 29 1 read-only TO3 Transmission Occurred for Buffer 3 3 1 read-only TO30 Transmission Occurred for Buffer 30 30 1 read-only TO31 Transmission Occurred for Buffer 31 31 1 read-only TO4 Transmission Occurred for Buffer 4 4 1 read-only TO5 Transmission Occurred for Buffer 5 5 1 read-only TO6 Transmission Occurred for Buffer 6 6 1 read-only TO7 Transmission Occurred for Buffer 7 7 1 read-only TO8 Transmission Occurred for Buffer 8 8 1 read-only TO9 Transmission Occurred for Buffer 9 9 1 read-only TXEFA Transmit Event FIFO Acknowledge Register 0xF8 32 read-write n 0x0 EFAI Event FIFO Acknowledge Index 0 5 read-write TXEFC Transmit Event FIFO Configuration Register 0xF0 32 read-write n 0x0 EFS Event FIFO Size 16 6 read-write EFSA Event FIFO Start Address 2 14 read-write EFWM Event FIFO Watermark 24 6 read-write TXEFS Transmit Event FIFO Status Register 0xF4 32 read-only n 0x0 EFF Event FIFO Full 24 1 read-only EFFL Event FIFO Fill Level 0 6 read-only EFGI Event FIFO Get Index 8 5 read-only EFPI Event FIFO Put Index 16 5 read-only TEFL Tx Event FIFO Element Lost 25 1 read-only TXESC Transmit Buffer Element Size Configuration Register 0xC8 32 read-write n 0x0 TBDS Tx Buffer Data Field Size 0 3 read-write 8_BYTE 8-byte data field 0x0 12_BYTE 12-byte data field 0x1 16_BYTE 16-byte data field 0x2 20_BYTE 20-byte data field 0x3 24_BYTE 24-byte data field 0x4 32_BYTE 32-byte data field 0x5 48_BYTE 4- byte data field 0x6 64_BYTE 64-byte data field 0x7 TXFQS Transmit FIFO/Queue Status Register 0xC4 32 read-only n 0x0 TFFL Tx FIFO Free Level 0 6 read-only TFGI Tx FIFO Get Index 8 5 read-only TFQF Tx FIFO/Queue Full 21 1 read-only TFQPI Tx FIFO/Queue Put Index 16 5 read-only XIDAM Extended ID AND Mask Register 0x90 32 read-write n 0x0 EIDM Extended ID Mask 0 29 read-write XIDFC Extended ID Filter Configuration Register 0x88 32 read-write n 0x0 FLESA Filter List Extended Start Address 2 14 read-write LSE List Size Extended 16 7 read-write MCAN1 Controller Area Network 1 MCAN 0x0 0x0 0xFC registers n MCAN1_INT0 37 MCAN1 37 MCAN1_INT1 38 BTP Bit Timing and Prescaler Register 0x1C 32 read-write n 0x0 BRP Baud Rate Prescaler 16 10 read-write SJW (Re) Synchronization Jump Width 0 4 read-write TSEG1 Time Segment Before Sample Point 8 6 read-write TSEG2 Time Segment After Sample Point 4 4 read-write CCCR CC Control Register 0x18 32 read-write n 0x0 ASM Restricted Operation Mode (read/write, write protection against '1') 2 1 read-write NORMAL Normal CAN operation. 0 RESTRICTED Restricted operation mode active. 1 CCE Configuration Change Enable (read/write, write protection) 1 1 read-write PROTECTED The processor has no write access to the protected configuration registers. 0 CONFIGURABLE The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). 1 CME CAN Mode Enable (read/write, write protection) 8 2 read-write ISO11898_1 CAN operation according to ISO11898-1 enabled 0 FD CAN FD operation enabled 1 CMR CAN Mode Request (read/write) 10 2 read-write NO_CHANGE No mode change 0x0 FD Request CAN FD operation 0x1 FD_BITRATE_SWITCH Request CAN FD operation with bit rate switching 0x2 ISO11898_1 Request CAN operation according ISO11898-1 0x3 CSA Clock Stop Acknowledge (read-only) 3 1 read-write CSR Clock Stop Request (read/write) 4 1 read-write NO_CLOCK_STOP No clock stop is requested. 0 CLOCK_STOP Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. 1 DAR Disable Automatic Retransmission (read/write, write protection) 6 1 read-write AUTO_RETX Automatic retransmission of messages not transmitted successfully enabled. 0 NO_AUTO_RETX Automatic retransmission disabled. 1 FDBS CAN FD Bit Rate Switching (read-only) 13 1 read-write FDO CAN FD Operation (read-only) 12 1 read-write INIT Initialization (read/write) 0 1 read-write DISABLED Normal operation. 0 ENABLED Initialization is started. 1 MON Bus Monitoring Mode (read/write, write protection against '1') 5 1 read-write DISABLED Bus Monitoring mode is disabled. 0 ENABLED Bus Monitoring mode is enabled. 1 TEST Test Mode Enable (read/write, write protection against '1') 7 1 read-write DISABLED Normal operation, MCAN_TEST register holds reset values. 0 ENABLED Test mode, write access to MCAN_TEST register enabled. 1 TXP Transmit Pause (read/write, write protection) 14 1 read-write CUST Customer Register 0x8 32 read-write n 0x0 CSV Customer-specific Value 0 32 read-write ECR Error Counter Register 0x40 32 read-only n 0x0 CEL CAN Error Logging (cleared on read) 16 8 read-only REC Receive Error Counter 8 7 read-only RP Receive Error Passive 15 1 read-only TEC Transmit Error Counter 0 8 read-only FBTP Fast Bit Timing and Prescaler Register 0xC 32 read-write n 0x0 FBRP Fast Baud Rate Prescaler 16 5 read-write FSJW Fast (Re) Synchronization Jump Width 0 2 read-write FTSEG1 Fast Time Segment Before Sample Point 8 4 read-write FTSEG2 Fast Time Segment After Sample Point 4 3 read-write TDC Transceiver Delay Compensation 23 1 read-write DISABLED Transceiver Delay Compensation disabled. 0 ENABLED Transceiver Delay Compensation enabled. 1 TDCO Transceiver Delay Compensation Offset 24 5 read-write GFC Global Filter Configuration Register 0x80 32 read-write n 0x0 ANFE Accept Non-matching Frames Extended 2 2 read-write RX_FIFO_0 Message stored in Receive FIFO 0 0 RX_FIFO_1 Message stored in Receive FIFO 1 1 ANFS Accept Non-matching Frames Standard 4 2 read-write RX_FIFO_0 Message stored in Receive FIFO 0 0 RX_FIFO_1 Message stored in Receive FIFO 1 1 RRFE Reject Remote Frames Extended 0 1 read-write FILTER Filter remote frames with 29-bit extended IDs. 0 REJECT Reject all remote frames with 29-bit extended IDs. 1 RRFS Reject Remote Frames Standard 1 1 read-write FILTER Filter remote frames with 11-bit standard IDs. 0 REJECT Reject all remote frames with 11-bit standard IDs. 1 HPMS High Priority Message Status Register 0x94 32 read-only n 0x0 BIDX Buffer Index 0 6 read-only FIDX Filter Index 8 7 read-only FLST Filter List 15 1 read-only MSI Message Storage Indicator 6 2 read-only NO_FIFO_SEL No FIFO selected. 0x0 LOST FIFO message. 0x1 FIFO_0 Message stored in FIFO 0. 0x2 FIFO_1 Message stored in FIFO 1. 0x3 IE Interrupt Enable Register 0x54 32 read-write n 0x0 ACKEE Acknowledge Error Interrupt Enable 29 1 read-write BEE Bit Error Interrupt Enable 28 1 read-write BOE Bus_Off Status Interrupt Enable 25 1 read-write CRCEE CRC Error Interrupt Enable 27 1 read-write DRXE Message stored to Dedicated Receive Buffer Interrupt Enable 19 1 read-write ELOE Error Logging Overflow Interrupt Enable 22 1 read-write EPE Error Passive Interrupt Enable 23 1 read-write EWE Warning Status Interrupt Enable 24 1 read-write FOEE Format Error Interrupt Enable 30 1 read-write HPME High Priority Message Interrupt Enable 8 1 read-write MRAFE Message RAM Access Failure Interrupt Enable 17 1 read-write RF0FE Receive FIFO 0 Full Interrupt Enable 2 1 read-write RF0LE Receive FIFO 0 Message Lost Interrupt Enable 3 1 read-write RF0NE Receive FIFO 0 New Message Interrupt Enable 0 1 read-write RF0WE Receive FIFO 0 Watermark Reached Interrupt Enable 1 1 read-write RF1FE Receive FIFO 1 Full Interrupt Enable 6 1 read-write RF1LE Receive FIFO 1 Message Lost Interrupt Enable 7 1 read-write RF1NE Receive FIFO 1 New Message Interrupt Enable 4 1 read-write RF1WE Receive FIFO 1 Watermark Reached Interrupt Enable 5 1 read-write STEE Stuff Error Interrupt Enable 31 1 read-write TCE Transmission Completed Interrupt Enable 9 1 read-write TCFE Transmission Cancellation Finished Interrupt Enable 10 1 read-write TEFFE Tx Event FIFO Full Interrupt Enable 14 1 read-write TEFLE Tx Event FIFO Event Lost Interrupt Enable 15 1 read-write TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 read-write TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 read-write TFEE Tx FIFO Empty Interrupt Enable 11 1 read-write TOOE Timeout Occurred Interrupt Enable 18 1 read-write TSWE Timestamp Wraparound Interrupt Enable 16 1 read-write WDIE Watchdog Interrupt Enable 26 1 read-write ILE Interrupt Line Enable Register 0x5C 32 read-write n 0x0 EINT0 Enable Interrupt Line 0 0 1 read-write EINT1 Enable Interrupt Line 1 1 1 read-write ILS Interrupt Line Select Register 0x58 32 read-write n 0x0 ACKEL Acknowledge Error Interrupt Line 29 1 read-write BEL Bit Error Interrupt Line 28 1 read-write BOL Bus_Off Status Interrupt Line 25 1 read-write CRCEL CRC Error Interrupt Line 27 1 read-write DRXL Message stored to Dedicated Receive Buffer Interrupt Line 19 1 read-write ELOL Error Logging Overflow Interrupt Line 22 1 read-write EPL Error Passive Interrupt Line 23 1 read-write EWL Warning Status Interrupt Line 24 1 read-write FOEL Format Error Interrupt Line 30 1 read-write HPML High Priority Message Interrupt Line 8 1 read-write MRAFL Message RAM Access Failure Interrupt Line 17 1 read-write RF0FL Receive FIFO 0 Full Interrupt Line 2 1 read-write RF0LL Receive FIFO 0 Message Lost Interrupt Line 3 1 read-write RF0NL Receive FIFO 0 New Message Interrupt Line 0 1 read-write RF0WL Receive FIFO 0 Watermark Reached Interrupt Line 1 1 read-write RF1FL Receive FIFO 1 Full Interrupt Line 6 1 read-write RF1LL Receive FIFO 1 Message Lost Interrupt Line 7 1 read-write RF1NL Receive FIFO 1 New Message Interrupt Line 4 1 read-write RF1WL Receive FIFO 1 Watermark Reached Interrupt Line 5 1 read-write STEL Stuff Error Interrupt Line 31 1 read-write TCFL Transmission Cancellation Finished Interrupt Line 10 1 read-write TCL Transmission Completed Interrupt Line 9 1 read-write TEFFL Tx Event FIFO Full Interrupt Line 14 1 read-write TEFLL Tx Event FIFO Event Lost Interrupt Line 15 1 read-write TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 read-write TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 read-write TFEL Tx FIFO Empty Interrupt Line 11 1 read-write TOOL Timeout Occurred Interrupt Line 18 1 read-write TSWL Timestamp Wraparound Interrupt Line 16 1 read-write WDIL Watchdog Interrupt Line 26 1 read-write IR Interrupt Register 0x50 32 read-write n 0x0 ACKE Acknowledge Error 29 1 read-write BE Bit Error 28 1 read-write BO Bus_Off Status 25 1 read-write CRCE CRC Error 27 1 read-write DRX Message stored to Dedicated Receive Buffer 19 1 read-write ELO Error Logging Overflow 22 1 read-write EP Error Passive 23 1 read-write EW Warning Status 24 1 read-write FOE Format Error 30 1 read-write HPM High Priority Message 8 1 read-write MRAF Message RAM Access Failure 17 1 read-write RF0F Receive FIFO 0 Full 2 1 read-write RF0L Receive FIFO 0 Message Lost 3 1 read-write RF0N Receive FIFO 0 New Message 0 1 read-write RF0W Receive FIFO 0 Watermark Reached 1 1 read-write RF1F Receive FIFO 1 Full 6 1 read-write RF1L Receive FIFO 1 Message Lost 7 1 read-write RF1N Receive FIFO 1 New Message 4 1 read-write RF1W Receive FIFO 1 Watermark Reached 5 1 read-write STE Stuff Error 31 1 read-write TC Transmission Completed 9 1 read-write TCF Transmission Cancellation Finished 10 1 read-write TEFF Tx Event FIFO Full 14 1 read-write TEFL Tx Event FIFO Element Lost 15 1 read-write TEFN Tx Event FIFO New Entry 12 1 read-write TEFW Tx Event FIFO Watermark Reached 13 1 read-write TFE Tx FIFO Empty 11 1 read-write TOO Timeout Occurred 18 1 read-write TSW Timestamp Wraparound 16 1 read-write WDI Watchdog Interrupt 26 1 read-write MCAN_MCAN_BTP Bit Timing and Prescaler Register 0x1C 32 read-write n 0x0 0x0 BRP Baud Rate Prescaler 16 10 SJW (Re) Synchronization Jump Width 0 4 TSEG1 Time Segment Before Sample Point 8 6 TSEG2 Time Segment After Sample Point 4 4 MCAN_MCAN_CCCR CC Control Register 0x18 32 read-write n 0x0 0x0 ASM Restricted Operation Mode (read/write, write protection against '1') 2 1 ASMSelect NORMAL Normal CAN operation. 0 RESTRICTED Restricted operation mode active. 1 CCE Configuration Change Enable (read/write, write protection) 1 1 CCESelect PROTECTED The processor has no write access to the protected configuration registers. 0 CONFIGURABLE The processor has write access to the protected configuration registers (while MCAN_CCCR.INIT = '1'). 1 CME CAN Mode Enable (read/write, write protection) 8 2 CMESelect ISO11898_1 CAN operation according to ISO11898-1 enabled 0 FD CAN FD operation enabled 1 CMR CAN Mode Request (read/write) 10 2 CMRSelect NO_CHANGE No mode change 0 FD Request CAN FD operation 1 FD_BITRATE_SWITCH Request CAN FD operation with bit rate switching 2 ISO11898_1 Request CAN operation according ISO11898-1 3 CSA Clock Stop Acknowledge (read-only) 3 1 CSR Clock Stop Request (read/write) 4 1 CSRSelect NO_CLOCK_STOP No clock stop is requested. 0 CLOCK_STOP Clock stop requested. When clock stop is requested, first INIT and then CSA will be set after all pend-ing transfer requests have been completed and the CAN bus reached idle. 1 DAR Disable Automatic Retransmission (read/write, write protection) 6 1 DARSelect AUTO_RETX Automatic retransmission of messages not transmitted successfully enabled. 0 NO_AUTO_RETX Automatic retransmission disabled. 1 FDBS CAN FD Bit Rate Switching (read-only) 13 1 FDO CAN FD Operation (read-only) 12 1 INIT Initialization (read/write) 0 1 INITSelect DISABLED Normal operation. 0 ENABLED Initialization is started. 1 MON Bus Monitoring Mode (read/write, write protection against '1') 5 1 MONSelect DISABLED Bus Monitoring mode is disabled. 0 ENABLED Bus Monitoring mode is enabled. 1 TEST Test Mode Enable (read/write, write protection against '1') 7 1 TESTSelect DISABLED Normal operation, MCAN_TEST register holds reset values. 0 ENABLED Test mode, write access to MCAN_TEST register enabled. 1 TXP Transmit Pause (read/write, write protection) 14 1 MCAN_MCAN_CUST Customer Register 0x8 32 read-write n 0x0 0x0 CSV Customer-specific Value 0 32 MCAN_MCAN_ECR Error Counter Register 0x40 32 read-only n 0x0 0x0 CEL CAN Error Logging (cleared on read) 16 8 REC Receive Error Counter 8 7 RP Receive Error Passive 15 1 TEC Transmit Error Counter 0 8 MCAN_MCAN_FBTP Fast Bit Timing and Prescaler Register 0xC 32 read-write n 0x0 0x0 FBRP Fast Baud Rate Prescaler 16 5 FSJW Fast (Re) Synchronization Jump Width 0 2 FTSEG1 Fast Time Segment Before Sample Point 8 4 FTSEG2 Fast Time Segment After Sample Point 4 3 TDC Transceiver Delay Compensation 23 1 TDCSelect DISABLED Transceiver Delay Compensation disabled. 0 ENABLED Transceiver Delay Compensation enabled. 1 TDCO Transceiver Delay Compensation Offset 24 5 MCAN_MCAN_GFC Global Filter Configuration Register 0x80 32 read-write n 0x0 0x0 ANFE Accept Non-matching Frames Extended 2 2 ANFESelect RX_FIFO_0 Message stored in Receive FIFO 0 0 RX_FIFO_1 Message stored in Receive FIFO 1 1 ANFS Accept Non-matching Frames Standard 4 2 ANFSSelect RX_FIFO_0 Message stored in Receive FIFO 0 0 RX_FIFO_1 Message stored in Receive FIFO 1 1 RRFE Reject Remote Frames Extended 0 1 RRFESelect FILTER Filter remote frames with 29-bit extended IDs. 0 REJECT Reject all remote frames with 29-bit extended IDs. 1 RRFS Reject Remote Frames Standard 1 1 RRFSSelect FILTER Filter remote frames with 11-bit standard IDs. 0 REJECT Reject all remote frames with 11-bit standard IDs. 1 MCAN_MCAN_HPMS High Priority Message Status Register 0x94 32 read-only n 0x0 0x0 BIDX Buffer Index 0 6 FIDX Filter Index 8 7 FLST Filter List 15 1 MSI Message Storage Indicator 6 2 MSISelect NO_FIFO_SEL No FIFO selected. 0 LOST FIFO message. 1 FIFO_0 Message stored in FIFO 0. 2 FIFO_1 Message stored in FIFO 1. 3 MCAN_MCAN_IE Interrupt Enable Register 0x54 32 read-write n 0x0 0x0 ACKEE Acknowledge Error Interrupt Enable 29 1 BEE Bit Error Interrupt Enable 28 1 BOE Bus_Off Status Interrupt Enable 25 1 CRCEE CRC Error Interrupt Enable 27 1 DRXE Message stored to Dedicated Receive Buffer Interrupt Enable 19 1 ELOE Error Logging Overflow Interrupt Enable 22 1 EPE Error Passive Interrupt Enable 23 1 EWE Warning Status Interrupt Enable 24 1 FOEE Format Error Interrupt Enable 30 1 HPME High Priority Message Interrupt Enable 8 1 MRAFE Message RAM Access Failure Interrupt Enable 17 1 RF0FE Receive FIFO 0 Full Interrupt Enable 2 1 RF0LE Receive FIFO 0 Message Lost Interrupt Enable 3 1 RF0NE Receive FIFO 0 New Message Interrupt Enable 0 1 RF0WE Receive FIFO 0 Watermark Reached Interrupt Enable 1 1 RF1FE Receive FIFO 1 Full Interrupt Enable 6 1 RF1LE Receive FIFO 1 Message Lost Interrupt Enable 7 1 RF1NE Receive FIFO 1 New Message Interrupt Enable 4 1 RF1WE Receive FIFO 1 Watermark Reached Interrupt Enable 5 1 STEE Stuff Error Interrupt Enable 31 1 TCE Transmission Completed Interrupt Enable 9 1 TCFE Transmission Cancellation Finished Interrupt Enable 10 1 TEFFE Tx Event FIFO Full Interrupt Enable 14 1 TEFLE Tx Event FIFO Event Lost Interrupt Enable 15 1 TEFNE Tx Event FIFO New Entry Interrupt Enable 12 1 TEFWE Tx Event FIFO Watermark Reached Interrupt Enable 13 1 TFEE Tx FIFO Empty Interrupt Enable 11 1 TOOE Timeout Occurred Interrupt Enable 18 1 TSWE Timestamp Wraparound Interrupt Enable 16 1 WDIE Watchdog Interrupt Enable 26 1 MCAN_MCAN_ILE Interrupt Line Enable Register 0x5C 32 read-write n 0x0 0x0 EINT0 Enable Interrupt Line 0 0 1 EINT1 Enable Interrupt Line 1 1 1 MCAN_MCAN_ILS Interrupt Line Select Register 0x58 32 read-write n 0x0 0x0 ACKEL Acknowledge Error Interrupt Line 29 1 BEL Bit Error Interrupt Line 28 1 BOL Bus_Off Status Interrupt Line 25 1 CRCEL CRC Error Interrupt Line 27 1 DRXL Message stored to Dedicated Receive Buffer Interrupt Line 19 1 ELOL Error Logging Overflow Interrupt Line 22 1 EPL Error Passive Interrupt Line 23 1 EWL Warning Status Interrupt Line 24 1 FOEL Format Error Interrupt Line 30 1 HPML High Priority Message Interrupt Line 8 1 MRAFL Message RAM Access Failure Interrupt Line 17 1 RF0FL Receive FIFO 0 Full Interrupt Line 2 1 RF0LL Receive FIFO 0 Message Lost Interrupt Line 3 1 RF0NL Receive FIFO 0 New Message Interrupt Line 0 1 RF0WL Receive FIFO 0 Watermark Reached Interrupt Line 1 1 RF1FL Receive FIFO 1 Full Interrupt Line 6 1 RF1LL Receive FIFO 1 Message Lost Interrupt Line 7 1 RF1NL Receive FIFO 1 New Message Interrupt Line 4 1 RF1WL Receive FIFO 1 Watermark Reached Interrupt Line 5 1 STEL Stuff Error Interrupt Line 31 1 TCFL Transmission Cancellation Finished Interrupt Line 10 1 TCL Transmission Completed Interrupt Line 9 1 TEFFL Tx Event FIFO Full Interrupt Line 14 1 TEFLL Tx Event FIFO Event Lost Interrupt Line 15 1 TEFNL Tx Event FIFO New Entry Interrupt Line 12 1 TEFWL Tx Event FIFO Watermark Reached Interrupt Line 13 1 TFEL Tx FIFO Empty Interrupt Line 11 1 TOOL Timeout Occurred Interrupt Line 18 1 TSWL Timestamp Wraparound Interrupt Line 16 1 WDIL Watchdog Interrupt Line 26 1 MCAN_MCAN_IR Interrupt Register 0x50 32 read-write n 0x0 0x0 ACKE Acknowledge Error 29 1 BE Bit Error 28 1 BO Bus_Off Status 25 1 CRCE CRC Error 27 1 DRX Message stored to Dedicated Receive Buffer 19 1 ELO Error Logging Overflow 22 1 EP Error Passive 23 1 EW Warning Status 24 1 FOE Format Error 30 1 HPM High Priority Message 8 1 MRAF Message RAM Access Failure 17 1 RF0F Receive FIFO 0 Full 2 1 RF0L Receive FIFO 0 Message Lost 3 1 RF0N Receive FIFO 0 New Message 0 1 RF0W Receive FIFO 0 Watermark Reached 1 1 RF1F Receive FIFO 1 Full 6 1 RF1L Receive FIFO 1 Message Lost 7 1 RF1N Receive FIFO 1 New Message 4 1 RF1W Receive FIFO 1 Watermark Reached 5 1 STE Stuff Error 31 1 TC Transmission Completed 9 1 TCF Transmission Cancellation Finished 10 1 TEFF Tx Event FIFO Full 14 1 TEFL Tx Event FIFO Element Lost 15 1 TEFN Tx Event FIFO New Entry 12 1 TEFW Tx Event FIFO Watermark Reached 13 1 TFE Tx FIFO Empty 11 1 TOO Timeout Occurred 18 1 TSW Timestamp Wraparound 16 1 WDI Watchdog Interrupt 26 1 MCAN_MCAN_NDAT1 New Data 1 Register 0x98 32 read-write n 0x0 0x0 ND0 New Data 0 1 ND1 New Data 1 1 ND10 New Data 10 1 ND11 New Data 11 1 ND12 New Data 12 1 ND13 New Data 13 1 ND14 New Data 14 1 ND15 New Data 15 1 ND16 New Data 16 1 ND17 New Data 17 1 ND18 New Data 18 1 ND19 New Data 19 1 ND2 New Data 2 1 ND20 New Data 20 1 ND21 New Data 21 1 ND22 New Data 22 1 ND23 New Data 23 1 ND24 New Data 24 1 ND25 New Data 25 1 ND26 New Data 26 1 ND27 New Data 27 1 ND28 New Data 28 1 ND29 New Data 29 1 ND3 New Data 3 1 ND30 New Data 30 1 ND31 New Data 31 1 ND4 New Data 4 1 ND5 New Data 5 1 ND6 New Data 6 1 ND7 New Data 7 1 ND8 New Data 8 1 ND9 New Data 9 1 MCAN_MCAN_NDAT2 New Data 2 Register 0x9C 32 read-write n 0x0 0x0 ND32 New Data 0 1 ND33 New Data 1 1 ND34 New Data 2 1 ND35 New Data 3 1 ND36 New Data 4 1 ND37 New Data 5 1 ND38 New Data 6 1 ND39 New Data 7 1 ND40 New Data 8 1 ND41 New Data 9 1 ND42 New Data 10 1 ND43 New Data 11 1 ND44 New Data 12 1 ND45 New Data 13 1 ND46 New Data 14 1 ND47 New Data 15 1 ND48 New Data 16 1 ND49 New Data 17 1 ND50 New Data 18 1 ND51 New Data 19 1 ND52 New Data 20 1 ND53 New Data 21 1 ND54 New Data 22 1 ND55 New Data 23 1 ND56 New Data 24 1 ND57 New Data 25 1 ND58 New Data 26 1 ND59 New Data 27 1 ND60 New Data 28 1 ND61 New Data 29 1 ND62 New Data 30 1 ND63 New Data 31 1 MCAN_MCAN_PSR Protocol Status Register 0x44 32 read-only n 0x0 0x0 ACT Activity 3 2 ACTSelect SYNCHRONIZING Node is synchronizing on CAN communication 0 IDLE Node is neither receiver nor transmitter 1 RECEIVER Node is operating as receiver 2 TRANSMITTER Node is operating as transmitter 3 BO Bus_Off Status 7 1 EP Error Passive 5 1 EW Warning Status 6 1 FLEC Fast Last Error Code (set to 111 on read) 8 3 LEC Last Error Code (set to 111 on read) 0 3 LECSelect NO_ERROR No error occurred since LEC has been reset by successful reception or transmission. 0 STUFF_ERROR More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 1 FORM_ERROR A fixed format part of a received frame has the wrong format. 2 ACK_ERROR The message transmitted by the MCAN was not acknowledged by another node. 3 BIT1_ERROR During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 4 BIT0_ERROR During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 5 CRC_ERROR The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 6 NO_CHANGE Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. 7 RBRS BRS Flag of Last Received CAN FD Message (cleared on read) 12 1 REDL Received a CAN FD Message (cleared on read) 13 1 RESI ESI Flag of Last Received CAN FD Message (cleared on read) 11 1 MCAN_MCAN_RWD RAM Watchdog Register 0x14 32 read-write n 0x0 0x0 WDC Watchdog Configuration (read/write) 0 8 WDV Watchdog Value (read-only) 8 8 MCAN_MCAN_RXBC Receive Rx Buffer Configuration Register 0xAC 32 read-write n 0x0 0x0 RBSA Receive Buffer Start Address 2 14 MCAN_MCAN_RXESC Receive Buffer / FIFO Element Size Configuration Register 0xBC 32 read-write n 0x0 0x0 F0DS Receive FIFO 0 Data Field Size 0 3 F0DSSelect _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 F1DS Receive FIFO 1 Data Field Size 4 3 F1DSSelect _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 RBDS Receive Buffer Data Field Size 8 3 RBDSSelect _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48-byte data field 6 _64_BYTE 64-byte data field 7 MCAN_MCAN_RXF0A Receive FIFO 0 Acknowledge Register 0xA8 32 read-write n 0x0 0x0 F0AI Receive FIFO 0 Acknowledge Index 0 6 MCAN_MCAN_RXF0C Receive FIFO 0 Configuration Register 0xA0 32 read-write n 0x0 0x0 F0OM FIFO 0 Operation Mode 31 1 F0S Receive FIFO 0 Start Address 16 7 F0SA Receive FIFO 0 Start Address 2 14 F0WM Receive FIFO 0 Watermark 24 7 MCAN_MCAN_RXF0S Receive FIFO 0 Status Register 0xA4 32 read-only n 0x0 0x0 F0F Receive FIFO 0 Fill Level 24 1 F0FL Receive FIFO 0 Fill Level 0 7 F0GI Receive FIFO 0 Get Index 8 6 F0PI Receive FIFO 0 Put Index 16 6 RF0L Receive FIFO 0 Message Lost 25 1 MCAN_MCAN_RXF1A Receive FIFO 1 Acknowledge Register 0xB8 32 read-write n 0x0 0x0 F1AI Receive FIFO 1 Acknowledge Index 0 6 MCAN_MCAN_RXF1C Receive FIFO 1 Configuration Register 0xB0 32 read-write n 0x0 0x0 F1OM FIFO 1 Operation Mode 31 1 F1S Receive FIFO 1 Start Address 16 7 F1SA Receive FIFO 1 Start Address 2 14 F1WM Receive FIFO 1 Watermark 24 7 MCAN_MCAN_RXF1S Receive FIFO 1 Status Register 0xB4 32 read-only n 0x0 0x0 DMS Debug Message Status 30 2 DMSSelect IDLE Idle state, wait for reception of debug messages, DMA request is cleared. 0 MSG_A Debug message A received. 1 MSG_AB Debug messages A, B received. 2 MSG_ABC Debug messages A, B, C received, DMA request is set. 3 F1F Receive FIFO 1 Fill Level 24 1 F1FL Receive FIFO 1 Fill Level 0 7 F1GI Receive FIFO 1 Get Index 8 6 F1PI Receive FIFO 1 Put Index 16 6 RF1L Receive FIFO 1 Message Lost 25 1 MCAN_MCAN_SIDFC Standard ID Filter Configuration Register 0x84 32 read-write n 0x0 0x0 FLSSA Filter List Standard Start Address 2 14 LSS List Size Standard 16 8 MCAN_MCAN_TEST Test Register 0x10 32 read-write n 0x0 0x0 LBCK Loop Back Mode (read/write) 4 1 LBCKSelect DISABLED Reset value. Loop Back mode is disabled. 0 ENABLED Loop Back mode is enabled (see Section 1.5.1.9). 1 RX Receive Pin (read-only) 7 1 TDCV Transceiver Delay Compensation Value (read-only) 8 6 TX Control of Transmit Pin (read/write) 5 2 TXSelect RESET Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. 0 SAMPLE_POINT_MONITORING Sample Point can be monitored at pin CANTX. 1 DOMINANT Dominant ('0') level at pin CANTX. 2 RECESSIVE Recessive ('1') at pin CANTX. 3 MCAN_MCAN_TOCC Timeout Counter Configuration Register 0x28 32 read-write n 0x0 0x0 ETOC Enable Timeout Counter 0 1 ETOCSelect NO_TIMEOUT Timeout Counter disabled. 0 TOS_CONTROLLED Timeout Counter enabled. 1 TOP Timeout Period 16 16 TOS Timeout Select 1 2 TOSSelect CONTINUOUS Continuous operation 0 TX_EV_TIMEOUT Timeout controlled by Tx Event FIFO 1 RX0_EV_TIMEOUT Timeout controlled by Receive FIFO 0 2 RX1_EV_TIMEOUT Timeout controlled by Receive FIFO 1 3 MCAN_MCAN_TOCV Timeout Counter Value Register 0x2C 32 read-write n 0x0 0x0 TOC Timeout Counter (cleared on write) 0 16 MCAN_MCAN_TSCC Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 0x0 TCP Timestamp Counter Prescaler 16 4 TSS Timestamp Select 0 2 TSSSelect ALWAYS_0 Timestamp counter value always 0x0000 0 TCP_INC Timestamp counter value incremented according to TCP 1 EXT_TIMESTAMP External timestamp counter value used 2 MCAN_MCAN_TSCV Timestamp Counter Value Register 0x24 32 read-write n 0x0 0x0 TSC Timestamp Counter (cleared on write) 0 16 MCAN_MCAN_TXBAR Transmit Buffer Add Request Register 0xD0 32 read-write n 0x0 0x0 AR0 Add Request for Transmit Buffer 0 0 1 AR1 Add Request for Transmit Buffer 1 1 1 AR10 Add Request for Transmit Buffer 10 10 1 AR11 Add Request for Transmit Buffer 11 11 1 AR12 Add Request for Transmit Buffer 12 12 1 AR13 Add Request for Transmit Buffer 13 13 1 AR14 Add Request for Transmit Buffer 14 14 1 AR15 Add Request for Transmit Buffer 15 15 1 AR16 Add Request for Transmit Buffer 16 16 1 AR17 Add Request for Transmit Buffer 17 17 1 AR18 Add Request for Transmit Buffer 18 18 1 AR19 Add Request for Transmit Buffer 19 19 1 AR2 Add Request for Transmit Buffer 2 2 1 AR20 Add Request for Transmit Buffer 20 20 1 AR21 Add Request for Transmit Buffer 21 21 1 AR22 Add Request for Transmit Buffer 22 22 1 AR23 Add Request for Transmit Buffer 23 23 1 AR24 Add Request for Transmit Buffer 24 24 1 AR25 Add Request for Transmit Buffer 25 25 1 AR26 Add Request for Transmit Buffer 26 26 1 AR27 Add Request for Transmit Buffer 27 27 1 AR28 Add Request for Transmit Buffer 28 28 1 AR29 Add Request for Transmit Buffer 29 29 1 AR3 Add Request for Transmit Buffer 3 3 1 AR30 Add Request for Transmit Buffer 30 30 1 AR31 Add Request for Transmit Buffer 31 31 1 AR4 Add Request for Transmit Buffer 4 4 1 AR5 Add Request for Transmit Buffer 5 5 1 AR6 Add Request for Transmit Buffer 6 6 1 AR7 Add Request for Transmit Buffer 7 7 1 AR8 Add Request for Transmit Buffer 8 8 1 AR9 Add Request for Transmit Buffer 9 9 1 MCAN_MCAN_TXBC Transmit Buffer Configuration Register 0xC0 32 read-write n 0x0 0x0 NDTB Number of Dedicated Transmit Buffers 16 6 TBSA Tx Buffers Start Address 2 14 TFQM Tx FIFO/Queue Mode 30 1 TFQS Transmit FIFO/Queue Size 24 6 MCAN_MCAN_TXBCF Transmit Buffer Cancellation Finished Register 0xDC 32 read-only n 0x0 0x0 CF0 Cancellation Finished for Transmit Buffer 0 0 1 CF1 Cancellation Finished for Transmit Buffer 1 1 1 CF10 Cancellation Finished for Transmit Buffer 10 10 1 CF11 Cancellation Finished for Transmit Buffer 11 11 1 CF12 Cancellation Finished for Transmit Buffer 12 12 1 CF13 Cancellation Finished for Transmit Buffer 13 13 1 CF14 Cancellation Finished for Transmit Buffer 14 14 1 CF15 Cancellation Finished for Transmit Buffer 15 15 1 CF16 Cancellation Finished for Transmit Buffer 16 16 1 CF17 Cancellation Finished for Transmit Buffer 17 17 1 CF18 Cancellation Finished for Transmit Buffer 18 18 1 CF19 Cancellation Finished for Transmit Buffer 19 19 1 CF2 Cancellation Finished for Transmit Buffer 2 2 1 CF20 Cancellation Finished for Transmit Buffer 20 20 1 CF21 Cancellation Finished for Transmit Buffer 21 21 1 CF22 Cancellation Finished for Transmit Buffer 22 22 1 CF23 Cancellation Finished for Transmit Buffer 23 23 1 CF24 Cancellation Finished for Transmit Buffer 24 24 1 CF25 Cancellation Finished for Transmit Buffer 25 25 1 CF26 Cancellation Finished for Transmit Buffer 26 26 1 CF27 Cancellation Finished for Transmit Buffer 27 27 1 CF28 Cancellation Finished for Transmit Buffer 28 28 1 CF29 Cancellation Finished for Transmit Buffer 29 29 1 CF3 Cancellation Finished for Transmit Buffer 3 3 1 CF30 Cancellation Finished for Transmit Buffer 30 30 1 CF31 Cancellation Finished for Transmit Buffer 31 31 1 CF4 Cancellation Finished for Transmit Buffer 4 4 1 CF5 Cancellation Finished for Transmit Buffer 5 5 1 CF6 Cancellation Finished for Transmit Buffer 6 6 1 CF7 Cancellation Finished for Transmit Buffer 7 7 1 CF8 Cancellation Finished for Transmit Buffer 8 8 1 CF9 Cancellation Finished for Transmit Buffer 9 9 1 MCAN_MCAN_TXBCIE Transmit Buffer Cancellation Finished Interrupt Enable Register 0xE4 32 read-write n 0x0 0x0 CFIE0 Cancellation Finished Interrupt Enable for Transmit Buffer 0 0 1 CFIE1 Cancellation Finished Interrupt Enable for Transmit Buffer 1 1 1 CFIE10 Cancellation Finished Interrupt Enable for Transmit Buffer 10 10 1 CFIE11 Cancellation Finished Interrupt Enable for Transmit Buffer 11 11 1 CFIE12 Cancellation Finished Interrupt Enable for Transmit Buffer 12 12 1 CFIE13 Cancellation Finished Interrupt Enable for Transmit Buffer 13 13 1 CFIE14 Cancellation Finished Interrupt Enable for Transmit Buffer 14 14 1 CFIE15 Cancellation Finished Interrupt Enable for Transmit Buffer 15 15 1 CFIE16 Cancellation Finished Interrupt Enable for Transmit Buffer 16 16 1 CFIE17 Cancellation Finished Interrupt Enable for Transmit Buffer 17 17 1 CFIE18 Cancellation Finished Interrupt Enable for Transmit Buffer 18 18 1 CFIE19 Cancellation Finished Interrupt Enable for Transmit Buffer 19 19 1 CFIE2 Cancellation Finished Interrupt Enable for Transmit Buffer 2 2 1 CFIE20 Cancellation Finished Interrupt Enable for Transmit Buffer 20 20 1 CFIE21 Cancellation Finished Interrupt Enable for Transmit Buffer 21 21 1 CFIE22 Cancellation Finished Interrupt Enable for Transmit Buffer 22 22 1 CFIE23 Cancellation Finished Interrupt Enable for Transmit Buffer 23 23 1 CFIE24 Cancellation Finished Interrupt Enable for Transmit Buffer 24 24 1 CFIE25 Cancellation Finished Interrupt Enable for Transmit Buffer 25 25 1 CFIE26 Cancellation Finished Interrupt Enable for Transmit Buffer 26 26 1 CFIE27 Cancellation Finished Interrupt Enable for Transmit Buffer 27 27 1 CFIE28 Cancellation Finished Interrupt Enable for Transmit Buffer 28 28 1 CFIE29 Cancellation Finished Interrupt Enable for Transmit Buffer 29 29 1 CFIE3 Cancellation Finished Interrupt Enable for Transmit Buffer 3 3 1 CFIE30 Cancellation Finished Interrupt Enable for Transmit Buffer 30 30 1 CFIE31 Cancellation Finished Interrupt Enable for Transmit Buffer 31 31 1 CFIE4 Cancellation Finished Interrupt Enable for Transmit Buffer 4 4 1 CFIE5 Cancellation Finished Interrupt Enable for Transmit Buffer 5 5 1 CFIE6 Cancellation Finished Interrupt Enable for Transmit Buffer 6 6 1 CFIE7 Cancellation Finished Interrupt Enable for Transmit Buffer 7 7 1 CFIE8 Cancellation Finished Interrupt Enable for Transmit Buffer 8 8 1 CFIE9 Cancellation Finished Interrupt Enable for Transmit Buffer 9 9 1 MCAN_MCAN_TXBCR Transmit Buffer Cancellation Request Register 0xD4 32 read-write n 0x0 0x0 CR0 Cancellation Request for Transmit Buffer 0 0 1 CR1 Cancellation Request for Transmit Buffer 1 1 1 CR10 Cancellation Request for Transmit Buffer 10 10 1 CR11 Cancellation Request for Transmit Buffer 11 11 1 CR12 Cancellation Request for Transmit Buffer 12 12 1 CR13 Cancellation Request for Transmit Buffer 13 13 1 CR14 Cancellation Request for Transmit Buffer 14 14 1 CR15 Cancellation Request for Transmit Buffer 15 15 1 CR16 Cancellation Request for Transmit Buffer 16 16 1 CR17 Cancellation Request for Transmit Buffer 17 17 1 CR18 Cancellation Request for Transmit Buffer 18 18 1 CR19 Cancellation Request for Transmit Buffer 19 19 1 CR2 Cancellation Request for Transmit Buffer 2 2 1 CR20 Cancellation Request for Transmit Buffer 20 20 1 CR21 Cancellation Request for Transmit Buffer 21 21 1 CR22 Cancellation Request for Transmit Buffer 22 22 1 CR23 Cancellation Request for Transmit Buffer 23 23 1 CR24 Cancellation Request for Transmit Buffer 24 24 1 CR25 Cancellation Request for Transmit Buffer 25 25 1 CR26 Cancellation Request for Transmit Buffer 26 26 1 CR27 Cancellation Request for Transmit Buffer 27 27 1 CR28 Cancellation Request for Transmit Buffer 28 28 1 CR29 Cancellation Request for Transmit Buffer 29 29 1 CR3 Cancellation Request for Transmit Buffer 3 3 1 CR30 Cancellation Request for Transmit Buffer 30 30 1 CR31 Cancellation Request for Transmit Buffer 31 31 1 CR4 Cancellation Request for Transmit Buffer 4 4 1 CR5 Cancellation Request for Transmit Buffer 5 5 1 CR6 Cancellation Request for Transmit Buffer 6 6 1 CR7 Cancellation Request for Transmit Buffer 7 7 1 CR8 Cancellation Request for Transmit Buffer 8 8 1 CR9 Cancellation Request for Transmit Buffer 9 9 1 MCAN_MCAN_TXBRP Transmit Buffer Request Pending Register 0xCC 32 read-only n 0x0 0x0 TRP0 Transmission Request Pending for Buffer 0 0 1 TRP1 Transmission Request Pending for Buffer 1 1 1 TRP10 Transmission Request Pending for Buffer 10 10 1 TRP11 Transmission Request Pending for Buffer 11 11 1 TRP12 Transmission Request Pending for Buffer 12 12 1 TRP13 Transmission Request Pending for Buffer 13 13 1 TRP14 Transmission Request Pending for Buffer 14 14 1 TRP15 Transmission Request Pending for Buffer 15 15 1 TRP16 Transmission Request Pending for Buffer 16 16 1 TRP17 Transmission Request Pending for Buffer 17 17 1 TRP18 Transmission Request Pending for Buffer 18 18 1 TRP19 Transmission Request Pending for Buffer 19 19 1 TRP2 Transmission Request Pending for Buffer 2 2 1 TRP20 Transmission Request Pending for Buffer 20 20 1 TRP21 Transmission Request Pending for Buffer 21 21 1 TRP22 Transmission Request Pending for Buffer 22 22 1 TRP23 Transmission Request Pending for Buffer 23 23 1 TRP24 Transmission Request Pending for Buffer 24 24 1 TRP25 Transmission Request Pending for Buffer 25 25 1 TRP26 Transmission Request Pending for Buffer 26 26 1 TRP27 Transmission Request Pending for Buffer 27 27 1 TRP28 Transmission Request Pending for Buffer 28 28 1 TRP29 Transmission Request Pending for Buffer 29 29 1 TRP3 Transmission Request Pending for Buffer 3 3 1 TRP30 Transmission Request Pending for Buffer 30 30 1 TRP31 Transmission Request Pending for Buffer 31 31 1 TRP4 Transmission Request Pending for Buffer 4 4 1 TRP5 Transmission Request Pending for Buffer 5 5 1 TRP6 Transmission Request Pending for Buffer 6 6 1 TRP7 Transmission Request Pending for Buffer 7 7 1 TRP8 Transmission Request Pending for Buffer 8 8 1 TRP9 Transmission Request Pending for Buffer 9 9 1 MCAN_MCAN_TXBTIE Transmit Buffer Transmission Interrupt Enable Register 0xE0 32 read-write n 0x0 0x0 TIE0 Transmission Interrupt Enable for Buffer 0 0 1 TIE1 Transmission Interrupt Enable for Buffer 1 1 1 TIE10 Transmission Interrupt Enable for Buffer 10 10 1 TIE11 Transmission Interrupt Enable for Buffer 11 11 1 TIE12 Transmission Interrupt Enable for Buffer 12 12 1 TIE13 Transmission Interrupt Enable for Buffer 13 13 1 TIE14 Transmission Interrupt Enable for Buffer 14 14 1 TIE15 Transmission Interrupt Enable for Buffer 15 15 1 TIE16 Transmission Interrupt Enable for Buffer 16 16 1 TIE17 Transmission Interrupt Enable for Buffer 17 17 1 TIE18 Transmission Interrupt Enable for Buffer 18 18 1 TIE19 Transmission Interrupt Enable for Buffer 19 19 1 TIE2 Transmission Interrupt Enable for Buffer 2 2 1 TIE20 Transmission Interrupt Enable for Buffer 20 20 1 TIE21 Transmission Interrupt Enable for Buffer 21 21 1 TIE22 Transmission Interrupt Enable for Buffer 22 22 1 TIE23 Transmission Interrupt Enable for Buffer 23 23 1 TIE24 Transmission Interrupt Enable for Buffer 24 24 1 TIE25 Transmission Interrupt Enable for Buffer 25 25 1 TIE26 Transmission Interrupt Enable for Buffer 26 26 1 TIE27 Transmission Interrupt Enable for Buffer 27 27 1 TIE28 Transmission Interrupt Enable for Buffer 28 28 1 TIE29 Transmission Interrupt Enable for Buffer 29 29 1 TIE3 Transmission Interrupt Enable for Buffer 3 3 1 TIE30 Transmission Interrupt Enable for Buffer 30 30 1 TIE31 Transmission Interrupt Enable for Buffer 31 31 1 TIE4 Transmission Interrupt Enable for Buffer 4 4 1 TIE5 Transmission Interrupt Enable for Buffer 5 5 1 TIE6 Transmission Interrupt Enable for Buffer 6 6 1 TIE7 Transmission Interrupt Enable for Buffer 7 7 1 TIE8 Transmission Interrupt Enable for Buffer 8 8 1 TIE9 Transmission Interrupt Enable for Buffer 9 9 1 MCAN_MCAN_TXBTO Transmit Buffer Transmission Occurred Register 0xD8 32 read-only n 0x0 0x0 TO0 Transmission Occurred for Buffer 0 0 1 TO1 Transmission Occurred for Buffer 1 1 1 TO10 Transmission Occurred for Buffer 10 10 1 TO11 Transmission Occurred for Buffer 11 11 1 TO12 Transmission Occurred for Buffer 12 12 1 TO13 Transmission Occurred for Buffer 13 13 1 TO14 Transmission Occurred for Buffer 14 14 1 TO15 Transmission Occurred for Buffer 15 15 1 TO16 Transmission Occurred for Buffer 16 16 1 TO17 Transmission Occurred for Buffer 17 17 1 TO18 Transmission Occurred for Buffer 18 18 1 TO19 Transmission Occurred for Buffer 19 19 1 TO2 Transmission Occurred for Buffer 2 2 1 TO20 Transmission Occurred for Buffer 20 20 1 TO21 Transmission Occurred for Buffer 21 21 1 TO22 Transmission Occurred for Buffer 22 22 1 TO23 Transmission Occurred for Buffer 23 23 1 TO24 Transmission Occurred for Buffer 24 24 1 TO25 Transmission Occurred for Buffer 25 25 1 TO26 Transmission Occurred for Buffer 26 26 1 TO27 Transmission Occurred for Buffer 27 27 1 TO28 Transmission Occurred for Buffer 28 28 1 TO29 Transmission Occurred for Buffer 29 29 1 TO3 Transmission Occurred for Buffer 3 3 1 TO30 Transmission Occurred for Buffer 30 30 1 TO31 Transmission Occurred for Buffer 31 31 1 TO4 Transmission Occurred for Buffer 4 4 1 TO5 Transmission Occurred for Buffer 5 5 1 TO6 Transmission Occurred for Buffer 6 6 1 TO7 Transmission Occurred for Buffer 7 7 1 TO8 Transmission Occurred for Buffer 8 8 1 TO9 Transmission Occurred for Buffer 9 9 1 MCAN_MCAN_TXEFA Transmit Event FIFO Acknowledge Register 0xF8 32 read-write n 0x0 0x0 EFAI Event FIFO Acknowledge Index 0 5 MCAN_MCAN_TXEFC Transmit Event FIFO Configuration Register 0xF0 32 read-write n 0x0 0x0 EFS Event FIFO Size 16 6 EFSA Event FIFO Start Address 2 14 EFWM Event FIFO Watermark 24 6 MCAN_MCAN_TXEFS Transmit Event FIFO Status Register 0xF4 32 read-only n 0x0 0x0 EFF Event FIFO Full 24 1 EFFL Event FIFO Fill Level 0 6 EFGI Event FIFO Get Index 8 5 EFPI Event FIFO Put Index 16 5 TEFL Tx Event FIFO Element Lost 25 1 MCAN_MCAN_TXESC Transmit Buffer Element Size Configuration Register 0xC8 32 read-write n 0x0 0x0 TBDS Tx Buffer Data Field Size 0 3 TBDSSelect _8_BYTE 8-byte data field 0 _12_BYTE 12-byte data field 1 _16_BYTE 16-byte data field 2 _20_BYTE 20-byte data field 3 _24_BYTE 24-byte data field 4 _32_BYTE 32-byte data field 5 _48_BYTE 48- byte data field 6 _64_BYTE 64-byte data field 7 MCAN_MCAN_TXFQS Transmit FIFO/Queue Status Register 0xC4 32 read-only n 0x0 0x0 TFFL Tx FIFO Free Level 0 6 TFGI Tx FIFO Get Index 8 5 TFQF Tx FIFO/Queue Full 21 1 TFQPI Tx FIFO/Queue Put Index 16 5 MCAN_MCAN_XIDAM Extended ID AND Mask Register 0x90 32 read-write n 0x0 0x0 EIDM Extended ID Mask 0 29 MCAN_MCAN_XIDFC Extended ID Filter Configuration Register 0x88 32 read-write n 0x0 0x0 FLESA Filter List Extended Start Address 2 14 LSE List Size Extended 16 7 NDAT1 New Data 1 Register 0x98 32 read-write n 0x0 ND0 New Data 0 1 read-write ND1 New Data 1 1 read-write ND10 New Data 10 1 read-write ND11 New Data 11 1 read-write ND12 New Data 12 1 read-write ND13 New Data 13 1 read-write ND14 New Data 14 1 read-write ND15 New Data 15 1 read-write ND16 New Data 16 1 read-write ND17 New Data 17 1 read-write ND18 New Data 18 1 read-write ND19 New Data 19 1 read-write ND2 New Data 2 1 read-write ND20 New Data 20 1 read-write ND21 New Data 21 1 read-write ND22 New Data 22 1 read-write ND23 New Data 23 1 read-write ND24 New Data 24 1 read-write ND25 New Data 25 1 read-write ND26 New Data 26 1 read-write ND27 New Data 27 1 read-write ND28 New Data 28 1 read-write ND29 New Data 29 1 read-write ND3 New Data 3 1 read-write ND30 New Data 30 1 read-write ND31 New Data 31 1 read-write ND4 New Data 4 1 read-write ND5 New Data 5 1 read-write ND6 New Data 6 1 read-write ND7 New Data 7 1 read-write ND8 New Data 8 1 read-write ND9 New Data 9 1 read-write NDAT2 New Data 2 Register 0x9C 32 read-write n 0x0 ND32 New Data 0 1 read-write ND33 New Data 1 1 read-write ND34 New Data 2 1 read-write ND35 New Data 3 1 read-write ND36 New Data 4 1 read-write ND37 New Data 5 1 read-write ND38 New Data 6 1 read-write ND39 New Data 7 1 read-write ND40 New Data 8 1 read-write ND41 New Data 9 1 read-write ND42 New Data 10 1 read-write ND43 New Data 11 1 read-write ND44 New Data 12 1 read-write ND45 New Data 13 1 read-write ND46 New Data 14 1 read-write ND47 New Data 15 1 read-write ND48 New Data 16 1 read-write ND49 New Data 17 1 read-write ND50 New Data 18 1 read-write ND51 New Data 19 1 read-write ND52 New Data 20 1 read-write ND53 New Data 21 1 read-write ND54 New Data 22 1 read-write ND55 New Data 23 1 read-write ND56 New Data 24 1 read-write ND57 New Data 25 1 read-write ND58 New Data 26 1 read-write ND59 New Data 27 1 read-write ND60 New Data 28 1 read-write ND61 New Data 29 1 read-write ND62 New Data 30 1 read-write ND63 New Data 31 1 read-write PSR Protocol Status Register 0x44 32 read-only n 0x0 ACT Activity 3 2 read-only SYNCHRONIZING Node is synchronizing on CAN communication 0x0 IDLE Node is neither receiver nor transmitter 0x1 RECEIVER Node is operating as receiver 0x2 TRANSMITTER Node is operating as transmitter 0x3 BO Bus_Off Status 7 1 read-only EP Error Passive 5 1 read-only EW Warning Status 6 1 read-only FLEC Fast Last Error Code (set to 111 on read) 8 3 read-only LEC Last Error Code (set to 111 on read) 0 3 read-only NO_ERROR No error occurred since LEC has been reset by successful reception or transmission. 0x0 STUFF_ERROR More than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 FORM_ERROR A fixed format part of a received frame has the wrong format. 0x2 ACK_ERROR The message transmitted by the MCAN was not acknowledged by another node. 0x3 BIT1_ERROR During the transmission of a message (with the exception of the arbitration field), the device wanted to send a recessive level (bit of logical value '1'), but the monitored bus value was dominant. 0x4 BIT0_ERROR During the transmission of a message (or acknowledge bit, or active error flag, or overload flag), the device wanted to send a dominant level (data or identifier bit logical value '0'), but the monitored bus value was recessive. During Bus_Off recovery this status is set each time a sequence of 11 recessive bits has been monitored. This enables the processor to monitor the proceeding of the Bus_Off recovery sequence (indicating the bus is not stuck at dominant or continuously disturbed). 0x5 CRC_ERROR The CRC check sum of a received message was incorrect. The CRC of an incoming message does not match with the CRC calculated from the received data. 0x6 NO_CHANGE Any read access to the Protocol Status Register re-initializes the LEC to '7'. When the LEC shows the value '7', no CAN bus event was detected since the last processor read access to the Protocol Status Register. 0x7 RBRS BRS Flag of Last Received CAN FD Message (cleared on read) 12 1 read-only REDL Received a CAN FD Message (cleared on read) 13 1 read-only RESI ESI Flag of Last Received CAN FD Message (cleared on read) 11 1 read-only RWD RAM Watchdog Register 0x14 32 read-write n 0x0 WDC Watchdog Configuration (read/write) 0 8 read-write WDV Watchdog Value (read-only) 8 8 read-write RXBC Receive Rx Buffer Configuration Register 0xAC 32 read-write n 0x0 RBSA Receive Buffer Start Address 2 14 read-write RXESC Receive Buffer / FIFO Element Size Configuration Register 0xBC 32 read-write n 0x0 F0DS Receive FIFO 0 Data Field Size 0 3 read-write 8_BYTE 8-byte data field 0x0 12_BYTE 12-byte data field 0x1 16_BYTE 16-byte data field 0x2 20_BYTE 20-byte data field 0x3 24_BYTE 24-byte data field 0x4 32_BYTE 32-byte data field 0x5 48_BYTE 48-byte data field 0x6 64_BYTE 64-byte data field 0x7 F1DS Receive FIFO 1 Data Field Size 4 3 read-write 8_BYTE 8-byte data field 0x0 12_BYTE 12-byte data field 0x1 16_BYTE 16-byte data field 0x2 20_BYTE 20-byte data field 0x3 24_BYTE 24-byte data field 0x4 32_BYTE 32-byte data field 0x5 48_BYTE 48-byte data field 0x6 64_BYTE 64-byte data field 0x7 RBDS Receive Buffer Data Field Size 8 3 read-write 8_BYTE 8-byte data field 0x0 12_BYTE 12-byte data field 0x1 16_BYTE 16-byte data field 0x2 20_BYTE 20-byte data field 0x3 24_BYTE 24-byte data field 0x4 32_BYTE 32-byte data field 0x5 48_BYTE 48-byte data field 0x6 64_BYTE 64-byte data field 0x7 RXF0A Receive FIFO 0 Acknowledge Register 0xA8 32 read-write n 0x0 F0AI Receive FIFO 0 Acknowledge Index 0 6 read-write RXF0C Receive FIFO 0 Configuration Register 0xA0 32 read-write n 0x0 F0OM FIFO 0 Operation Mode 31 1 read-write F0S Receive FIFO 0 Start Address 16 7 read-write F0SA Receive FIFO 0 Start Address 2 14 read-write F0WM Receive FIFO 0 Watermark 24 7 read-write RXF0S Receive FIFO 0 Status Register 0xA4 32 read-only n 0x0 F0F Receive FIFO 0 Fill Level 24 1 read-only F0FL Receive FIFO 0 Fill Level 0 7 read-only F0GI Receive FIFO 0 Get Index 8 6 read-only F0PI Receive FIFO 0 Put Index 16 6 read-only RF0L Receive FIFO 0 Message Lost 25 1 read-only RXF1A Receive FIFO 1 Acknowledge Register 0xB8 32 read-write n 0x0 F1AI Receive FIFO 1 Acknowledge Index 0 6 read-write RXF1C Receive FIFO 1 Configuration Register 0xB0 32 read-write n 0x0 F1OM FIFO 1 Operation Mode 31 1 read-write F1S Receive FIFO 1 Start Address 16 7 read-write F1SA Receive FIFO 1 Start Address 2 14 read-write F1WM Receive FIFO 1 Watermark 24 7 read-write RXF1S Receive FIFO 1 Status Register 0xB4 32 read-only n 0x0 DMS Debug Message Status 30 2 read-only IDLE Idle state, wait for reception of debug messages, DMA request is cleared. 0x0 MSG_A Debug message A received. 0x1 MSG_AB Debug messages A, B received. 0x2 MSG_ABC Debug messages A, B, C received, DMA request is set. 0x3 F1F Receive FIFO 1 Fill Level 24 1 read-only F1FL Receive FIFO 1 Fill Level 0 7 read-only F1GI Receive FIFO 1 Get Index 8 6 read-only F1PI Receive FIFO 1 Put Index 16 6 read-only RF1L Receive FIFO 1 Message Lost 25 1 read-only SIDFC Standard ID Filter Configuration Register 0x84 32 read-write n 0x0 FLSSA Filter List Standard Start Address 2 14 read-write LSS List Size Standard 16 8 read-write TEST Test Register 0x10 32 read-write n LBCK Loop Back Mode (read/write) 4 1 read-write DISABLED Reset value. Loop Back mode is disabled. 0 ENABLED Loop Back mode is enabled (see Section 1.5.1.9). 1 RX Receive Pin (read-only) 7 1 read-write TDCV Transceiver Delay Compensation Value (read-only) 8 6 read-write TX Control of Transmit Pin (read/write) 5 2 read-write RESET Reset value, CANTX controlled by the CAN Core, updated at the end of the CAN bit time. 0x0 SAMPLE_POINT_MONITORING Sample Point can be monitored at pin CANTX. 0x1 DOMINANT Dominant ('0') level at pin CANTX. 0x2 RECESSIVE Recessive ('1') at pin CANTX. 0x3 TOCC Timeout Counter Configuration Register 0x28 32 read-write n 0x0 ETOC Enable Timeout Counter 0 1 read-write NO_TIMEOUT Timeout Counter disabled. 0 TOS_CONTROLLED Timeout Counter enabled. 1 TOP Timeout Period 16 16 read-write TOS Timeout Select 1 2 read-write CONTINUOUS Continuous operation 0x0 TX_EV_TIMEOUT Timeout controlled by Tx Event FIFO 0x1 RX0_EV_TIMEOUT Timeout controlled by Receive FIFO 0 0x2 RX1_EV_TIMEOUT Timeout controlled by Receive FIFO 1 0x3 TOCV Timeout Counter Value Register 0x2C 32 read-write n 0x0 TOC Timeout Counter (cleared on write) 0 16 read-write TSCC Timestamp Counter Configuration Register 0x20 32 read-write n 0x0 TCP Timestamp Counter Prescaler 16 4 read-write TSS Timestamp Select 0 2 read-write ALWAYS_0 Timestamp counter value always 0x0000 0x0 TCP_INC Timestamp counter value incremented according to TCP 0x1 EXT_TIMESTAMP External timestamp counter value used 0x2 TSCV Timestamp Counter Value Register 0x24 32 read-write n 0x0 TSC Timestamp Counter (cleared on write) 0 16 read-write TXBAR Transmit Buffer Add Request Register 0xD0 32 read-write n 0x0 AR0 Add Request for Transmit Buffer 0 0 1 read-write AR1 Add Request for Transmit Buffer 1 1 1 read-write AR10 Add Request for Transmit Buffer 10 10 1 read-write AR11 Add Request for Transmit Buffer 11 11 1 read-write AR12 Add Request for Transmit Buffer 12 12 1 read-write AR13 Add Request for Transmit Buffer 13 13 1 read-write AR14 Add Request for Transmit Buffer 14 14 1 read-write AR15 Add Request for Transmit Buffer 15 15 1 read-write AR16 Add Request for Transmit Buffer 16 16 1 read-write AR17 Add Request for Transmit Buffer 17 17 1 read-write AR18 Add Request for Transmit Buffer 18 18 1 read-write AR19 Add Request for Transmit Buffer 19 19 1 read-write AR2 Add Request for Transmit Buffer 2 2 1 read-write AR20 Add Request for Transmit Buffer 20 20 1 read-write AR21 Add Request for Transmit Buffer 21 21 1 read-write AR22 Add Request for Transmit Buffer 22 22 1 read-write AR23 Add Request for Transmit Buffer 23 23 1 read-write AR24 Add Request for Transmit Buffer 24 24 1 read-write AR25 Add Request for Transmit Buffer 25 25 1 read-write AR26 Add Request for Transmit Buffer 26 26 1 read-write AR27 Add Request for Transmit Buffer 27 27 1 read-write AR28 Add Request for Transmit Buffer 28 28 1 read-write AR29 Add Request for Transmit Buffer 29 29 1 read-write AR3 Add Request for Transmit Buffer 3 3 1 read-write AR30 Add Request for Transmit Buffer 30 30 1 read-write AR31 Add Request for Transmit Buffer 31 31 1 read-write AR4 Add Request for Transmit Buffer 4 4 1 read-write AR5 Add Request for Transmit Buffer 5 5 1 read-write AR6 Add Request for Transmit Buffer 6 6 1 read-write AR7 Add Request for Transmit Buffer 7 7 1 read-write AR8 Add Request for Transmit Buffer 8 8 1 read-write AR9 Add Request for Transmit Buffer 9 9 1 read-write TXBC Transmit Buffer Configuration Register 0xC0 32 read-write n 0x0 NDTB Number of Dedicated Transmit Buffers 16 6 read-write TBSA Tx Buffers Start Address 2 14 read-write TFQM Tx FIFO/Queue Mode 30 1 read-write TFQS Transmit FIFO/Queue Size 24 6 read-write TXBCF Transmit Buffer Cancellation Finished Register 0xDC 32 read-only n 0x0 CF0 Cancellation Finished for Transmit Buffer 0 0 1 read-only CF1 Cancellation Finished for Transmit Buffer 1 1 1 read-only CF10 Cancellation Finished for Transmit Buffer 10 10 1 read-only CF11 Cancellation Finished for Transmit Buffer 11 11 1 read-only CF12 Cancellation Finished for Transmit Buffer 12 12 1 read-only CF13 Cancellation Finished for Transmit Buffer 13 13 1 read-only CF14 Cancellation Finished for Transmit Buffer 14 14 1 read-only CF15 Cancellation Finished for Transmit Buffer 15 15 1 read-only CF16 Cancellation Finished for Transmit Buffer 16 16 1 read-only CF17 Cancellation Finished for Transmit Buffer 17 17 1 read-only CF18 Cancellation Finished for Transmit Buffer 18 18 1 read-only CF19 Cancellation Finished for Transmit Buffer 19 19 1 read-only CF2 Cancellation Finished for Transmit Buffer 2 2 1 read-only CF20 Cancellation Finished for Transmit Buffer 20 20 1 read-only CF21 Cancellation Finished for Transmit Buffer 21 21 1 read-only CF22 Cancellation Finished for Transmit Buffer 22 22 1 read-only CF23 Cancellation Finished for Transmit Buffer 23 23 1 read-only CF24 Cancellation Finished for Transmit Buffer 24 24 1 read-only CF25 Cancellation Finished for Transmit Buffer 25 25 1 read-only CF26 Cancellation Finished for Transmit Buffer 26 26 1 read-only CF27 Cancellation Finished for Transmit Buffer 27 27 1 read-only CF28 Cancellation Finished for Transmit Buffer 28 28 1 read-only CF29 Cancellation Finished for Transmit Buffer 29 29 1 read-only CF3 Cancellation Finished for Transmit Buffer 3 3 1 read-only CF30 Cancellation Finished for Transmit Buffer 30 30 1 read-only CF31 Cancellation Finished for Transmit Buffer 31 31 1 read-only CF4 Cancellation Finished for Transmit Buffer 4 4 1 read-only CF5 Cancellation Finished for Transmit Buffer 5 5 1 read-only CF6 Cancellation Finished for Transmit Buffer 6 6 1 read-only CF7 Cancellation Finished for Transmit Buffer 7 7 1 read-only CF8 Cancellation Finished for Transmit Buffer 8 8 1 read-only CF9 Cancellation Finished for Transmit Buffer 9 9 1 read-only TXBCIE Transmit Buffer Cancellation Finished Interrupt Enable Register 0xE4 32 read-write n 0x0 CFIE0 Cancellation Finished Interrupt Enable for Transmit Buffer 0 0 1 read-write CFIE1 Cancellation Finished Interrupt Enable for Transmit Buffer 1 1 1 read-write CFIE10 Cancellation Finished Interrupt Enable for Transmit Buffer 10 10 1 read-write CFIE11 Cancellation Finished Interrupt Enable for Transmit Buffer 11 11 1 read-write CFIE12 Cancellation Finished Interrupt Enable for Transmit Buffer 12 12 1 read-write CFIE13 Cancellation Finished Interrupt Enable for Transmit Buffer 13 13 1 read-write CFIE14 Cancellation Finished Interrupt Enable for Transmit Buffer 14 14 1 read-write CFIE15 Cancellation Finished Interrupt Enable for Transmit Buffer 15 15 1 read-write CFIE16 Cancellation Finished Interrupt Enable for Transmit Buffer 16 16 1 read-write CFIE17 Cancellation Finished Interrupt Enable for Transmit Buffer 17 17 1 read-write CFIE18 Cancellation Finished Interrupt Enable for Transmit Buffer 18 18 1 read-write CFIE19 Cancellation Finished Interrupt Enable for Transmit Buffer 19 19 1 read-write CFIE2 Cancellation Finished Interrupt Enable for Transmit Buffer 2 2 1 read-write CFIE20 Cancellation Finished Interrupt Enable for Transmit Buffer 20 20 1 read-write CFIE21 Cancellation Finished Interrupt Enable for Transmit Buffer 21 21 1 read-write CFIE22 Cancellation Finished Interrupt Enable for Transmit Buffer 22 22 1 read-write CFIE23 Cancellation Finished Interrupt Enable for Transmit Buffer 23 23 1 read-write CFIE24 Cancellation Finished Interrupt Enable for Transmit Buffer 24 24 1 read-write CFIE25 Cancellation Finished Interrupt Enable for Transmit Buffer 25 25 1 read-write CFIE26 Cancellation Finished Interrupt Enable for Transmit Buffer 26 26 1 read-write CFIE27 Cancellation Finished Interrupt Enable for Transmit Buffer 27 27 1 read-write CFIE28 Cancellation Finished Interrupt Enable for Transmit Buffer 28 28 1 read-write CFIE29 Cancellation Finished Interrupt Enable for Transmit Buffer 29 29 1 read-write CFIE3 Cancellation Finished Interrupt Enable for Transmit Buffer 3 3 1 read-write CFIE30 Cancellation Finished Interrupt Enable for Transmit Buffer 30 30 1 read-write CFIE31 Cancellation Finished Interrupt Enable for Transmit Buffer 31 31 1 read-write CFIE4 Cancellation Finished Interrupt Enable for Transmit Buffer 4 4 1 read-write CFIE5 Cancellation Finished Interrupt Enable for Transmit Buffer 5 5 1 read-write CFIE6 Cancellation Finished Interrupt Enable for Transmit Buffer 6 6 1 read-write CFIE7 Cancellation Finished Interrupt Enable for Transmit Buffer 7 7 1 read-write CFIE8 Cancellation Finished Interrupt Enable for Transmit Buffer 8 8 1 read-write CFIE9 Cancellation Finished Interrupt Enable for Transmit Buffer 9 9 1 read-write TXBCR Transmit Buffer Cancellation Request Register 0xD4 32 read-write n 0x0 CR0 Cancellation Request for Transmit Buffer 0 0 1 read-write CR1 Cancellation Request for Transmit Buffer 1 1 1 read-write CR10 Cancellation Request for Transmit Buffer 10 10 1 read-write CR11 Cancellation Request for Transmit Buffer 11 11 1 read-write CR12 Cancellation Request for Transmit Buffer 12 12 1 read-write CR13 Cancellation Request for Transmit Buffer 13 13 1 read-write CR14 Cancellation Request for Transmit Buffer 14 14 1 read-write CR15 Cancellation Request for Transmit Buffer 15 15 1 read-write CR16 Cancellation Request for Transmit Buffer 16 16 1 read-write CR17 Cancellation Request for Transmit Buffer 17 17 1 read-write CR18 Cancellation Request for Transmit Buffer 18 18 1 read-write CR19 Cancellation Request for Transmit Buffer 19 19 1 read-write CR2 Cancellation Request for Transmit Buffer 2 2 1 read-write CR20 Cancellation Request for Transmit Buffer 20 20 1 read-write CR21 Cancellation Request for Transmit Buffer 21 21 1 read-write CR22 Cancellation Request for Transmit Buffer 22 22 1 read-write CR23 Cancellation Request for Transmit Buffer 23 23 1 read-write CR24 Cancellation Request for Transmit Buffer 24 24 1 read-write CR25 Cancellation Request for Transmit Buffer 25 25 1 read-write CR26 Cancellation Request for Transmit Buffer 26 26 1 read-write CR27 Cancellation Request for Transmit Buffer 27 27 1 read-write CR28 Cancellation Request for Transmit Buffer 28 28 1 read-write CR29 Cancellation Request for Transmit Buffer 29 29 1 read-write CR3 Cancellation Request for Transmit Buffer 3 3 1 read-write CR30 Cancellation Request for Transmit Buffer 30 30 1 read-write CR31 Cancellation Request for Transmit Buffer 31 31 1 read-write CR4 Cancellation Request for Transmit Buffer 4 4 1 read-write CR5 Cancellation Request for Transmit Buffer 5 5 1 read-write CR6 Cancellation Request for Transmit Buffer 6 6 1 read-write CR7 Cancellation Request for Transmit Buffer 7 7 1 read-write CR8 Cancellation Request for Transmit Buffer 8 8 1 read-write CR9 Cancellation Request for Transmit Buffer 9 9 1 read-write TXBRP Transmit Buffer Request Pending Register 0xCC 32 read-only n 0x0 TRP0 Transmission Request Pending for Buffer 0 0 1 read-only TRP1 Transmission Request Pending for Buffer 1 1 1 read-only TRP10 Transmission Request Pending for Buffer 10 10 1 read-only TRP11 Transmission Request Pending for Buffer 11 11 1 read-only TRP12 Transmission Request Pending for Buffer 12 12 1 read-only TRP13 Transmission Request Pending for Buffer 13 13 1 read-only TRP14 Transmission Request Pending for Buffer 14 14 1 read-only TRP15 Transmission Request Pending for Buffer 15 15 1 read-only TRP16 Transmission Request Pending for Buffer 16 16 1 read-only TRP17 Transmission Request Pending for Buffer 17 17 1 read-only TRP18 Transmission Request Pending for Buffer 18 18 1 read-only TRP19 Transmission Request Pending for Buffer 19 19 1 read-only TRP2 Transmission Request Pending for Buffer 2 2 1 read-only TRP20 Transmission Request Pending for Buffer 20 20 1 read-only TRP21 Transmission Request Pending for Buffer 21 21 1 read-only TRP22 Transmission Request Pending for Buffer 22 22 1 read-only TRP23 Transmission Request Pending for Buffer 23 23 1 read-only TRP24 Transmission Request Pending for Buffer 24 24 1 read-only TRP25 Transmission Request Pending for Buffer 25 25 1 read-only TRP26 Transmission Request Pending for Buffer 26 26 1 read-only TRP27 Transmission Request Pending for Buffer 27 27 1 read-only TRP28 Transmission Request Pending for Buffer 28 28 1 read-only TRP29 Transmission Request Pending for Buffer 29 29 1 read-only TRP3 Transmission Request Pending for Buffer 3 3 1 read-only TRP30 Transmission Request Pending for Buffer 30 30 1 read-only TRP31 Transmission Request Pending for Buffer 31 31 1 read-only TRP4 Transmission Request Pending for Buffer 4 4 1 read-only TRP5 Transmission Request Pending for Buffer 5 5 1 read-only TRP6 Transmission Request Pending for Buffer 6 6 1 read-only TRP7 Transmission Request Pending for Buffer 7 7 1 read-only TRP8 Transmission Request Pending for Buffer 8 8 1 read-only TRP9 Transmission Request Pending for Buffer 9 9 1 read-only TXBTIE Transmit Buffer Transmission Interrupt Enable Register 0xE0 32 read-write n 0x0 TIE0 Transmission Interrupt Enable for Buffer 0 0 1 read-write TIE1 Transmission Interrupt Enable for Buffer 1 1 1 read-write TIE10 Transmission Interrupt Enable for Buffer 10 10 1 read-write TIE11 Transmission Interrupt Enable for Buffer 11 11 1 read-write TIE12 Transmission Interrupt Enable for Buffer 12 12 1 read-write TIE13 Transmission Interrupt Enable for Buffer 13 13 1 read-write TIE14 Transmission Interrupt Enable for Buffer 14 14 1 read-write TIE15 Transmission Interrupt Enable for Buffer 15 15 1 read-write TIE16 Transmission Interrupt Enable for Buffer 16 16 1 read-write TIE17 Transmission Interrupt Enable for Buffer 17 17 1 read-write TIE18 Transmission Interrupt Enable for Buffer 18 18 1 read-write TIE19 Transmission Interrupt Enable for Buffer 19 19 1 read-write TIE2 Transmission Interrupt Enable for Buffer 2 2 1 read-write TIE20 Transmission Interrupt Enable for Buffer 20 20 1 read-write TIE21 Transmission Interrupt Enable for Buffer 21 21 1 read-write TIE22 Transmission Interrupt Enable for Buffer 22 22 1 read-write TIE23 Transmission Interrupt Enable for Buffer 23 23 1 read-write TIE24 Transmission Interrupt Enable for Buffer 24 24 1 read-write TIE25 Transmission Interrupt Enable for Buffer 25 25 1 read-write TIE26 Transmission Interrupt Enable for Buffer 26 26 1 read-write TIE27 Transmission Interrupt Enable for Buffer 27 27 1 read-write TIE28 Transmission Interrupt Enable for Buffer 28 28 1 read-write TIE29 Transmission Interrupt Enable for Buffer 29 29 1 read-write TIE3 Transmission Interrupt Enable for Buffer 3 3 1 read-write TIE30 Transmission Interrupt Enable for Buffer 30 30 1 read-write TIE31 Transmission Interrupt Enable for Buffer 31 31 1 read-write TIE4 Transmission Interrupt Enable for Buffer 4 4 1 read-write TIE5 Transmission Interrupt Enable for Buffer 5 5 1 read-write TIE6 Transmission Interrupt Enable for Buffer 6 6 1 read-write TIE7 Transmission Interrupt Enable for Buffer 7 7 1 read-write TIE8 Transmission Interrupt Enable for Buffer 8 8 1 read-write TIE9 Transmission Interrupt Enable for Buffer 9 9 1 read-write TXBTO Transmit Buffer Transmission Occurred Register 0xD8 32 read-only n 0x0 TO0 Transmission Occurred for Buffer 0 0 1 read-only TO1 Transmission Occurred for Buffer 1 1 1 read-only TO10 Transmission Occurred for Buffer 10 10 1 read-only TO11 Transmission Occurred for Buffer 11 11 1 read-only TO12 Transmission Occurred for Buffer 12 12 1 read-only TO13 Transmission Occurred for Buffer 13 13 1 read-only TO14 Transmission Occurred for Buffer 14 14 1 read-only TO15 Transmission Occurred for Buffer 15 15 1 read-only TO16 Transmission Occurred for Buffer 16 16 1 read-only TO17 Transmission Occurred for Buffer 17 17 1 read-only TO18 Transmission Occurred for Buffer 18 18 1 read-only TO19 Transmission Occurred for Buffer 19 19 1 read-only TO2 Transmission Occurred for Buffer 2 2 1 read-only TO20 Transmission Occurred for Buffer 20 20 1 read-only TO21 Transmission Occurred for Buffer 21 21 1 read-only TO22 Transmission Occurred for Buffer 22 22 1 read-only TO23 Transmission Occurred for Buffer 23 23 1 read-only TO24 Transmission Occurred for Buffer 24 24 1 read-only TO25 Transmission Occurred for Buffer 25 25 1 read-only TO26 Transmission Occurred for Buffer 26 26 1 read-only TO27 Transmission Occurred for Buffer 27 27 1 read-only TO28 Transmission Occurred for Buffer 28 28 1 read-only TO29 Transmission Occurred for Buffer 29 29 1 read-only TO3 Transmission Occurred for Buffer 3 3 1 read-only TO30 Transmission Occurred for Buffer 30 30 1 read-only TO31 Transmission Occurred for Buffer 31 31 1 read-only TO4 Transmission Occurred for Buffer 4 4 1 read-only TO5 Transmission Occurred for Buffer 5 5 1 read-only TO6 Transmission Occurred for Buffer 6 6 1 read-only TO7 Transmission Occurred for Buffer 7 7 1 read-only TO8 Transmission Occurred for Buffer 8 8 1 read-only TO9 Transmission Occurred for Buffer 9 9 1 read-only TXEFA Transmit Event FIFO Acknowledge Register 0xF8 32 read-write n 0x0 EFAI Event FIFO Acknowledge Index 0 5 read-write TXEFC Transmit Event FIFO Configuration Register 0xF0 32 read-write n 0x0 EFS Event FIFO Size 16 6 read-write EFSA Event FIFO Start Address 2 14 read-write EFWM Event FIFO Watermark 24 6 read-write TXEFS Transmit Event FIFO Status Register 0xF4 32 read-only n 0x0 EFF Event FIFO Full 24 1 read-only EFFL Event FIFO Fill Level 0 6 read-only EFGI Event FIFO Get Index 8 5 read-only EFPI Event FIFO Put Index 16 5 read-only TEFL Tx Event FIFO Element Lost 25 1 read-only TXESC Transmit Buffer Element Size Configuration Register 0xC8 32 read-write n 0x0 TBDS Tx Buffer Data Field Size 0 3 read-write 8_BYTE 8-byte data field 0x0 12_BYTE 12-byte data field 0x1 16_BYTE 16-byte data field 0x2 20_BYTE 20-byte data field 0x3 24_BYTE 24-byte data field 0x4 32_BYTE 32-byte data field 0x5 48_BYTE 4- byte data field 0x6 64_BYTE 64-byte data field 0x7 TXFQS Transmit FIFO/Queue Status Register 0xC4 32 read-only n 0x0 TFFL Tx FIFO Free Level 0 6 read-only TFGI Tx FIFO Get Index 8 5 read-only TFQF Tx FIFO/Queue Full 21 1 read-only TFQPI Tx FIFO/Queue Put Index 16 5 read-only XIDAM Extended ID AND Mask Register 0x90 32 read-write n 0x0 EIDM Extended ID Mask 0 29 read-write XIDFC Extended ID Filter Configuration Register 0x88 32 read-write n 0x0 FLESA Filter List Extended Start Address 2 14 read-write LSE List Size Extended 16 7 read-write MPU Memory Protection Unit MPU 0x0 0x0 0x2C registers n CTRL MPU Control Register 0x4 32 read-write n 0x0 0x0 ENABLE Enables the MPU 0 1 HFNMIENA Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers. 1 1 PRIVDEFENA Enables privileged software access to the default memory map. 2 1 RASR MPU Region Attribute and Size Register 0x10 32 read-write n 0x0 0x0 AP Access permission field. 24 3 B MPU access permission attributes. 16 1 C MPU access permission attributes. 17 1 ENABLE Region enable bit. 0 1 S Shareable bit. 18 1 SIZE Specifies the size of the MPU protection region. 1 5 SRD Subregion disable bits. 8 8 TEX MPU access permission attributes. 19 3 XN Instruction access disable bit. 28 1 RASR_A1 MPU Alias 1 Region Attribute and Size Register 0x18 32 read-write n 0x0 0x0 RASR_A2 MPU Alias 2 Region Attribute and Size Register 0x20 32 read-write n 0x0 0x0 RASR_A3 MPU Alias 3 Region Attribute and Size Register 0x28 32 read-write n 0x0 0x0 RBAR MPU Region Base Address Register 0xC 32 read-write n 0x0 0x0 ADDR Region base address field. 5 27 REGION MPU region field. 0 4 VALID MPU Region Number valid bit. 4 1 RBAR_A1 MPU Alias 1 Region Base Address Register 0x14 32 read-write n 0x0 0x0 RBAR_A2 MPU Alias 2 Region Base Address Register 0x1C 32 read-write n 0x0 0x0 RBAR_A3 MPU Alias 3 Region Base Address Register 0x24 32 read-write n 0x0 0x0 RNR MPU Region Number Register 0x8 32 read-write n 0x0 0x0 REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. 0 8 TYPE MPU Type Register 0x0 32 read-write n 0x0 0x0 DREGION Indicates the number of supported MPU instruction regions. 8 8 IREGION Indicates the number of supported MPU data regions. 16 8 SEPARATE Indicates support for unified or separate instruction and date memory maps. 0 1 NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0xE04 registers n IABR[0] Interrupt Active bit Register n 0x400 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR[1] Interrupt Active bit Register n 0x604 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR[2] Interrupt Active bit Register n 0x80C 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR[3] Interrupt Active bit Register n 0xA18 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR[4] Interrupt Active bit Register n 0xC28 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR[5] Interrupt Active bit Register n 0xE3C 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR[6] Interrupt Active bit Register n 0x1054 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 IABR[7] Interrupt Active bit Register n 0x1270 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 ICER[0] Interrupt Clear Enable Register n 0x100 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[1] Interrupt Clear Enable Register n 0x184 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[2] Interrupt Clear Enable Register n 0x20C 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[3] Interrupt Clear Enable Register n 0x298 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[4] Interrupt Clear Enable Register n 0x328 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[5] Interrupt Clear Enable Register n 0x3BC 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[6] Interrupt Clear Enable Register n 0x454 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICER[7] Interrupt Clear Enable Register n 0x4F0 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 ICPR[0] Interrupt Clear Pending Register n 0x300 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[1] Interrupt Clear Pending Register n 0x484 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[2] Interrupt Clear Pending Register n 0x60C 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[3] Interrupt Clear Pending Register n 0x798 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[4] Interrupt Clear Pending Register n 0x928 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[5] Interrupt Clear Pending Register n 0xABC 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[6] Interrupt Clear Pending Register n 0xC54 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 ICPR[7] Interrupt Clear Pending Register n 0xDF0 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 IP[0] Interrupt Priority Register (8Bit wide) n 0x600 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[100] Interrupt Priority Register (8Bit wide) n 0x145BA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[101] Interrupt Priority Register (8Bit wide) n 0x1491F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[102] Interrupt Priority Register (8Bit wide) n 0x14C85 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[103] Interrupt Priority Register (8Bit wide) n 0x14FEC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[104] Interrupt Priority Register (8Bit wide) n 0x15354 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[105] Interrupt Priority Register (8Bit wide) n 0x156BD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[106] Interrupt Priority Register (8Bit wide) n 0x15A27 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[107] Interrupt Priority Register (8Bit wide) n 0x15D92 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[108] Interrupt Priority Register (8Bit wide) n 0x160FE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[109] Interrupt Priority Register (8Bit wide) n 0x1646B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[10] Interrupt Priority Register (8Bit wide) n 0x2437 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[110] Interrupt Priority Register (8Bit wide) n 0x167D9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[111] Interrupt Priority Register (8Bit wide) n 0x16B48 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[112] Interrupt Priority Register (8Bit wide) n 0x16EB8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[113] Interrupt Priority Register (8Bit wide) n 0x17229 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[114] Interrupt Priority Register (8Bit wide) n 0x1759B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[115] Interrupt Priority Register (8Bit wide) n 0x1790E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[116] Interrupt Priority Register (8Bit wide) n 0x17C82 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[117] Interrupt Priority Register (8Bit wide) n 0x17FF7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[118] Interrupt Priority Register (8Bit wide) n 0x1836D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[119] Interrupt Priority Register (8Bit wide) n 0x186E4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[11] Interrupt Priority Register (8Bit wide) n 0x2742 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[120] Interrupt Priority Register (8Bit wide) n 0x18A5C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[121] Interrupt Priority Register (8Bit wide) n 0x18DD5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[122] Interrupt Priority Register (8Bit wide) n 0x1914F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[123] Interrupt Priority Register (8Bit wide) n 0x194CA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[124] Interrupt Priority Register (8Bit wide) n 0x19846 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[125] Interrupt Priority Register (8Bit wide) n 0x19BC3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[126] Interrupt Priority Register (8Bit wide) n 0x19F41 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[127] Interrupt Priority Register (8Bit wide) n 0x1A2C0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[128] Interrupt Priority Register (8Bit wide) n 0x1A640 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[129] Interrupt Priority Register (8Bit wide) n 0x1A9C1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[12] Interrupt Priority Register (8Bit wide) n 0x2A4E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[130] Interrupt Priority Register (8Bit wide) n 0x1AD43 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[131] Interrupt Priority Register (8Bit wide) n 0x1B0C6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[132] Interrupt Priority Register (8Bit wide) n 0x1B44A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[133] Interrupt Priority Register (8Bit wide) n 0x1B7CF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[134] Interrupt Priority Register (8Bit wide) n 0x1BB55 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[135] Interrupt Priority Register (8Bit wide) n 0x1BEDC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[136] Interrupt Priority Register (8Bit wide) n 0x1C264 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[137] Interrupt Priority Register (8Bit wide) n 0x1C5ED 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[138] Interrupt Priority Register (8Bit wide) n 0x1C977 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[139] Interrupt Priority Register (8Bit wide) n 0x1CD02 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[13] Interrupt Priority Register (8Bit wide) n 0x2D5B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[140] Interrupt Priority Register (8Bit wide) n 0x1D08E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[141] Interrupt Priority Register (8Bit wide) n 0x1D41B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[142] Interrupt Priority Register (8Bit wide) n 0x1D7A9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[143] Interrupt Priority Register (8Bit wide) n 0x1DB38 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[144] Interrupt Priority Register (8Bit wide) n 0x1DEC8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[145] Interrupt Priority Register (8Bit wide) n 0x1E259 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[146] Interrupt Priority Register (8Bit wide) n 0x1E5EB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[147] Interrupt Priority Register (8Bit wide) n 0x1E97E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[148] Interrupt Priority Register (8Bit wide) n 0x1ED12 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[149] Interrupt Priority Register (8Bit wide) n 0x1F0A7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[14] Interrupt Priority Register (8Bit wide) n 0x3069 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[150] Interrupt Priority Register (8Bit wide) n 0x1F43D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[151] Interrupt Priority Register (8Bit wide) n 0x1F7D4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[152] Interrupt Priority Register (8Bit wide) n 0x1FB6C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[153] Interrupt Priority Register (8Bit wide) n 0x1FF05 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[154] Interrupt Priority Register (8Bit wide) n 0x2029F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[155] Interrupt Priority Register (8Bit wide) n 0x2063A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[156] Interrupt Priority Register (8Bit wide) n 0x209D6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[157] Interrupt Priority Register (8Bit wide) n 0x20D73 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[158] Interrupt Priority Register (8Bit wide) n 0x21111 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[159] Interrupt Priority Register (8Bit wide) n 0x214B0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[15] Interrupt Priority Register (8Bit wide) n 0x3378 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[160] Interrupt Priority Register (8Bit wide) n 0x21850 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[161] Interrupt Priority Register (8Bit wide) n 0x21BF1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[162] Interrupt Priority Register (8Bit wide) n 0x21F93 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[163] Interrupt Priority Register (8Bit wide) n 0x22336 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[164] Interrupt Priority Register (8Bit wide) n 0x226DA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[165] Interrupt Priority Register (8Bit wide) n 0x22A7F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[166] Interrupt Priority Register (8Bit wide) n 0x22E25 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[167] Interrupt Priority Register (8Bit wide) n 0x231CC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[168] Interrupt Priority Register (8Bit wide) n 0x23574 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[169] Interrupt Priority Register (8Bit wide) n 0x2391D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[16] Interrupt Priority Register (8Bit wide) n 0x3688 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[170] Interrupt Priority Register (8Bit wide) n 0x23CC7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[171] Interrupt Priority Register (8Bit wide) n 0x24072 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[172] Interrupt Priority Register (8Bit wide) n 0x2441E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[173] Interrupt Priority Register (8Bit wide) n 0x247CB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[174] Interrupt Priority Register (8Bit wide) n 0x24B79 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[175] Interrupt Priority Register (8Bit wide) n 0x24F28 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[176] Interrupt Priority Register (8Bit wide) n 0x252D8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[177] Interrupt Priority Register (8Bit wide) n 0x25689 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[178] Interrupt Priority Register (8Bit wide) n 0x25A3B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[179] Interrupt Priority Register (8Bit wide) n 0x25DEE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[17] Interrupt Priority Register (8Bit wide) n 0x3999 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[180] Interrupt Priority Register (8Bit wide) n 0x261A2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[181] Interrupt Priority Register (8Bit wide) n 0x26557 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[182] Interrupt Priority Register (8Bit wide) n 0x2690D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[183] Interrupt Priority Register (8Bit wide) n 0x26CC4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[184] Interrupt Priority Register (8Bit wide) n 0x2707C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[185] Interrupt Priority Register (8Bit wide) n 0x27435 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[186] Interrupt Priority Register (8Bit wide) n 0x277EF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[187] Interrupt Priority Register (8Bit wide) n 0x27BAA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[188] Interrupt Priority Register (8Bit wide) n 0x27F66 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[189] Interrupt Priority Register (8Bit wide) n 0x28323 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[18] Interrupt Priority Register (8Bit wide) n 0x3CAB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[190] Interrupt Priority Register (8Bit wide) n 0x286E1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[191] Interrupt Priority Register (8Bit wide) n 0x28AA0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[192] Interrupt Priority Register (8Bit wide) n 0x28E60 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[193] Interrupt Priority Register (8Bit wide) n 0x29221 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[194] Interrupt Priority Register (8Bit wide) n 0x295E3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[195] Interrupt Priority Register (8Bit wide) n 0x299A6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[196] Interrupt Priority Register (8Bit wide) n 0x29D6A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[197] Interrupt Priority Register (8Bit wide) n 0x2A12F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[198] Interrupt Priority Register (8Bit wide) n 0x2A4F5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[199] Interrupt Priority Register (8Bit wide) n 0x2A8BC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[19] Interrupt Priority Register (8Bit wide) n 0x3FBE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[1] Interrupt Priority Register (8Bit wide) n 0x901 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[200] Interrupt Priority Register (8Bit wide) n 0x2AC84 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[201] Interrupt Priority Register (8Bit wide) n 0x2B04D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[202] Interrupt Priority Register (8Bit wide) n 0x2B417 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[203] Interrupt Priority Register (8Bit wide) n 0x2B7E2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[204] Interrupt Priority Register (8Bit wide) n 0x2BBAE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[205] Interrupt Priority Register (8Bit wide) n 0x2BF7B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[206] Interrupt Priority Register (8Bit wide) n 0x2C349 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[207] Interrupt Priority Register (8Bit wide) n 0x2C718 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[208] Interrupt Priority Register (8Bit wide) n 0x2CAE8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[209] Interrupt Priority Register (8Bit wide) n 0x2CEB9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[20] Interrupt Priority Register (8Bit wide) n 0x42D2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[210] Interrupt Priority Register (8Bit wide) n 0x2D28B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[211] Interrupt Priority Register (8Bit wide) n 0x2D65E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[212] Interrupt Priority Register (8Bit wide) n 0x2DA32 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[213] Interrupt Priority Register (8Bit wide) n 0x2DE07 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[214] Interrupt Priority Register (8Bit wide) n 0x2E1DD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[215] Interrupt Priority Register (8Bit wide) n 0x2E5B4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[216] Interrupt Priority Register (8Bit wide) n 0x2E98C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[217] Interrupt Priority Register (8Bit wide) n 0x2ED65 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[218] Interrupt Priority Register (8Bit wide) n 0x2F13F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[219] Interrupt Priority Register (8Bit wide) n 0x2F51A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[21] Interrupt Priority Register (8Bit wide) n 0x45E7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[220] Interrupt Priority Register (8Bit wide) n 0x2F8F6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[221] Interrupt Priority Register (8Bit wide) n 0x2FCD3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[222] Interrupt Priority Register (8Bit wide) n 0x300B1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[223] Interrupt Priority Register (8Bit wide) n 0x30490 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[224] Interrupt Priority Register (8Bit wide) n 0x30870 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[225] Interrupt Priority Register (8Bit wide) n 0x30C51 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[226] Interrupt Priority Register (8Bit wide) n 0x31033 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[227] Interrupt Priority Register (8Bit wide) n 0x31416 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[228] Interrupt Priority Register (8Bit wide) n 0x317FA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[229] Interrupt Priority Register (8Bit wide) n 0x31BDF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[22] Interrupt Priority Register (8Bit wide) n 0x48FD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[230] Interrupt Priority Register (8Bit wide) n 0x31FC5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[231] Interrupt Priority Register (8Bit wide) n 0x323AC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[232] Interrupt Priority Register (8Bit wide) n 0x32794 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[233] Interrupt Priority Register (8Bit wide) n 0x32B7D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[234] Interrupt Priority Register (8Bit wide) n 0x32F67 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[235] Interrupt Priority Register (8Bit wide) n 0x33352 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[236] Interrupt Priority Register (8Bit wide) n 0x3373E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[237] Interrupt Priority Register (8Bit wide) n 0x33B2B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[238] Interrupt Priority Register (8Bit wide) n 0x33F19 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[239] Interrupt Priority Register (8Bit wide) n 0x34308 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[23] Interrupt Priority Register (8Bit wide) n 0x4C14 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[24] Interrupt Priority Register (8Bit wide) n 0x4F2C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[25] Interrupt Priority Register (8Bit wide) n 0x5245 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[26] Interrupt Priority Register (8Bit wide) n 0x555F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[27] Interrupt Priority Register (8Bit wide) n 0x587A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[28] Interrupt Priority Register (8Bit wide) n 0x5B96 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[29] Interrupt Priority Register (8Bit wide) n 0x5EB3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[2] Interrupt Priority Register (8Bit wide) n 0xC03 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[30] Interrupt Priority Register (8Bit wide) n 0x61D1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[31] Interrupt Priority Register (8Bit wide) n 0x64F0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[32] Interrupt Priority Register (8Bit wide) n 0x6810 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[33] Interrupt Priority Register (8Bit wide) n 0x6B31 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[34] Interrupt Priority Register (8Bit wide) n 0x6E53 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[35] Interrupt Priority Register (8Bit wide) n 0x7176 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[36] Interrupt Priority Register (8Bit wide) n 0x749A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[37] Interrupt Priority Register (8Bit wide) n 0x77BF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[38] Interrupt Priority Register (8Bit wide) n 0x7AE5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[39] Interrupt Priority Register (8Bit wide) n 0x7E0C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[3] Interrupt Priority Register (8Bit wide) n 0xF06 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[40] Interrupt Priority Register (8Bit wide) n 0x8134 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[41] Interrupt Priority Register (8Bit wide) n 0x845D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[42] Interrupt Priority Register (8Bit wide) n 0x8787 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[43] Interrupt Priority Register (8Bit wide) n 0x8AB2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[44] Interrupt Priority Register (8Bit wide) n 0x8DDE 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[45] Interrupt Priority Register (8Bit wide) n 0x910B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[46] Interrupt Priority Register (8Bit wide) n 0x9439 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[47] Interrupt Priority Register (8Bit wide) n 0x9768 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[48] Interrupt Priority Register (8Bit wide) n 0x9A98 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[49] Interrupt Priority Register (8Bit wide) n 0x9DC9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[4] Interrupt Priority Register (8Bit wide) n 0x120A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[50] Interrupt Priority Register (8Bit wide) n 0xA0FB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[51] Interrupt Priority Register (8Bit wide) n 0xA42E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[52] Interrupt Priority Register (8Bit wide) n 0xA762 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[53] Interrupt Priority Register (8Bit wide) n 0xAA97 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[54] Interrupt Priority Register (8Bit wide) n 0xADCD 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[55] Interrupt Priority Register (8Bit wide) n 0xB104 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[56] Interrupt Priority Register (8Bit wide) n 0xB43C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[57] Interrupt Priority Register (8Bit wide) n 0xB775 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[58] Interrupt Priority Register (8Bit wide) n 0xBAAF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[59] Interrupt Priority Register (8Bit wide) n 0xBDEA 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[5] Interrupt Priority Register (8Bit wide) n 0x150F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[60] Interrupt Priority Register (8Bit wide) n 0xC126 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[61] Interrupt Priority Register (8Bit wide) n 0xC463 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[62] Interrupt Priority Register (8Bit wide) n 0xC7A1 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[63] Interrupt Priority Register (8Bit wide) n 0xCAE0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[64] Interrupt Priority Register (8Bit wide) n 0xCE20 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[65] Interrupt Priority Register (8Bit wide) n 0xD161 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[66] Interrupt Priority Register (8Bit wide) n 0xD4A3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[67] Interrupt Priority Register (8Bit wide) n 0xD7E6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[68] Interrupt Priority Register (8Bit wide) n 0xDB2A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[69] Interrupt Priority Register (8Bit wide) n 0xDE6F 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[6] Interrupt Priority Register (8Bit wide) n 0x1815 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[70] Interrupt Priority Register (8Bit wide) n 0xE1B5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[71] Interrupt Priority Register (8Bit wide) n 0xE4FC 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[72] Interrupt Priority Register (8Bit wide) n 0xE844 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[73] Interrupt Priority Register (8Bit wide) n 0xEB8D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[74] Interrupt Priority Register (8Bit wide) n 0xEED7 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[75] Interrupt Priority Register (8Bit wide) n 0xF222 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[76] Interrupt Priority Register (8Bit wide) n 0xF56E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[77] Interrupt Priority Register (8Bit wide) n 0xF8BB 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[78] Interrupt Priority Register (8Bit wide) n 0xFC09 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[79] Interrupt Priority Register (8Bit wide) n 0xFF58 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[7] Interrupt Priority Register (8Bit wide) n 0x1B1C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[80] Interrupt Priority Register (8Bit wide) n 0x102A8 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[81] Interrupt Priority Register (8Bit wide) n 0x105F9 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[82] Interrupt Priority Register (8Bit wide) n 0x1094B 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[83] Interrupt Priority Register (8Bit wide) n 0x10C9E 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[84] Interrupt Priority Register (8Bit wide) n 0x10FF2 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[85] Interrupt Priority Register (8Bit wide) n 0x11347 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[86] Interrupt Priority Register (8Bit wide) n 0x1169D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[87] Interrupt Priority Register (8Bit wide) n 0x119F4 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[88] Interrupt Priority Register (8Bit wide) n 0x11D4C 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[89] Interrupt Priority Register (8Bit wide) n 0x120A5 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[8] Interrupt Priority Register (8Bit wide) n 0x1E24 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[90] Interrupt Priority Register (8Bit wide) n 0x123FF 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[91] Interrupt Priority Register (8Bit wide) n 0x1275A 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[92] Interrupt Priority Register (8Bit wide) n 0x12AB6 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[93] Interrupt Priority Register (8Bit wide) n 0x12E13 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[94] Interrupt Priority Register (8Bit wide) n 0x13171 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[95] Interrupt Priority Register (8Bit wide) n 0x134D0 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[96] Interrupt Priority Register (8Bit wide) n 0x13830 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[97] Interrupt Priority Register (8Bit wide) n 0x13B91 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[98] Interrupt Priority Register (8Bit wide) n 0x13EF3 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[99] Interrupt Priority Register (8Bit wide) n 0x14256 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 IP[9] Interrupt Priority Register (8Bit wide) n 0x212D 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 ISER[0] Interrupt Set Enable Register n 0x0 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[1] Interrupt Set Enable Register n 0x4 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[2] Interrupt Set Enable Register n 0xC 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[3] Interrupt Set Enable Register n 0x18 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[4] Interrupt Set Enable Register n 0x28 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[5] Interrupt Set Enable Register n 0x3C 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[6] Interrupt Set Enable Register n 0x54 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISER[7] Interrupt Set Enable Register n 0x70 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 ISPR[0] Interrupt Set Pending Register n 0x200 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[1] Interrupt Set Pending Register n 0x304 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[2] Interrupt Set Pending Register n 0x40C 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[3] Interrupt Set Pending Register n 0x518 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[4] Interrupt Set Pending Register n 0x628 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[5] Interrupt Set Pending Register n 0x73C 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[6] Interrupt Set Pending Register n 0x854 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 ISPR[7] Interrupt Set Pending Register n 0x970 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 STIR Software Trigger Interrupt Register 0xE00 32 write-only n 0x0 0x0 INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 PIOA Parallel Input/Output Controller A PIO 0x0 0x0 0x200 registers n PIOA 10 ABCDSR0 Peripheral Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 P0 IO Line Index 0 1 read-only P1 IO Line Index 1 1 read-only P10 IO Line Index 10 1 read-only P11 IO Line Index 11 1 read-only P12 IO Line Index 12 1 read-only P13 IO Line Index 13 1 read-only P14 IO Line Index 14 1 read-only P15 IO Line Index 15 1 read-only P16 IO Line Index 16 1 read-only P17 IO Line Index 17 1 read-only P18 IO Line Index 18 1 read-only P19 IO Line Index 19 1 read-only P2 IO Line Index 2 1 read-only P20 IO Line Index 20 1 read-only P21 IO Line Index 21 1 read-only P22 IO Line Index 22 1 read-only P23 IO Line Index 23 1 read-only P24 IO Line Index 24 1 read-only P25 IO Line Index 25 1 read-only P26 IO Line Index 26 1 read-only P27 IO Line Index 27 1 read-only P28 IO Line Index 28 1 read-only P29 IO Line Index 29 1 read-only P3 IO Line Index 3 1 read-only P30 IO Line Index 30 1 read-only P31 IO Line Index 31 1 read-only P4 IO Line Index 4 1 read-only P5 IO Line Index 5 1 read-only P6 IO Line Index 6 1 read-only P7 IO Line Index 7 1 read-only P8 IO Line Index 8 1 read-only P9 IO Line Index 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DRIVER I/O Drive Register 0x118 32 read-write n 0x0 LINE0 Drive of PIO Line 0 0 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n P0 Peripheral Clock Glitch Filtering Select 0 1 write-only P1 Peripheral Clock Glitch Filtering Select 1 1 write-only P10 Peripheral Clock Glitch Filtering Select 10 1 write-only P11 Peripheral Clock Glitch Filtering Select 11 1 write-only P12 Peripheral Clock Glitch Filtering Select 12 1 write-only P13 Peripheral Clock Glitch Filtering Select 13 1 write-only P14 Peripheral Clock Glitch Filtering Select 14 1 write-only P15 Peripheral Clock Glitch Filtering Select 15 1 write-only P16 Peripheral Clock Glitch Filtering Select 16 1 write-only P17 Peripheral Clock Glitch Filtering Select 17 1 write-only P18 Peripheral Clock Glitch Filtering Select 18 1 write-only P19 Peripheral Clock Glitch Filtering Select 19 1 write-only P2 Peripheral Clock Glitch Filtering Select 2 1 write-only P20 Peripheral Clock Glitch Filtering Select 20 1 write-only P21 Peripheral Clock Glitch Filtering Select 21 1 write-only P22 Peripheral Clock Glitch Filtering Select 22 1 write-only P23 Peripheral Clock Glitch Filtering Select 23 1 write-only P24 Peripheral Clock Glitch Filtering Select 24 1 write-only P25 Peripheral Clock Glitch Filtering Select 25 1 write-only P26 Peripheral Clock Glitch Filtering Select 26 1 write-only P27 Peripheral Clock Glitch Filtering Select 27 1 write-only P28 Peripheral Clock Glitch Filtering Select 28 1 write-only P29 Peripheral Clock Glitch Filtering Select 29 1 write-only P3 Peripheral Clock Glitch Filtering Select 3 1 write-only P30 Peripheral Clock Glitch Filtering Select 30 1 write-only P31 Peripheral Clock Glitch Filtering Select 31 1 write-only P4 Peripheral Clock Glitch Filtering Select 4 1 write-only P5 Peripheral Clock Glitch Filtering Select 5 1 write-only P6 Peripheral Clock Glitch Filtering Select 6 1 write-only P7 Peripheral Clock Glitch Filtering Select 7 1 write-only P8 Peripheral Clock Glitch Filtering Select 8 1 write-only P9 Peripheral Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n P0 Slow Clock Debouncing Filtering Select 0 1 write-only P1 Slow Clock Debouncing Filtering Select 1 1 write-only P10 Slow Clock Debouncing Filtering Select 10 1 write-only P11 Slow Clock Debouncing Filtering Select 11 1 write-only P12 Slow Clock Debouncing Filtering Select 12 1 write-only P13 Slow Clock Debouncing Filtering Select 13 1 write-only P14 Slow Clock Debouncing Filtering Select 14 1 write-only P15 Slow Clock Debouncing Filtering Select 15 1 write-only P16 Slow Clock Debouncing Filtering Select 16 1 write-only P17 Slow Clock Debouncing Filtering Select 17 1 write-only P18 Slow Clock Debouncing Filtering Select 18 1 write-only P19 Slow Clock Debouncing Filtering Select 19 1 write-only P2 Slow Clock Debouncing Filtering Select 2 1 write-only P20 Slow Clock Debouncing Filtering Select 20 1 write-only P21 Slow Clock Debouncing Filtering Select 21 1 write-only P22 Slow Clock Debouncing Filtering Select 22 1 write-only P23 Slow Clock Debouncing Filtering Select 23 1 write-only P24 Slow Clock Debouncing Filtering Select 24 1 write-only P25 Slow Clock Debouncing Filtering Select 25 1 write-only P26 Slow Clock Debouncing Filtering Select 26 1 write-only P27 Slow Clock Debouncing Filtering Select 27 1 write-only P28 Slow Clock Debouncing Filtering Select 28 1 write-only P29 Slow Clock Debouncing Filtering Select 29 1 write-only P3 Slow Clock Debouncing Filtering Select 3 1 write-only P30 Slow Clock Debouncing Filtering Select 30 1 write-only P31 Slow Clock Debouncing Filtering Select 31 1 write-only P4 Slow Clock Debouncing Filtering Select 4 1 write-only P5 Slow Clock Debouncing Filtering Select 5 1 write-only P6 Slow Clock Debouncing Filtering Select 6 1 write-only P7 Slow Clock Debouncing Filtering Select 7 1 write-only P8 Slow Clock Debouncing Filtering Select 8 1 write-only P9 Slow Clock Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 P0 Input Filter Status 0 1 read-only P1 Input Filter Status 1 1 read-only P10 Input Filter Status 10 1 read-only P11 Input Filter Status 11 1 read-only P12 Input Filter Status 12 1 read-only P13 Input Filter Status 13 1 read-only P14 Input Filter Status 14 1 read-only P15 Input Filter Status 15 1 read-only P16 Input Filter Status 16 1 read-only P17 Input Filter Status 17 1 read-only P18 Input Filter Status 18 1 read-only P19 Input Filter Status 19 1 read-only P2 Input Filter Status 2 1 read-only P20 Input Filter Status 20 1 read-only P21 Input Filter Status 21 1 read-only P22 Input Filter Status 22 1 read-only P23 Input Filter Status 23 1 read-only P24 Input Filter Status 24 1 read-only P25 Input Filter Status 25 1 read-only P26 Input Filter Status 26 1 read-only P27 Input Filter Status 27 1 read-only P28 Input Filter Status 28 1 read-only P29 Input Filter Status 29 1 read-only P3 Input Filter Status 3 1 read-only P30 Input Filter Status 30 1 read-only P31 Input Filter Status 31 1 read-only P4 Input Filter Status 4 1 read-only P5 Input Filter Status 5 1 read-only P6 Input Filter Status 6 1 read-only P7 Input Filter Status 7 1 read-only P8 Input Filter Status 8 1 read-only P9 Input Filter Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LOCKSR Lock Status 0xE0 32 read-only n 0x0 P0 Lock Status 0 1 read-only P1 Lock Status 1 1 read-only P10 Lock Status 10 1 read-only P11 Lock Status 11 1 read-only P12 Lock Status 12 1 read-only P13 Lock Status 13 1 read-only P14 Lock Status 14 1 read-only P15 Lock Status 15 1 read-only P16 Lock Status 16 1 read-only P17 Lock Status 17 1 read-only P18 Lock Status 18 1 read-only P19 Lock Status 19 1 read-only P2 Lock Status 2 1 read-only P20 Lock Status 20 1 read-only P21 Lock Status 21 1 read-only P22 Lock Status 22 1 read-only P23 Lock Status 23 1 read-only P24 Lock Status 24 1 read-only P25 Lock Status 25 1 read-only P26 Lock Status 26 1 read-only P27 Lock Status 27 1 read-only P28 Lock Status 28 1 read-only P29 Lock Status 29 1 read-only P3 Lock Status 3 1 read-only P30 Lock Status 30 1 read-only P31 Lock Status 31 1 read-only P4 Lock Status 4 1 read-only P5 Lock Status 5 1 read-only P6 Lock Status 6 1 read-only P7 Lock Status 7 1 read-only P8 Lock Status 8 1 read-only P9 Lock Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n P0 Multi-drive Disable 0 1 write-only P1 Multi-drive Disable 1 1 write-only P10 Multi-drive Disable 10 1 write-only P11 Multi-drive Disable 11 1 write-only P12 Multi-drive Disable 12 1 write-only P13 Multi-drive Disable 13 1 write-only P14 Multi-drive Disable 14 1 write-only P15 Multi-drive Disable 15 1 write-only P16 Multi-drive Disable 16 1 write-only P17 Multi-drive Disable 17 1 write-only P18 Multi-drive Disable 18 1 write-only P19 Multi-drive Disable 19 1 write-only P2 Multi-drive Disable 2 1 write-only P20 Multi-drive Disable 20 1 write-only P21 Multi-drive Disable 21 1 write-only P22 Multi-drive Disable 22 1 write-only P23 Multi-drive Disable 23 1 write-only P24 Multi-drive Disable 24 1 write-only P25 Multi-drive Disable 25 1 write-only P26 Multi-drive Disable 26 1 write-only P27 Multi-drive Disable 27 1 write-only P28 Multi-drive Disable 28 1 write-only P29 Multi-drive Disable 29 1 write-only P3 Multi-drive Disable 3 1 write-only P30 Multi-drive Disable 30 1 write-only P31 Multi-drive Disable 31 1 write-only P4 Multi-drive Disable 4 1 write-only P5 Multi-drive Disable 5 1 write-only P6 Multi-drive Disable 6 1 write-only P7 Multi-drive Disable 7 1 write-only P8 Multi-drive Disable 8 1 write-only P9 Multi-drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n P0 Multi-drive Enable 0 1 write-only P1 Multi-drive Enable 1 1 write-only P10 Multi-drive Enable 10 1 write-only P11 Multi-drive Enable 11 1 write-only P12 Multi-drive Enable 12 1 write-only P13 Multi-drive Enable 13 1 write-only P14 Multi-drive Enable 14 1 write-only P15 Multi-drive Enable 15 1 write-only P16 Multi-drive Enable 16 1 write-only P17 Multi-drive Enable 17 1 write-only P18 Multi-drive Enable 18 1 write-only P19 Multi-drive Enable 19 1 write-only P2 Multi-drive Enable 2 1 write-only P20 Multi-drive Enable 20 1 write-only P21 Multi-drive Enable 21 1 write-only P22 Multi-drive Enable 22 1 write-only P23 Multi-drive Enable 23 1 write-only P24 Multi-drive Enable 24 1 write-only P25 Multi-drive Enable 25 1 write-only P26 Multi-drive Enable 26 1 write-only P27 Multi-drive Enable 27 1 write-only P28 Multi-drive Enable 28 1 write-only P29 Multi-drive Enable 29 1 write-only P3 Multi-drive Enable 3 1 write-only P30 Multi-drive Enable 30 1 write-only P31 Multi-drive Enable 31 1 write-only P4 Multi-drive Enable 4 1 write-only P5 Multi-drive Enable 5 1 write-only P6 Multi-drive Enable 6 1 write-only P7 Multi-drive Enable 7 1 write-only P8 Multi-drive Enable 8 1 write-only P9 Multi-drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 P0 Multi-drive Status 0 1 read-only P1 Multi-drive Status 1 1 read-only P10 Multi-drive Status 10 1 read-only P11 Multi-drive Status 11 1 read-only P12 Multi-drive Status 12 1 read-only P13 Multi-drive Status 13 1 read-only P14 Multi-drive Status 14 1 read-only P15 Multi-drive Status 15 1 read-only P16 Multi-drive Status 16 1 read-only P17 Multi-drive Status 17 1 read-only P18 Multi-drive Status 18 1 read-only P19 Multi-drive Status 19 1 read-only P2 Multi-drive Status 2 1 read-only P20 Multi-drive Status 20 1 read-only P21 Multi-drive Status 21 1 read-only P22 Multi-drive Status 22 1 read-only P23 Multi-drive Status 23 1 read-only P24 Multi-drive Status 24 1 read-only P25 Multi-drive Status 25 1 read-only P26 Multi-drive Status 26 1 read-only P27 Multi-drive Status 27 1 read-only P28 Multi-drive Status 28 1 read-only P29 Multi-drive Status 29 1 read-only P3 Multi-drive Status 3 1 read-only P30 Multi-drive Status 30 1 read-only P31 Multi-drive Status 31 1 read-only P4 Multi-drive Status 4 1 read-only P5 Multi-drive Status 5 1 read-only P6 Multi-drive Status 6 1 read-only P7 Multi-drive Status 7 1 read-only P8 Multi-drive Status 8 1 read-only P9 Multi-drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 write-only ENDRX End of Reception Transfer Interrupt Disable 2 1 write-only OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 write-only RXBUFF Reception Buffer Full Interrupt Disable 3 1 write-only PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 write-only ENDRX End of Reception Transfer Interrupt Enable 2 1 write-only OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 write-only RXBUFF Reception Buffer Full Interrupt Enable 3 1 write-only PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 read-only ENDRX End of Reception Transfer Interrupt Mask 2 1 read-only OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 read-only RXBUFF Reception Buffer Full Interrupt Mask 3 1 read-only PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 DRDY Parallel Capture Mode Data Ready 0 1 read-only OVRE Parallel Capture Mode Overrun Error 1 1 read-only PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 read-write DSIZE Parallel Capture Mode Data Size 4 2 read-write BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 read-write HALFS Parallel Capture Mode Half Sampling 10 1 read-write PCEN Parallel Capture Mode Enable 0 1 read-write PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 RDATA Parallel Capture Mode Reception Data 0 32 read-only PDR PIO Disable Register 0x4 32 write-only n P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PIO_PIO_ABCDSR[0] Peripheral ABCD Select Register 0 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_PIO_ABCDSR[1] Peripheral ABCD Select Register 0 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_PIO_AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 PIO_PIO_AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 PIO_PIO_AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 PIO_PIO_CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 PIO_PIO_DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 PIO_PIO_ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_PIO_ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 PIO_PIO_FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 PIO_PIO_FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_PIO_IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 PIO_PIO_IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 PIO_PIO_IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 PIO_PIO_IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 PIO_PIO_IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 PIO_PIO_IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 PIO_PIO_IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 PIO_PIO_IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 PIO_PIO_IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 PIO_PIO_ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 PIO_PIO_LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 PIO_PIO_LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 PIO_PIO_MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 PIO_PIO_MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 PIO_PIO_MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 PIO_PIO_ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 PIO_PIO_ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PIO_OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 PIO_PIO_OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 PIO_PIO_OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 PIO_PIO_OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 PIO_PIO_OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PIO_PIO_PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PIO_PIO_PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PIO_PIO_PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PIO_PIO_PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PIO_PIO_PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PIO_PIO_PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PIO_PIO_PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PIO_PIO_PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PIO_PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_PIO_PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PIO_PIO_PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PIO_PIO_PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PIO_PIO_PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PIO_PIO_PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PIO_PIO_PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PIO_PIO_PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 PIO_PIO_REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 PIO_PIO_SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 PIO_PIO_SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 PIO_PIO_SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 PIO_PIO_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5261647 PIO_PIO_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PPDDR Pad Pull-down Disable Register 0x90 32 write-only n P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-down Enable Register 0x94 32 write-only n P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-down Status Register 0x98 32 read-only n P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n P0 Rising Edge/High-Level Interrupt Selection 0 1 write-only P1 Rising Edge/High-Level Interrupt Selection 1 1 write-only P10 Rising Edge/High-Level Interrupt Selection 10 1 write-only P11 Rising Edge/High-Level Interrupt Selection 11 1 write-only P12 Rising Edge/High-Level Interrupt Selection 12 1 write-only P13 Rising Edge/High-Level Interrupt Selection 13 1 write-only P14 Rising Edge/High-Level Interrupt Selection 14 1 write-only P15 Rising Edge/High-Level Interrupt Selection 15 1 write-only P16 Rising Edge/High-Level Interrupt Selection 16 1 write-only P17 Rising Edge/High-Level Interrupt Selection 17 1 write-only P18 Rising Edge/High-Level Interrupt Selection 18 1 write-only P19 Rising Edge/High-Level Interrupt Selection 19 1 write-only P2 Rising Edge/High-Level Interrupt Selection 2 1 write-only P20 Rising Edge/High-Level Interrupt Selection 20 1 write-only P21 Rising Edge/High-Level Interrupt Selection 21 1 write-only P22 Rising Edge/High-Level Interrupt Selection 22 1 write-only P23 Rising Edge/High-Level Interrupt Selection 23 1 write-only P24 Rising Edge/High-Level Interrupt Selection 24 1 write-only P25 Rising Edge/High-Level Interrupt Selection 25 1 write-only P26 Rising Edge/High-Level Interrupt Selection 26 1 write-only P27 Rising Edge/High-Level Interrupt Selection 27 1 write-only P28 Rising Edge/High-Level Interrupt Selection 28 1 write-only P29 Rising Edge/High-Level Interrupt Selection 29 1 write-only P3 Rising Edge/High-Level Interrupt Selection 3 1 write-only P30 Rising Edge/High-Level Interrupt Selection 30 1 write-only P31 Rising Edge/High-Level Interrupt Selection 31 1 write-only P4 Rising Edge/High-Level Interrupt Selection 4 1 write-only P5 Rising Edge/High-Level Interrupt Selection 5 1 write-only P6 Rising Edge/High-Level Interrupt Selection 6 1 write-only P7 Rising Edge/High-Level Interrupt Selection 7 1 write-only P8 Rising Edge/High-Level Interrupt Selection 8 1 write-only P9 Rising Edge/High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIOB Parallel Input/Output Controller B PIO 0x0 0x0 0x200 registers n PIOB 11 ABCDSR0 Peripheral Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 P0 IO Line Index 0 1 read-only P1 IO Line Index 1 1 read-only P10 IO Line Index 10 1 read-only P11 IO Line Index 11 1 read-only P12 IO Line Index 12 1 read-only P13 IO Line Index 13 1 read-only P14 IO Line Index 14 1 read-only P15 IO Line Index 15 1 read-only P16 IO Line Index 16 1 read-only P17 IO Line Index 17 1 read-only P18 IO Line Index 18 1 read-only P19 IO Line Index 19 1 read-only P2 IO Line Index 2 1 read-only P20 IO Line Index 20 1 read-only P21 IO Line Index 21 1 read-only P22 IO Line Index 22 1 read-only P23 IO Line Index 23 1 read-only P24 IO Line Index 24 1 read-only P25 IO Line Index 25 1 read-only P26 IO Line Index 26 1 read-only P27 IO Line Index 27 1 read-only P28 IO Line Index 28 1 read-only P29 IO Line Index 29 1 read-only P3 IO Line Index 3 1 read-only P30 IO Line Index 30 1 read-only P31 IO Line Index 31 1 read-only P4 IO Line Index 4 1 read-only P5 IO Line Index 5 1 read-only P6 IO Line Index 6 1 read-only P7 IO Line Index 7 1 read-only P8 IO Line Index 8 1 read-only P9 IO Line Index 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DRIVER I/O Drive Register 0x118 32 read-write n 0x0 LINE0 Drive of PIO Line 0 0 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n P0 Peripheral Clock Glitch Filtering Select 0 1 write-only P1 Peripheral Clock Glitch Filtering Select 1 1 write-only P10 Peripheral Clock Glitch Filtering Select 10 1 write-only P11 Peripheral Clock Glitch Filtering Select 11 1 write-only P12 Peripheral Clock Glitch Filtering Select 12 1 write-only P13 Peripheral Clock Glitch Filtering Select 13 1 write-only P14 Peripheral Clock Glitch Filtering Select 14 1 write-only P15 Peripheral Clock Glitch Filtering Select 15 1 write-only P16 Peripheral Clock Glitch Filtering Select 16 1 write-only P17 Peripheral Clock Glitch Filtering Select 17 1 write-only P18 Peripheral Clock Glitch Filtering Select 18 1 write-only P19 Peripheral Clock Glitch Filtering Select 19 1 write-only P2 Peripheral Clock Glitch Filtering Select 2 1 write-only P20 Peripheral Clock Glitch Filtering Select 20 1 write-only P21 Peripheral Clock Glitch Filtering Select 21 1 write-only P22 Peripheral Clock Glitch Filtering Select 22 1 write-only P23 Peripheral Clock Glitch Filtering Select 23 1 write-only P24 Peripheral Clock Glitch Filtering Select 24 1 write-only P25 Peripheral Clock Glitch Filtering Select 25 1 write-only P26 Peripheral Clock Glitch Filtering Select 26 1 write-only P27 Peripheral Clock Glitch Filtering Select 27 1 write-only P28 Peripheral Clock Glitch Filtering Select 28 1 write-only P29 Peripheral Clock Glitch Filtering Select 29 1 write-only P3 Peripheral Clock Glitch Filtering Select 3 1 write-only P30 Peripheral Clock Glitch Filtering Select 30 1 write-only P31 Peripheral Clock Glitch Filtering Select 31 1 write-only P4 Peripheral Clock Glitch Filtering Select 4 1 write-only P5 Peripheral Clock Glitch Filtering Select 5 1 write-only P6 Peripheral Clock Glitch Filtering Select 6 1 write-only P7 Peripheral Clock Glitch Filtering Select 7 1 write-only P8 Peripheral Clock Glitch Filtering Select 8 1 write-only P9 Peripheral Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n P0 Slow Clock Debouncing Filtering Select 0 1 write-only P1 Slow Clock Debouncing Filtering Select 1 1 write-only P10 Slow Clock Debouncing Filtering Select 10 1 write-only P11 Slow Clock Debouncing Filtering Select 11 1 write-only P12 Slow Clock Debouncing Filtering Select 12 1 write-only P13 Slow Clock Debouncing Filtering Select 13 1 write-only P14 Slow Clock Debouncing Filtering Select 14 1 write-only P15 Slow Clock Debouncing Filtering Select 15 1 write-only P16 Slow Clock Debouncing Filtering Select 16 1 write-only P17 Slow Clock Debouncing Filtering Select 17 1 write-only P18 Slow Clock Debouncing Filtering Select 18 1 write-only P19 Slow Clock Debouncing Filtering Select 19 1 write-only P2 Slow Clock Debouncing Filtering Select 2 1 write-only P20 Slow Clock Debouncing Filtering Select 20 1 write-only P21 Slow Clock Debouncing Filtering Select 21 1 write-only P22 Slow Clock Debouncing Filtering Select 22 1 write-only P23 Slow Clock Debouncing Filtering Select 23 1 write-only P24 Slow Clock Debouncing Filtering Select 24 1 write-only P25 Slow Clock Debouncing Filtering Select 25 1 write-only P26 Slow Clock Debouncing Filtering Select 26 1 write-only P27 Slow Clock Debouncing Filtering Select 27 1 write-only P28 Slow Clock Debouncing Filtering Select 28 1 write-only P29 Slow Clock Debouncing Filtering Select 29 1 write-only P3 Slow Clock Debouncing Filtering Select 3 1 write-only P30 Slow Clock Debouncing Filtering Select 30 1 write-only P31 Slow Clock Debouncing Filtering Select 31 1 write-only P4 Slow Clock Debouncing Filtering Select 4 1 write-only P5 Slow Clock Debouncing Filtering Select 5 1 write-only P6 Slow Clock Debouncing Filtering Select 6 1 write-only P7 Slow Clock Debouncing Filtering Select 7 1 write-only P8 Slow Clock Debouncing Filtering Select 8 1 write-only P9 Slow Clock Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 P0 Input Filter Status 0 1 read-only P1 Input Filter Status 1 1 read-only P10 Input Filter Status 10 1 read-only P11 Input Filter Status 11 1 read-only P12 Input Filter Status 12 1 read-only P13 Input Filter Status 13 1 read-only P14 Input Filter Status 14 1 read-only P15 Input Filter Status 15 1 read-only P16 Input Filter Status 16 1 read-only P17 Input Filter Status 17 1 read-only P18 Input Filter Status 18 1 read-only P19 Input Filter Status 19 1 read-only P2 Input Filter Status 2 1 read-only P20 Input Filter Status 20 1 read-only P21 Input Filter Status 21 1 read-only P22 Input Filter Status 22 1 read-only P23 Input Filter Status 23 1 read-only P24 Input Filter Status 24 1 read-only P25 Input Filter Status 25 1 read-only P26 Input Filter Status 26 1 read-only P27 Input Filter Status 27 1 read-only P28 Input Filter Status 28 1 read-only P29 Input Filter Status 29 1 read-only P3 Input Filter Status 3 1 read-only P30 Input Filter Status 30 1 read-only P31 Input Filter Status 31 1 read-only P4 Input Filter Status 4 1 read-only P5 Input Filter Status 5 1 read-only P6 Input Filter Status 6 1 read-only P7 Input Filter Status 7 1 read-only P8 Input Filter Status 8 1 read-only P9 Input Filter Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LOCKSR Lock Status 0xE0 32 read-only n 0x0 P0 Lock Status 0 1 read-only P1 Lock Status 1 1 read-only P10 Lock Status 10 1 read-only P11 Lock Status 11 1 read-only P12 Lock Status 12 1 read-only P13 Lock Status 13 1 read-only P14 Lock Status 14 1 read-only P15 Lock Status 15 1 read-only P16 Lock Status 16 1 read-only P17 Lock Status 17 1 read-only P18 Lock Status 18 1 read-only P19 Lock Status 19 1 read-only P2 Lock Status 2 1 read-only P20 Lock Status 20 1 read-only P21 Lock Status 21 1 read-only P22 Lock Status 22 1 read-only P23 Lock Status 23 1 read-only P24 Lock Status 24 1 read-only P25 Lock Status 25 1 read-only P26 Lock Status 26 1 read-only P27 Lock Status 27 1 read-only P28 Lock Status 28 1 read-only P29 Lock Status 29 1 read-only P3 Lock Status 3 1 read-only P30 Lock Status 30 1 read-only P31 Lock Status 31 1 read-only P4 Lock Status 4 1 read-only P5 Lock Status 5 1 read-only P6 Lock Status 6 1 read-only P7 Lock Status 7 1 read-only P8 Lock Status 8 1 read-only P9 Lock Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n P0 Multi-drive Disable 0 1 write-only P1 Multi-drive Disable 1 1 write-only P10 Multi-drive Disable 10 1 write-only P11 Multi-drive Disable 11 1 write-only P12 Multi-drive Disable 12 1 write-only P13 Multi-drive Disable 13 1 write-only P14 Multi-drive Disable 14 1 write-only P15 Multi-drive Disable 15 1 write-only P16 Multi-drive Disable 16 1 write-only P17 Multi-drive Disable 17 1 write-only P18 Multi-drive Disable 18 1 write-only P19 Multi-drive Disable 19 1 write-only P2 Multi-drive Disable 2 1 write-only P20 Multi-drive Disable 20 1 write-only P21 Multi-drive Disable 21 1 write-only P22 Multi-drive Disable 22 1 write-only P23 Multi-drive Disable 23 1 write-only P24 Multi-drive Disable 24 1 write-only P25 Multi-drive Disable 25 1 write-only P26 Multi-drive Disable 26 1 write-only P27 Multi-drive Disable 27 1 write-only P28 Multi-drive Disable 28 1 write-only P29 Multi-drive Disable 29 1 write-only P3 Multi-drive Disable 3 1 write-only P30 Multi-drive Disable 30 1 write-only P31 Multi-drive Disable 31 1 write-only P4 Multi-drive Disable 4 1 write-only P5 Multi-drive Disable 5 1 write-only P6 Multi-drive Disable 6 1 write-only P7 Multi-drive Disable 7 1 write-only P8 Multi-drive Disable 8 1 write-only P9 Multi-drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n P0 Multi-drive Enable 0 1 write-only P1 Multi-drive Enable 1 1 write-only P10 Multi-drive Enable 10 1 write-only P11 Multi-drive Enable 11 1 write-only P12 Multi-drive Enable 12 1 write-only P13 Multi-drive Enable 13 1 write-only P14 Multi-drive Enable 14 1 write-only P15 Multi-drive Enable 15 1 write-only P16 Multi-drive Enable 16 1 write-only P17 Multi-drive Enable 17 1 write-only P18 Multi-drive Enable 18 1 write-only P19 Multi-drive Enable 19 1 write-only P2 Multi-drive Enable 2 1 write-only P20 Multi-drive Enable 20 1 write-only P21 Multi-drive Enable 21 1 write-only P22 Multi-drive Enable 22 1 write-only P23 Multi-drive Enable 23 1 write-only P24 Multi-drive Enable 24 1 write-only P25 Multi-drive Enable 25 1 write-only P26 Multi-drive Enable 26 1 write-only P27 Multi-drive Enable 27 1 write-only P28 Multi-drive Enable 28 1 write-only P29 Multi-drive Enable 29 1 write-only P3 Multi-drive Enable 3 1 write-only P30 Multi-drive Enable 30 1 write-only P31 Multi-drive Enable 31 1 write-only P4 Multi-drive Enable 4 1 write-only P5 Multi-drive Enable 5 1 write-only P6 Multi-drive Enable 6 1 write-only P7 Multi-drive Enable 7 1 write-only P8 Multi-drive Enable 8 1 write-only P9 Multi-drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 P0 Multi-drive Status 0 1 read-only P1 Multi-drive Status 1 1 read-only P10 Multi-drive Status 10 1 read-only P11 Multi-drive Status 11 1 read-only P12 Multi-drive Status 12 1 read-only P13 Multi-drive Status 13 1 read-only P14 Multi-drive Status 14 1 read-only P15 Multi-drive Status 15 1 read-only P16 Multi-drive Status 16 1 read-only P17 Multi-drive Status 17 1 read-only P18 Multi-drive Status 18 1 read-only P19 Multi-drive Status 19 1 read-only P2 Multi-drive Status 2 1 read-only P20 Multi-drive Status 20 1 read-only P21 Multi-drive Status 21 1 read-only P22 Multi-drive Status 22 1 read-only P23 Multi-drive Status 23 1 read-only P24 Multi-drive Status 24 1 read-only P25 Multi-drive Status 25 1 read-only P26 Multi-drive Status 26 1 read-only P27 Multi-drive Status 27 1 read-only P28 Multi-drive Status 28 1 read-only P29 Multi-drive Status 29 1 read-only P3 Multi-drive Status 3 1 read-only P30 Multi-drive Status 30 1 read-only P31 Multi-drive Status 31 1 read-only P4 Multi-drive Status 4 1 read-only P5 Multi-drive Status 5 1 read-only P6 Multi-drive Status 6 1 read-only P7 Multi-drive Status 7 1 read-only P8 Multi-drive Status 8 1 read-only P9 Multi-drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 write-only ENDRX End of Reception Transfer Interrupt Disable 2 1 write-only OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 write-only RXBUFF Reception Buffer Full Interrupt Disable 3 1 write-only PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 write-only ENDRX End of Reception Transfer Interrupt Enable 2 1 write-only OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 write-only RXBUFF Reception Buffer Full Interrupt Enable 3 1 write-only PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 read-only ENDRX End of Reception Transfer Interrupt Mask 2 1 read-only OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 read-only RXBUFF Reception Buffer Full Interrupt Mask 3 1 read-only PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 DRDY Parallel Capture Mode Data Ready 0 1 read-only OVRE Parallel Capture Mode Overrun Error 1 1 read-only PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 read-write DSIZE Parallel Capture Mode Data Size 4 2 read-write BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 read-write HALFS Parallel Capture Mode Half Sampling 10 1 read-write PCEN Parallel Capture Mode Enable 0 1 read-write PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 RDATA Parallel Capture Mode Reception Data 0 32 read-only PDR PIO Disable Register 0x4 32 write-only n P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PIO_PIO_ABCDSR[0] Peripheral ABCD Select Register 0 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_PIO_ABCDSR[1] Peripheral ABCD Select Register 0 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_PIO_AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 PIO_PIO_AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 PIO_PIO_AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 PIO_PIO_CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 PIO_PIO_DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 PIO_PIO_ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_PIO_ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 PIO_PIO_FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 PIO_PIO_FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_PIO_IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 PIO_PIO_IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 PIO_PIO_IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 PIO_PIO_IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 PIO_PIO_IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 PIO_PIO_IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 PIO_PIO_IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 PIO_PIO_IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 PIO_PIO_IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 PIO_PIO_ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 PIO_PIO_LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 PIO_PIO_LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 PIO_PIO_MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 PIO_PIO_MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 PIO_PIO_MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 PIO_PIO_ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 PIO_PIO_ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PIO_OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 PIO_PIO_OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 PIO_PIO_OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 PIO_PIO_OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 PIO_PIO_OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PIO_PIO_PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PIO_PIO_PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PIO_PIO_PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PIO_PIO_PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PIO_PIO_PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PIO_PIO_PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PIO_PIO_PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PIO_PIO_PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PIO_PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_PIO_PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PIO_PIO_PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PIO_PIO_PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PIO_PIO_PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PIO_PIO_PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PIO_PIO_PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PIO_PIO_PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 PIO_PIO_REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 PIO_PIO_SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 PIO_PIO_SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 PIO_PIO_SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 PIO_PIO_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5261647 PIO_PIO_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PPDDR Pad Pull-down Disable Register 0x90 32 write-only n P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-down Enable Register 0x94 32 write-only n P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-down Status Register 0x98 32 read-only n P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n P0 Rising Edge/High-Level Interrupt Selection 0 1 write-only P1 Rising Edge/High-Level Interrupt Selection 1 1 write-only P10 Rising Edge/High-Level Interrupt Selection 10 1 write-only P11 Rising Edge/High-Level Interrupt Selection 11 1 write-only P12 Rising Edge/High-Level Interrupt Selection 12 1 write-only P13 Rising Edge/High-Level Interrupt Selection 13 1 write-only P14 Rising Edge/High-Level Interrupt Selection 14 1 write-only P15 Rising Edge/High-Level Interrupt Selection 15 1 write-only P16 Rising Edge/High-Level Interrupt Selection 16 1 write-only P17 Rising Edge/High-Level Interrupt Selection 17 1 write-only P18 Rising Edge/High-Level Interrupt Selection 18 1 write-only P19 Rising Edge/High-Level Interrupt Selection 19 1 write-only P2 Rising Edge/High-Level Interrupt Selection 2 1 write-only P20 Rising Edge/High-Level Interrupt Selection 20 1 write-only P21 Rising Edge/High-Level Interrupt Selection 21 1 write-only P22 Rising Edge/High-Level Interrupt Selection 22 1 write-only P23 Rising Edge/High-Level Interrupt Selection 23 1 write-only P24 Rising Edge/High-Level Interrupt Selection 24 1 write-only P25 Rising Edge/High-Level Interrupt Selection 25 1 write-only P26 Rising Edge/High-Level Interrupt Selection 26 1 write-only P27 Rising Edge/High-Level Interrupt Selection 27 1 write-only P28 Rising Edge/High-Level Interrupt Selection 28 1 write-only P29 Rising Edge/High-Level Interrupt Selection 29 1 write-only P3 Rising Edge/High-Level Interrupt Selection 3 1 write-only P30 Rising Edge/High-Level Interrupt Selection 30 1 write-only P31 Rising Edge/High-Level Interrupt Selection 31 1 write-only P4 Rising Edge/High-Level Interrupt Selection 4 1 write-only P5 Rising Edge/High-Level Interrupt Selection 5 1 write-only P6 Rising Edge/High-Level Interrupt Selection 6 1 write-only P7 Rising Edge/High-Level Interrupt Selection 7 1 write-only P8 Rising Edge/High-Level Interrupt Selection 8 1 write-only P9 Rising Edge/High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PIOD Parallel Input/Output Controller D PIO 0x0 0x0 0x200 registers n PIOD 16 ABCDSR0 Peripheral Select Register 0x70 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write ABCDSR1 Peripheral Select Register 0x74 32 read-write n P0 Peripheral Select 0 1 read-write P1 Peripheral Select 1 1 read-write P10 Peripheral Select 10 1 read-write P11 Peripheral Select 11 1 read-write P12 Peripheral Select 12 1 read-write P13 Peripheral Select 13 1 read-write P14 Peripheral Select 14 1 read-write P15 Peripheral Select 15 1 read-write P16 Peripheral Select 16 1 read-write P17 Peripheral Select 17 1 read-write P18 Peripheral Select 18 1 read-write P19 Peripheral Select 19 1 read-write P2 Peripheral Select 2 1 read-write P20 Peripheral Select 20 1 read-write P21 Peripheral Select 21 1 read-write P22 Peripheral Select 22 1 read-write P23 Peripheral Select 23 1 read-write P24 Peripheral Select 24 1 read-write P25 Peripheral Select 25 1 read-write P26 Peripheral Select 26 1 read-write P27 Peripheral Select 27 1 read-write P28 Peripheral Select 28 1 read-write P29 Peripheral Select 29 1 read-write P3 Peripheral Select 3 1 read-write P30 Peripheral Select 30 1 read-write P31 Peripheral Select 31 1 read-write P4 Peripheral Select 4 1 read-write P5 Peripheral Select 5 1 read-write P6 Peripheral Select 6 1 read-write P7 Peripheral Select 7 1 read-write P8 Peripheral Select 8 1 read-write P9 Peripheral Select 9 1 read-write AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n P0 Additional Interrupt Modes Disable 0 1 write-only P1 Additional Interrupt Modes Disable 1 1 write-only P10 Additional Interrupt Modes Disable 10 1 write-only P11 Additional Interrupt Modes Disable 11 1 write-only P12 Additional Interrupt Modes Disable 12 1 write-only P13 Additional Interrupt Modes Disable 13 1 write-only P14 Additional Interrupt Modes Disable 14 1 write-only P15 Additional Interrupt Modes Disable 15 1 write-only P16 Additional Interrupt Modes Disable 16 1 write-only P17 Additional Interrupt Modes Disable 17 1 write-only P18 Additional Interrupt Modes Disable 18 1 write-only P19 Additional Interrupt Modes Disable 19 1 write-only P2 Additional Interrupt Modes Disable 2 1 write-only P20 Additional Interrupt Modes Disable 20 1 write-only P21 Additional Interrupt Modes Disable 21 1 write-only P22 Additional Interrupt Modes Disable 22 1 write-only P23 Additional Interrupt Modes Disable 23 1 write-only P24 Additional Interrupt Modes Disable 24 1 write-only P25 Additional Interrupt Modes Disable 25 1 write-only P26 Additional Interrupt Modes Disable 26 1 write-only P27 Additional Interrupt Modes Disable 27 1 write-only P28 Additional Interrupt Modes Disable 28 1 write-only P29 Additional Interrupt Modes Disable 29 1 write-only P3 Additional Interrupt Modes Disable 3 1 write-only P30 Additional Interrupt Modes Disable 30 1 write-only P31 Additional Interrupt Modes Disable 31 1 write-only P4 Additional Interrupt Modes Disable 4 1 write-only P5 Additional Interrupt Modes Disable 5 1 write-only P6 Additional Interrupt Modes Disable 6 1 write-only P7 Additional Interrupt Modes Disable 7 1 write-only P8 Additional Interrupt Modes Disable 8 1 write-only P9 Additional Interrupt Modes Disable 9 1 write-only AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n P0 Additional Interrupt Modes Enable 0 1 write-only P1 Additional Interrupt Modes Enable 1 1 write-only P10 Additional Interrupt Modes Enable 10 1 write-only P11 Additional Interrupt Modes Enable 11 1 write-only P12 Additional Interrupt Modes Enable 12 1 write-only P13 Additional Interrupt Modes Enable 13 1 write-only P14 Additional Interrupt Modes Enable 14 1 write-only P15 Additional Interrupt Modes Enable 15 1 write-only P16 Additional Interrupt Modes Enable 16 1 write-only P17 Additional Interrupt Modes Enable 17 1 write-only P18 Additional Interrupt Modes Enable 18 1 write-only P19 Additional Interrupt Modes Enable 19 1 write-only P2 Additional Interrupt Modes Enable 2 1 write-only P20 Additional Interrupt Modes Enable 20 1 write-only P21 Additional Interrupt Modes Enable 21 1 write-only P22 Additional Interrupt Modes Enable 22 1 write-only P23 Additional Interrupt Modes Enable 23 1 write-only P24 Additional Interrupt Modes Enable 24 1 write-only P25 Additional Interrupt Modes Enable 25 1 write-only P26 Additional Interrupt Modes Enable 26 1 write-only P27 Additional Interrupt Modes Enable 27 1 write-only P28 Additional Interrupt Modes Enable 28 1 write-only P29 Additional Interrupt Modes Enable 29 1 write-only P3 Additional Interrupt Modes Enable 3 1 write-only P30 Additional Interrupt Modes Enable 30 1 write-only P31 Additional Interrupt Modes Enable 31 1 write-only P4 Additional Interrupt Modes Enable 4 1 write-only P5 Additional Interrupt Modes Enable 5 1 write-only P6 Additional Interrupt Modes Enable 6 1 write-only P7 Additional Interrupt Modes Enable 7 1 write-only P8 Additional Interrupt Modes Enable 8 1 write-only P9 Additional Interrupt Modes Enable 9 1 write-only AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 P0 IO Line Index 0 1 read-only P1 IO Line Index 1 1 read-only P10 IO Line Index 10 1 read-only P11 IO Line Index 11 1 read-only P12 IO Line Index 12 1 read-only P13 IO Line Index 13 1 read-only P14 IO Line Index 14 1 read-only P15 IO Line Index 15 1 read-only P16 IO Line Index 16 1 read-only P17 IO Line Index 17 1 read-only P18 IO Line Index 18 1 read-only P19 IO Line Index 19 1 read-only P2 IO Line Index 2 1 read-only P20 IO Line Index 20 1 read-only P21 IO Line Index 21 1 read-only P22 IO Line Index 22 1 read-only P23 IO Line Index 23 1 read-only P24 IO Line Index 24 1 read-only P25 IO Line Index 25 1 read-only P26 IO Line Index 26 1 read-only P27 IO Line Index 27 1 read-only P28 IO Line Index 28 1 read-only P29 IO Line Index 29 1 read-only P3 IO Line Index 3 1 read-only P30 IO Line Index 30 1 read-only P31 IO Line Index 31 1 read-only P4 IO Line Index 4 1 read-only P5 IO Line Index 5 1 read-only P6 IO Line Index 6 1 read-only P7 IO Line Index 7 1 read-only P8 IO Line Index 8 1 read-only P9 IO Line Index 9 1 read-only CODR Clear Output Data Register 0x34 32 write-only n P0 Clear Output Data 0 1 write-only P1 Clear Output Data 1 1 write-only P10 Clear Output Data 10 1 write-only P11 Clear Output Data 11 1 write-only P12 Clear Output Data 12 1 write-only P13 Clear Output Data 13 1 write-only P14 Clear Output Data 14 1 write-only P15 Clear Output Data 15 1 write-only P16 Clear Output Data 16 1 write-only P17 Clear Output Data 17 1 write-only P18 Clear Output Data 18 1 write-only P19 Clear Output Data 19 1 write-only P2 Clear Output Data 2 1 write-only P20 Clear Output Data 20 1 write-only P21 Clear Output Data 21 1 write-only P22 Clear Output Data 22 1 write-only P23 Clear Output Data 23 1 write-only P24 Clear Output Data 24 1 write-only P25 Clear Output Data 25 1 write-only P26 Clear Output Data 26 1 write-only P27 Clear Output Data 27 1 write-only P28 Clear Output Data 28 1 write-only P29 Clear Output Data 29 1 write-only P3 Clear Output Data 3 1 write-only P30 Clear Output Data 30 1 write-only P31 Clear Output Data 31 1 write-only P4 Clear Output Data 4 1 write-only P5 Clear Output Data 5 1 write-only P6 Clear Output Data 6 1 write-only P7 Clear Output Data 7 1 write-only P8 Clear Output Data 8 1 write-only P9 Clear Output Data 9 1 write-only DRIVER I/O Drive Register 0x118 32 read-write n 0x0 LINE0 Drive of PIO Line 0 0 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 read-write LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only ESR Edge Select Register 0xC0 32 write-only n P0 Edge Interrupt Selection 0 1 write-only P1 Edge Interrupt Selection 1 1 write-only P10 Edge Interrupt Selection 10 1 write-only P11 Edge Interrupt Selection 11 1 write-only P12 Edge Interrupt Selection 12 1 write-only P13 Edge Interrupt Selection 13 1 write-only P14 Edge Interrupt Selection 14 1 write-only P15 Edge Interrupt Selection 15 1 write-only P16 Edge Interrupt Selection 16 1 write-only P17 Edge Interrupt Selection 17 1 write-only P18 Edge Interrupt Selection 18 1 write-only P19 Edge Interrupt Selection 19 1 write-only P2 Edge Interrupt Selection 2 1 write-only P20 Edge Interrupt Selection 20 1 write-only P21 Edge Interrupt Selection 21 1 write-only P22 Edge Interrupt Selection 22 1 write-only P23 Edge Interrupt Selection 23 1 write-only P24 Edge Interrupt Selection 24 1 write-only P25 Edge Interrupt Selection 25 1 write-only P26 Edge Interrupt Selection 26 1 write-only P27 Edge Interrupt Selection 27 1 write-only P28 Edge Interrupt Selection 28 1 write-only P29 Edge Interrupt Selection 29 1 write-only P3 Edge Interrupt Selection 3 1 write-only P30 Edge Interrupt Selection 30 1 write-only P31 Edge Interrupt Selection 31 1 write-only P4 Edge Interrupt Selection 4 1 write-only P5 Edge Interrupt Selection 5 1 write-only P6 Edge Interrupt Selection 6 1 write-only P7 Edge Interrupt Selection 7 1 write-only P8 Edge Interrupt Selection 8 1 write-only P9 Edge Interrupt Selection 9 1 write-only FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n P0 Falling Edge/Low-Level Interrupt Selection 0 1 write-only P1 Falling Edge/Low-Level Interrupt Selection 1 1 write-only P10 Falling Edge/Low-Level Interrupt Selection 10 1 write-only P11 Falling Edge/Low-Level Interrupt Selection 11 1 write-only P12 Falling Edge/Low-Level Interrupt Selection 12 1 write-only P13 Falling Edge/Low-Level Interrupt Selection 13 1 write-only P14 Falling Edge/Low-Level Interrupt Selection 14 1 write-only P15 Falling Edge/Low-Level Interrupt Selection 15 1 write-only P16 Falling Edge/Low-Level Interrupt Selection 16 1 write-only P17 Falling Edge/Low-Level Interrupt Selection 17 1 write-only P18 Falling Edge/Low-Level Interrupt Selection 18 1 write-only P19 Falling Edge/Low-Level Interrupt Selection 19 1 write-only P2 Falling Edge/Low-Level Interrupt Selection 2 1 write-only P20 Falling Edge/Low-Level Interrupt Selection 20 1 write-only P21 Falling Edge/Low-Level Interrupt Selection 21 1 write-only P22 Falling Edge/Low-Level Interrupt Selection 22 1 write-only P23 Falling Edge/Low-Level Interrupt Selection 23 1 write-only P24 Falling Edge/Low-Level Interrupt Selection 24 1 write-only P25 Falling Edge/Low-Level Interrupt Selection 25 1 write-only P26 Falling Edge/Low-Level Interrupt Selection 26 1 write-only P27 Falling Edge/Low-Level Interrupt Selection 27 1 write-only P28 Falling Edge/Low-Level Interrupt Selection 28 1 write-only P29 Falling Edge/Low-Level Interrupt Selection 29 1 write-only P3 Falling Edge/Low-Level Interrupt Selection 3 1 write-only P30 Falling Edge/Low-Level Interrupt Selection 30 1 write-only P31 Falling Edge/Low-Level Interrupt Selection 31 1 write-only P4 Falling Edge/Low-Level Interrupt Selection 4 1 write-only P5 Falling Edge/Low-Level Interrupt Selection 5 1 write-only P6 Falling Edge/Low-Level Interrupt Selection 6 1 write-only P7 Falling Edge/Low-Level Interrupt Selection 7 1 write-only P8 Falling Edge/Low-Level Interrupt Selection 8 1 write-only P9 Falling Edge/Low-Level Interrupt Selection 9 1 write-only FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 P0 Edge/Level Interrupt Source Selection 0 1 read-only P1 Edge/Level Interrupt Source Selection 1 1 read-only P10 Edge/Level Interrupt Source Selection 10 1 read-only P11 Edge/Level Interrupt Source Selection 11 1 read-only P12 Edge/Level Interrupt Source Selection 12 1 read-only P13 Edge/Level Interrupt Source Selection 13 1 read-only P14 Edge/Level Interrupt Source Selection 14 1 read-only P15 Edge/Level Interrupt Source Selection 15 1 read-only P16 Edge/Level Interrupt Source Selection 16 1 read-only P17 Edge/Level Interrupt Source Selection 17 1 read-only P18 Edge/Level Interrupt Source Selection 18 1 read-only P19 Edge/Level Interrupt Source Selection 19 1 read-only P2 Edge/Level Interrupt Source Selection 2 1 read-only P20 Edge/Level Interrupt Source Selection 20 1 read-only P21 Edge/Level Interrupt Source Selection 21 1 read-only P22 Edge/Level Interrupt Source Selection 22 1 read-only P23 Edge/Level Interrupt Source Selection 23 1 read-only P24 Edge/Level Interrupt Source Selection 24 1 read-only P25 Edge/Level Interrupt Source Selection 25 1 read-only P26 Edge/Level Interrupt Source Selection 26 1 read-only P27 Edge/Level Interrupt Source Selection 27 1 read-only P28 Edge/Level Interrupt Source Selection 28 1 read-only P29 Edge/Level Interrupt Source Selection 29 1 read-only P3 Edge/Level Interrupt Source Selection 3 1 read-only P30 Edge/Level Interrupt Source Selection 30 1 read-only P31 Edge/Level Interrupt Source Selection 31 1 read-only P4 Edge/Level Interrupt Source Selection 4 1 read-only P5 Edge/Level Interrupt Source Selection 5 1 read-only P6 Edge/Level Interrupt Source Selection 6 1 read-only P7 Edge/Level Interrupt Source Selection 7 1 read-only P8 Edge/Level Interrupt Source Selection 8 1 read-only P9 Edge/Level Interrupt Source Selection 9 1 read-only IDR Interrupt Disable Register 0x44 32 write-only n P0 Input Change Interrupt Disable 0 1 write-only P1 Input Change Interrupt Disable 1 1 write-only P10 Input Change Interrupt Disable 10 1 write-only P11 Input Change Interrupt Disable 11 1 write-only P12 Input Change Interrupt Disable 12 1 write-only P13 Input Change Interrupt Disable 13 1 write-only P14 Input Change Interrupt Disable 14 1 write-only P15 Input Change Interrupt Disable 15 1 write-only P16 Input Change Interrupt Disable 16 1 write-only P17 Input Change Interrupt Disable 17 1 write-only P18 Input Change Interrupt Disable 18 1 write-only P19 Input Change Interrupt Disable 19 1 write-only P2 Input Change Interrupt Disable 2 1 write-only P20 Input Change Interrupt Disable 20 1 write-only P21 Input Change Interrupt Disable 21 1 write-only P22 Input Change Interrupt Disable 22 1 write-only P23 Input Change Interrupt Disable 23 1 write-only P24 Input Change Interrupt Disable 24 1 write-only P25 Input Change Interrupt Disable 25 1 write-only P26 Input Change Interrupt Disable 26 1 write-only P27 Input Change Interrupt Disable 27 1 write-only P28 Input Change Interrupt Disable 28 1 write-only P29 Input Change Interrupt Disable 29 1 write-only P3 Input Change Interrupt Disable 3 1 write-only P30 Input Change Interrupt Disable 30 1 write-only P31 Input Change Interrupt Disable 31 1 write-only P4 Input Change Interrupt Disable 4 1 write-only P5 Input Change Interrupt Disable 5 1 write-only P6 Input Change Interrupt Disable 6 1 write-only P7 Input Change Interrupt Disable 7 1 write-only P8 Input Change Interrupt Disable 8 1 write-only P9 Input Change Interrupt Disable 9 1 write-only IER Interrupt Enable Register 0x40 32 write-only n P0 Input Change Interrupt Enable 0 1 write-only P1 Input Change Interrupt Enable 1 1 write-only P10 Input Change Interrupt Enable 10 1 write-only P11 Input Change Interrupt Enable 11 1 write-only P12 Input Change Interrupt Enable 12 1 write-only P13 Input Change Interrupt Enable 13 1 write-only P14 Input Change Interrupt Enable 14 1 write-only P15 Input Change Interrupt Enable 15 1 write-only P16 Input Change Interrupt Enable 16 1 write-only P17 Input Change Interrupt Enable 17 1 write-only P18 Input Change Interrupt Enable 18 1 write-only P19 Input Change Interrupt Enable 19 1 write-only P2 Input Change Interrupt Enable 2 1 write-only P20 Input Change Interrupt Enable 20 1 write-only P21 Input Change Interrupt Enable 21 1 write-only P22 Input Change Interrupt Enable 22 1 write-only P23 Input Change Interrupt Enable 23 1 write-only P24 Input Change Interrupt Enable 24 1 write-only P25 Input Change Interrupt Enable 25 1 write-only P26 Input Change Interrupt Enable 26 1 write-only P27 Input Change Interrupt Enable 27 1 write-only P28 Input Change Interrupt Enable 28 1 write-only P29 Input Change Interrupt Enable 29 1 write-only P3 Input Change Interrupt Enable 3 1 write-only P30 Input Change Interrupt Enable 30 1 write-only P31 Input Change Interrupt Enable 31 1 write-only P4 Input Change Interrupt Enable 4 1 write-only P5 Input Change Interrupt Enable 5 1 write-only P6 Input Change Interrupt Enable 6 1 write-only P7 Input Change Interrupt Enable 7 1 write-only P8 Input Change Interrupt Enable 8 1 write-only P9 Input Change Interrupt Enable 9 1 write-only IFDR Glitch Input Filter Disable Register 0x24 32 write-only n P0 Input Filter Disable 0 1 write-only P1 Input Filter Disable 1 1 write-only P10 Input Filter Disable 10 1 write-only P11 Input Filter Disable 11 1 write-only P12 Input Filter Disable 12 1 write-only P13 Input Filter Disable 13 1 write-only P14 Input Filter Disable 14 1 write-only P15 Input Filter Disable 15 1 write-only P16 Input Filter Disable 16 1 write-only P17 Input Filter Disable 17 1 write-only P18 Input Filter Disable 18 1 write-only P19 Input Filter Disable 19 1 write-only P2 Input Filter Disable 2 1 write-only P20 Input Filter Disable 20 1 write-only P21 Input Filter Disable 21 1 write-only P22 Input Filter Disable 22 1 write-only P23 Input Filter Disable 23 1 write-only P24 Input Filter Disable 24 1 write-only P25 Input Filter Disable 25 1 write-only P26 Input Filter Disable 26 1 write-only P27 Input Filter Disable 27 1 write-only P28 Input Filter Disable 28 1 write-only P29 Input Filter Disable 29 1 write-only P3 Input Filter Disable 3 1 write-only P30 Input Filter Disable 30 1 write-only P31 Input Filter Disable 31 1 write-only P4 Input Filter Disable 4 1 write-only P5 Input Filter Disable 5 1 write-only P6 Input Filter Disable 6 1 write-only P7 Input Filter Disable 7 1 write-only P8 Input Filter Disable 8 1 write-only P9 Input Filter Disable 9 1 write-only IFER Glitch Input Filter Enable Register 0x20 32 write-only n P0 Input Filter Enable 0 1 write-only P1 Input Filter Enable 1 1 write-only P10 Input Filter Enable 10 1 write-only P11 Input Filter Enable 11 1 write-only P12 Input Filter Enable 12 1 write-only P13 Input Filter Enable 13 1 write-only P14 Input Filter Enable 14 1 write-only P15 Input Filter Enable 15 1 write-only P16 Input Filter Enable 16 1 write-only P17 Input Filter Enable 17 1 write-only P18 Input Filter Enable 18 1 write-only P19 Input Filter Enable 19 1 write-only P2 Input Filter Enable 2 1 write-only P20 Input Filter Enable 20 1 write-only P21 Input Filter Enable 21 1 write-only P22 Input Filter Enable 22 1 write-only P23 Input Filter Enable 23 1 write-only P24 Input Filter Enable 24 1 write-only P25 Input Filter Enable 25 1 write-only P26 Input Filter Enable 26 1 write-only P27 Input Filter Enable 27 1 write-only P28 Input Filter Enable 28 1 write-only P29 Input Filter Enable 29 1 write-only P3 Input Filter Enable 3 1 write-only P30 Input Filter Enable 30 1 write-only P31 Input Filter Enable 31 1 write-only P4 Input Filter Enable 4 1 write-only P5 Input Filter Enable 5 1 write-only P6 Input Filter Enable 6 1 write-only P7 Input Filter Enable 7 1 write-only P8 Input Filter Enable 8 1 write-only P9 Input Filter Enable 9 1 write-only IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n P0 Peripheral Clock Glitch Filtering Select 0 1 write-only P1 Peripheral Clock Glitch Filtering Select 1 1 write-only P10 Peripheral Clock Glitch Filtering Select 10 1 write-only P11 Peripheral Clock Glitch Filtering Select 11 1 write-only P12 Peripheral Clock Glitch Filtering Select 12 1 write-only P13 Peripheral Clock Glitch Filtering Select 13 1 write-only P14 Peripheral Clock Glitch Filtering Select 14 1 write-only P15 Peripheral Clock Glitch Filtering Select 15 1 write-only P16 Peripheral Clock Glitch Filtering Select 16 1 write-only P17 Peripheral Clock Glitch Filtering Select 17 1 write-only P18 Peripheral Clock Glitch Filtering Select 18 1 write-only P19 Peripheral Clock Glitch Filtering Select 19 1 write-only P2 Peripheral Clock Glitch Filtering Select 2 1 write-only P20 Peripheral Clock Glitch Filtering Select 20 1 write-only P21 Peripheral Clock Glitch Filtering Select 21 1 write-only P22 Peripheral Clock Glitch Filtering Select 22 1 write-only P23 Peripheral Clock Glitch Filtering Select 23 1 write-only P24 Peripheral Clock Glitch Filtering Select 24 1 write-only P25 Peripheral Clock Glitch Filtering Select 25 1 write-only P26 Peripheral Clock Glitch Filtering Select 26 1 write-only P27 Peripheral Clock Glitch Filtering Select 27 1 write-only P28 Peripheral Clock Glitch Filtering Select 28 1 write-only P29 Peripheral Clock Glitch Filtering Select 29 1 write-only P3 Peripheral Clock Glitch Filtering Select 3 1 write-only P30 Peripheral Clock Glitch Filtering Select 30 1 write-only P31 Peripheral Clock Glitch Filtering Select 31 1 write-only P4 Peripheral Clock Glitch Filtering Select 4 1 write-only P5 Peripheral Clock Glitch Filtering Select 5 1 write-only P6 Peripheral Clock Glitch Filtering Select 6 1 write-only P7 Peripheral Clock Glitch Filtering Select 7 1 write-only P8 Peripheral Clock Glitch Filtering Select 8 1 write-only P9 Peripheral Clock Glitch Filtering Select 9 1 write-only IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n P0 Slow Clock Debouncing Filtering Select 0 1 write-only P1 Slow Clock Debouncing Filtering Select 1 1 write-only P10 Slow Clock Debouncing Filtering Select 10 1 write-only P11 Slow Clock Debouncing Filtering Select 11 1 write-only P12 Slow Clock Debouncing Filtering Select 12 1 write-only P13 Slow Clock Debouncing Filtering Select 13 1 write-only P14 Slow Clock Debouncing Filtering Select 14 1 write-only P15 Slow Clock Debouncing Filtering Select 15 1 write-only P16 Slow Clock Debouncing Filtering Select 16 1 write-only P17 Slow Clock Debouncing Filtering Select 17 1 write-only P18 Slow Clock Debouncing Filtering Select 18 1 write-only P19 Slow Clock Debouncing Filtering Select 19 1 write-only P2 Slow Clock Debouncing Filtering Select 2 1 write-only P20 Slow Clock Debouncing Filtering Select 20 1 write-only P21 Slow Clock Debouncing Filtering Select 21 1 write-only P22 Slow Clock Debouncing Filtering Select 22 1 write-only P23 Slow Clock Debouncing Filtering Select 23 1 write-only P24 Slow Clock Debouncing Filtering Select 24 1 write-only P25 Slow Clock Debouncing Filtering Select 25 1 write-only P26 Slow Clock Debouncing Filtering Select 26 1 write-only P27 Slow Clock Debouncing Filtering Select 27 1 write-only P28 Slow Clock Debouncing Filtering Select 28 1 write-only P29 Slow Clock Debouncing Filtering Select 29 1 write-only P3 Slow Clock Debouncing Filtering Select 3 1 write-only P30 Slow Clock Debouncing Filtering Select 30 1 write-only P31 Slow Clock Debouncing Filtering Select 31 1 write-only P4 Slow Clock Debouncing Filtering Select 4 1 write-only P5 Slow Clock Debouncing Filtering Select 5 1 write-only P6 Slow Clock Debouncing Filtering Select 6 1 write-only P7 Slow Clock Debouncing Filtering Select 7 1 write-only P8 Slow Clock Debouncing Filtering Select 8 1 write-only P9 Slow Clock Debouncing Filtering Select 9 1 write-only IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 read-only P1 Glitch or Debouncing Filter Selection Status 1 1 read-only P10 Glitch or Debouncing Filter Selection Status 10 1 read-only P11 Glitch or Debouncing Filter Selection Status 11 1 read-only P12 Glitch or Debouncing Filter Selection Status 12 1 read-only P13 Glitch or Debouncing Filter Selection Status 13 1 read-only P14 Glitch or Debouncing Filter Selection Status 14 1 read-only P15 Glitch or Debouncing Filter Selection Status 15 1 read-only P16 Glitch or Debouncing Filter Selection Status 16 1 read-only P17 Glitch or Debouncing Filter Selection Status 17 1 read-only P18 Glitch or Debouncing Filter Selection Status 18 1 read-only P19 Glitch or Debouncing Filter Selection Status 19 1 read-only P2 Glitch or Debouncing Filter Selection Status 2 1 read-only P20 Glitch or Debouncing Filter Selection Status 20 1 read-only P21 Glitch or Debouncing Filter Selection Status 21 1 read-only P22 Glitch or Debouncing Filter Selection Status 22 1 read-only P23 Glitch or Debouncing Filter Selection Status 23 1 read-only P24 Glitch or Debouncing Filter Selection Status 24 1 read-only P25 Glitch or Debouncing Filter Selection Status 25 1 read-only P26 Glitch or Debouncing Filter Selection Status 26 1 read-only P27 Glitch or Debouncing Filter Selection Status 27 1 read-only P28 Glitch or Debouncing Filter Selection Status 28 1 read-only P29 Glitch or Debouncing Filter Selection Status 29 1 read-only P3 Glitch or Debouncing Filter Selection Status 3 1 read-only P30 Glitch or Debouncing Filter Selection Status 30 1 read-only P31 Glitch or Debouncing Filter Selection Status 31 1 read-only P4 Glitch or Debouncing Filter Selection Status 4 1 read-only P5 Glitch or Debouncing Filter Selection Status 5 1 read-only P6 Glitch or Debouncing Filter Selection Status 6 1 read-only P7 Glitch or Debouncing Filter Selection Status 7 1 read-only P8 Glitch or Debouncing Filter Selection Status 8 1 read-only P9 Glitch or Debouncing Filter Selection Status 9 1 read-only IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 P0 Input Filter Status 0 1 read-only P1 Input Filter Status 1 1 read-only P10 Input Filter Status 10 1 read-only P11 Input Filter Status 11 1 read-only P12 Input Filter Status 12 1 read-only P13 Input Filter Status 13 1 read-only P14 Input Filter Status 14 1 read-only P15 Input Filter Status 15 1 read-only P16 Input Filter Status 16 1 read-only P17 Input Filter Status 17 1 read-only P18 Input Filter Status 18 1 read-only P19 Input Filter Status 19 1 read-only P2 Input Filter Status 2 1 read-only P20 Input Filter Status 20 1 read-only P21 Input Filter Status 21 1 read-only P22 Input Filter Status 22 1 read-only P23 Input Filter Status 23 1 read-only P24 Input Filter Status 24 1 read-only P25 Input Filter Status 25 1 read-only P26 Input Filter Status 26 1 read-only P27 Input Filter Status 27 1 read-only P28 Input Filter Status 28 1 read-only P29 Input Filter Status 29 1 read-only P3 Input Filter Status 3 1 read-only P30 Input Filter Status 30 1 read-only P31 Input Filter Status 31 1 read-only P4 Input Filter Status 4 1 read-only P5 Input Filter Status 5 1 read-only P6 Input Filter Status 6 1 read-only P7 Input Filter Status 7 1 read-only P8 Input Filter Status 8 1 read-only P9 Input Filter Status 9 1 read-only IMR Interrupt Mask Register 0x48 32 read-only n 0x0 P0 Input Change Interrupt Mask 0 1 read-only P1 Input Change Interrupt Mask 1 1 read-only P10 Input Change Interrupt Mask 10 1 read-only P11 Input Change Interrupt Mask 11 1 read-only P12 Input Change Interrupt Mask 12 1 read-only P13 Input Change Interrupt Mask 13 1 read-only P14 Input Change Interrupt Mask 14 1 read-only P15 Input Change Interrupt Mask 15 1 read-only P16 Input Change Interrupt Mask 16 1 read-only P17 Input Change Interrupt Mask 17 1 read-only P18 Input Change Interrupt Mask 18 1 read-only P19 Input Change Interrupt Mask 19 1 read-only P2 Input Change Interrupt Mask 2 1 read-only P20 Input Change Interrupt Mask 20 1 read-only P21 Input Change Interrupt Mask 21 1 read-only P22 Input Change Interrupt Mask 22 1 read-only P23 Input Change Interrupt Mask 23 1 read-only P24 Input Change Interrupt Mask 24 1 read-only P25 Input Change Interrupt Mask 25 1 read-only P26 Input Change Interrupt Mask 26 1 read-only P27 Input Change Interrupt Mask 27 1 read-only P28 Input Change Interrupt Mask 28 1 read-only P29 Input Change Interrupt Mask 29 1 read-only P3 Input Change Interrupt Mask 3 1 read-only P30 Input Change Interrupt Mask 30 1 read-only P31 Input Change Interrupt Mask 31 1 read-only P4 Input Change Interrupt Mask 4 1 read-only P5 Input Change Interrupt Mask 5 1 read-only P6 Input Change Interrupt Mask 6 1 read-only P7 Input Change Interrupt Mask 7 1 read-only P8 Input Change Interrupt Mask 8 1 read-only P9 Input Change Interrupt Mask 9 1 read-only ISR Interrupt Status Register 0x4C 32 read-only n 0x0 P0 Input Change Interrupt Status 0 1 read-only P1 Input Change Interrupt Status 1 1 read-only P10 Input Change Interrupt Status 10 1 read-only P11 Input Change Interrupt Status 11 1 read-only P12 Input Change Interrupt Status 12 1 read-only P13 Input Change Interrupt Status 13 1 read-only P14 Input Change Interrupt Status 14 1 read-only P15 Input Change Interrupt Status 15 1 read-only P16 Input Change Interrupt Status 16 1 read-only P17 Input Change Interrupt Status 17 1 read-only P18 Input Change Interrupt Status 18 1 read-only P19 Input Change Interrupt Status 19 1 read-only P2 Input Change Interrupt Status 2 1 read-only P20 Input Change Interrupt Status 20 1 read-only P21 Input Change Interrupt Status 21 1 read-only P22 Input Change Interrupt Status 22 1 read-only P23 Input Change Interrupt Status 23 1 read-only P24 Input Change Interrupt Status 24 1 read-only P25 Input Change Interrupt Status 25 1 read-only P26 Input Change Interrupt Status 26 1 read-only P27 Input Change Interrupt Status 27 1 read-only P28 Input Change Interrupt Status 28 1 read-only P29 Input Change Interrupt Status 29 1 read-only P3 Input Change Interrupt Status 3 1 read-only P30 Input Change Interrupt Status 30 1 read-only P31 Input Change Interrupt Status 31 1 read-only P4 Input Change Interrupt Status 4 1 read-only P5 Input Change Interrupt Status 5 1 read-only P6 Input Change Interrupt Status 6 1 read-only P7 Input Change Interrupt Status 7 1 read-only P8 Input Change Interrupt Status 8 1 read-only P9 Input Change Interrupt Status 9 1 read-only LOCKSR Lock Status 0xE0 32 read-only n 0x0 P0 Lock Status 0 1 read-only P1 Lock Status 1 1 read-only P10 Lock Status 10 1 read-only P11 Lock Status 11 1 read-only P12 Lock Status 12 1 read-only P13 Lock Status 13 1 read-only P14 Lock Status 14 1 read-only P15 Lock Status 15 1 read-only P16 Lock Status 16 1 read-only P17 Lock Status 17 1 read-only P18 Lock Status 18 1 read-only P19 Lock Status 19 1 read-only P2 Lock Status 2 1 read-only P20 Lock Status 20 1 read-only P21 Lock Status 21 1 read-only P22 Lock Status 22 1 read-only P23 Lock Status 23 1 read-only P24 Lock Status 24 1 read-only P25 Lock Status 25 1 read-only P26 Lock Status 26 1 read-only P27 Lock Status 27 1 read-only P28 Lock Status 28 1 read-only P29 Lock Status 29 1 read-only P3 Lock Status 3 1 read-only P30 Lock Status 30 1 read-only P31 Lock Status 31 1 read-only P4 Lock Status 4 1 read-only P5 Lock Status 5 1 read-only P6 Lock Status 6 1 read-only P7 Lock Status 7 1 read-only P8 Lock Status 8 1 read-only P9 Lock Status 9 1 read-only LSR Level Select Register 0xC4 32 write-only n P0 Level Interrupt Selection 0 1 write-only P1 Level Interrupt Selection 1 1 write-only P10 Level Interrupt Selection 10 1 write-only P11 Level Interrupt Selection 11 1 write-only P12 Level Interrupt Selection 12 1 write-only P13 Level Interrupt Selection 13 1 write-only P14 Level Interrupt Selection 14 1 write-only P15 Level Interrupt Selection 15 1 write-only P16 Level Interrupt Selection 16 1 write-only P17 Level Interrupt Selection 17 1 write-only P18 Level Interrupt Selection 18 1 write-only P19 Level Interrupt Selection 19 1 write-only P2 Level Interrupt Selection 2 1 write-only P20 Level Interrupt Selection 20 1 write-only P21 Level Interrupt Selection 21 1 write-only P22 Level Interrupt Selection 22 1 write-only P23 Level Interrupt Selection 23 1 write-only P24 Level Interrupt Selection 24 1 write-only P25 Level Interrupt Selection 25 1 write-only P26 Level Interrupt Selection 26 1 write-only P27 Level Interrupt Selection 27 1 write-only P28 Level Interrupt Selection 28 1 write-only P29 Level Interrupt Selection 29 1 write-only P3 Level Interrupt Selection 3 1 write-only P30 Level Interrupt Selection 30 1 write-only P31 Level Interrupt Selection 31 1 write-only P4 Level Interrupt Selection 4 1 write-only P5 Level Interrupt Selection 5 1 write-only P6 Level Interrupt Selection 6 1 write-only P7 Level Interrupt Selection 7 1 write-only P8 Level Interrupt Selection 8 1 write-only P9 Level Interrupt Selection 9 1 write-only MDDR Multi-driver Disable Register 0x54 32 write-only n P0 Multi-drive Disable 0 1 write-only P1 Multi-drive Disable 1 1 write-only P10 Multi-drive Disable 10 1 write-only P11 Multi-drive Disable 11 1 write-only P12 Multi-drive Disable 12 1 write-only P13 Multi-drive Disable 13 1 write-only P14 Multi-drive Disable 14 1 write-only P15 Multi-drive Disable 15 1 write-only P16 Multi-drive Disable 16 1 write-only P17 Multi-drive Disable 17 1 write-only P18 Multi-drive Disable 18 1 write-only P19 Multi-drive Disable 19 1 write-only P2 Multi-drive Disable 2 1 write-only P20 Multi-drive Disable 20 1 write-only P21 Multi-drive Disable 21 1 write-only P22 Multi-drive Disable 22 1 write-only P23 Multi-drive Disable 23 1 write-only P24 Multi-drive Disable 24 1 write-only P25 Multi-drive Disable 25 1 write-only P26 Multi-drive Disable 26 1 write-only P27 Multi-drive Disable 27 1 write-only P28 Multi-drive Disable 28 1 write-only P29 Multi-drive Disable 29 1 write-only P3 Multi-drive Disable 3 1 write-only P30 Multi-drive Disable 30 1 write-only P31 Multi-drive Disable 31 1 write-only P4 Multi-drive Disable 4 1 write-only P5 Multi-drive Disable 5 1 write-only P6 Multi-drive Disable 6 1 write-only P7 Multi-drive Disable 7 1 write-only P8 Multi-drive Disable 8 1 write-only P9 Multi-drive Disable 9 1 write-only MDER Multi-driver Enable Register 0x50 32 write-only n P0 Multi-drive Enable 0 1 write-only P1 Multi-drive Enable 1 1 write-only P10 Multi-drive Enable 10 1 write-only P11 Multi-drive Enable 11 1 write-only P12 Multi-drive Enable 12 1 write-only P13 Multi-drive Enable 13 1 write-only P14 Multi-drive Enable 14 1 write-only P15 Multi-drive Enable 15 1 write-only P16 Multi-drive Enable 16 1 write-only P17 Multi-drive Enable 17 1 write-only P18 Multi-drive Enable 18 1 write-only P19 Multi-drive Enable 19 1 write-only P2 Multi-drive Enable 2 1 write-only P20 Multi-drive Enable 20 1 write-only P21 Multi-drive Enable 21 1 write-only P22 Multi-drive Enable 22 1 write-only P23 Multi-drive Enable 23 1 write-only P24 Multi-drive Enable 24 1 write-only P25 Multi-drive Enable 25 1 write-only P26 Multi-drive Enable 26 1 write-only P27 Multi-drive Enable 27 1 write-only P28 Multi-drive Enable 28 1 write-only P29 Multi-drive Enable 29 1 write-only P3 Multi-drive Enable 3 1 write-only P30 Multi-drive Enable 30 1 write-only P31 Multi-drive Enable 31 1 write-only P4 Multi-drive Enable 4 1 write-only P5 Multi-drive Enable 5 1 write-only P6 Multi-drive Enable 6 1 write-only P7 Multi-drive Enable 7 1 write-only P8 Multi-drive Enable 8 1 write-only P9 Multi-drive Enable 9 1 write-only MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 P0 Multi-drive Status 0 1 read-only P1 Multi-drive Status 1 1 read-only P10 Multi-drive Status 10 1 read-only P11 Multi-drive Status 11 1 read-only P12 Multi-drive Status 12 1 read-only P13 Multi-drive Status 13 1 read-only P14 Multi-drive Status 14 1 read-only P15 Multi-drive Status 15 1 read-only P16 Multi-drive Status 16 1 read-only P17 Multi-drive Status 17 1 read-only P18 Multi-drive Status 18 1 read-only P19 Multi-drive Status 19 1 read-only P2 Multi-drive Status 2 1 read-only P20 Multi-drive Status 20 1 read-only P21 Multi-drive Status 21 1 read-only P22 Multi-drive Status 22 1 read-only P23 Multi-drive Status 23 1 read-only P24 Multi-drive Status 24 1 read-only P25 Multi-drive Status 25 1 read-only P26 Multi-drive Status 26 1 read-only P27 Multi-drive Status 27 1 read-only P28 Multi-drive Status 28 1 read-only P29 Multi-drive Status 29 1 read-only P3 Multi-drive Status 3 1 read-only P30 Multi-drive Status 30 1 read-only P31 Multi-drive Status 31 1 read-only P4 Multi-drive Status 4 1 read-only P5 Multi-drive Status 5 1 read-only P6 Multi-drive Status 6 1 read-only P7 Multi-drive Status 7 1 read-only P8 Multi-drive Status 8 1 read-only P9 Multi-drive Status 9 1 read-only ODR Output Disable Register 0x14 32 write-only n P0 Output Disable 0 1 write-only P1 Output Disable 1 1 write-only P10 Output Disable 10 1 write-only P11 Output Disable 11 1 write-only P12 Output Disable 12 1 write-only P13 Output Disable 13 1 write-only P14 Output Disable 14 1 write-only P15 Output Disable 15 1 write-only P16 Output Disable 16 1 write-only P17 Output Disable 17 1 write-only P18 Output Disable 18 1 write-only P19 Output Disable 19 1 write-only P2 Output Disable 2 1 write-only P20 Output Disable 20 1 write-only P21 Output Disable 21 1 write-only P22 Output Disable 22 1 write-only P23 Output Disable 23 1 write-only P24 Output Disable 24 1 write-only P25 Output Disable 25 1 write-only P26 Output Disable 26 1 write-only P27 Output Disable 27 1 write-only P28 Output Disable 28 1 write-only P29 Output Disable 29 1 write-only P3 Output Disable 3 1 write-only P30 Output Disable 30 1 write-only P31 Output Disable 31 1 write-only P4 Output Disable 4 1 write-only P5 Output Disable 5 1 write-only P6 Output Disable 6 1 write-only P7 Output Disable 7 1 write-only P8 Output Disable 8 1 write-only P9 Output Disable 9 1 write-only ODSR Output Data Status Register 0x38 32 read-write n P0 Output Data Status 0 1 read-write P1 Output Data Status 1 1 read-write P10 Output Data Status 10 1 read-write P11 Output Data Status 11 1 read-write P12 Output Data Status 12 1 read-write P13 Output Data Status 13 1 read-write P14 Output Data Status 14 1 read-write P15 Output Data Status 15 1 read-write P16 Output Data Status 16 1 read-write P17 Output Data Status 17 1 read-write P18 Output Data Status 18 1 read-write P19 Output Data Status 19 1 read-write P2 Output Data Status 2 1 read-write P20 Output Data Status 20 1 read-write P21 Output Data Status 21 1 read-write P22 Output Data Status 22 1 read-write P23 Output Data Status 23 1 read-write P24 Output Data Status 24 1 read-write P25 Output Data Status 25 1 read-write P26 Output Data Status 26 1 read-write P27 Output Data Status 27 1 read-write P28 Output Data Status 28 1 read-write P29 Output Data Status 29 1 read-write P3 Output Data Status 3 1 read-write P30 Output Data Status 30 1 read-write P31 Output Data Status 31 1 read-write P4 Output Data Status 4 1 read-write P5 Output Data Status 5 1 read-write P6 Output Data Status 6 1 read-write P7 Output Data Status 7 1 read-write P8 Output Data Status 8 1 read-write P9 Output Data Status 9 1 read-write OER Output Enable Register 0x10 32 write-only n P0 Output Enable 0 1 write-only P1 Output Enable 1 1 write-only P10 Output Enable 10 1 write-only P11 Output Enable 11 1 write-only P12 Output Enable 12 1 write-only P13 Output Enable 13 1 write-only P14 Output Enable 14 1 write-only P15 Output Enable 15 1 write-only P16 Output Enable 16 1 write-only P17 Output Enable 17 1 write-only P18 Output Enable 18 1 write-only P19 Output Enable 19 1 write-only P2 Output Enable 2 1 write-only P20 Output Enable 20 1 write-only P21 Output Enable 21 1 write-only P22 Output Enable 22 1 write-only P23 Output Enable 23 1 write-only P24 Output Enable 24 1 write-only P25 Output Enable 25 1 write-only P26 Output Enable 26 1 write-only P27 Output Enable 27 1 write-only P28 Output Enable 28 1 write-only P29 Output Enable 29 1 write-only P3 Output Enable 3 1 write-only P30 Output Enable 30 1 write-only P31 Output Enable 31 1 write-only P4 Output Enable 4 1 write-only P5 Output Enable 5 1 write-only P6 Output Enable 6 1 write-only P7 Output Enable 7 1 write-only P8 Output Enable 8 1 write-only P9 Output Enable 9 1 write-only OSR Output Status Register 0x18 32 read-only n 0x0 P0 Output Status 0 1 read-only P1 Output Status 1 1 read-only P10 Output Status 10 1 read-only P11 Output Status 11 1 read-only P12 Output Status 12 1 read-only P13 Output Status 13 1 read-only P14 Output Status 14 1 read-only P15 Output Status 15 1 read-only P16 Output Status 16 1 read-only P17 Output Status 17 1 read-only P18 Output Status 18 1 read-only P19 Output Status 19 1 read-only P2 Output Status 2 1 read-only P20 Output Status 20 1 read-only P21 Output Status 21 1 read-only P22 Output Status 22 1 read-only P23 Output Status 23 1 read-only P24 Output Status 24 1 read-only P25 Output Status 25 1 read-only P26 Output Status 26 1 read-only P27 Output Status 27 1 read-only P28 Output Status 28 1 read-only P29 Output Status 29 1 read-only P3 Output Status 3 1 read-only P30 Output Status 30 1 read-only P31 Output Status 31 1 read-only P4 Output Status 4 1 read-only P5 Output Status 5 1 read-only P6 Output Status 6 1 read-only P7 Output Status 7 1 read-only P8 Output Status 8 1 read-only P9 Output Status 9 1 read-only OWDR Output Write Disable 0xA4 32 write-only n P0 Output Write Disable 0 1 write-only P1 Output Write Disable 1 1 write-only P10 Output Write Disable 10 1 write-only P11 Output Write Disable 11 1 write-only P12 Output Write Disable 12 1 write-only P13 Output Write Disable 13 1 write-only P14 Output Write Disable 14 1 write-only P15 Output Write Disable 15 1 write-only P16 Output Write Disable 16 1 write-only P17 Output Write Disable 17 1 write-only P18 Output Write Disable 18 1 write-only P19 Output Write Disable 19 1 write-only P2 Output Write Disable 2 1 write-only P20 Output Write Disable 20 1 write-only P21 Output Write Disable 21 1 write-only P22 Output Write Disable 22 1 write-only P23 Output Write Disable 23 1 write-only P24 Output Write Disable 24 1 write-only P25 Output Write Disable 25 1 write-only P26 Output Write Disable 26 1 write-only P27 Output Write Disable 27 1 write-only P28 Output Write Disable 28 1 write-only P29 Output Write Disable 29 1 write-only P3 Output Write Disable 3 1 write-only P30 Output Write Disable 30 1 write-only P31 Output Write Disable 31 1 write-only P4 Output Write Disable 4 1 write-only P5 Output Write Disable 5 1 write-only P6 Output Write Disable 6 1 write-only P7 Output Write Disable 7 1 write-only P8 Output Write Disable 8 1 write-only P9 Output Write Disable 9 1 write-only OWER Output Write Enable 0xA0 32 write-only n P0 Output Write Enable 0 1 write-only P1 Output Write Enable 1 1 write-only P10 Output Write Enable 10 1 write-only P11 Output Write Enable 11 1 write-only P12 Output Write Enable 12 1 write-only P13 Output Write Enable 13 1 write-only P14 Output Write Enable 14 1 write-only P15 Output Write Enable 15 1 write-only P16 Output Write Enable 16 1 write-only P17 Output Write Enable 17 1 write-only P18 Output Write Enable 18 1 write-only P19 Output Write Enable 19 1 write-only P2 Output Write Enable 2 1 write-only P20 Output Write Enable 20 1 write-only P21 Output Write Enable 21 1 write-only P22 Output Write Enable 22 1 write-only P23 Output Write Enable 23 1 write-only P24 Output Write Enable 24 1 write-only P25 Output Write Enable 25 1 write-only P26 Output Write Enable 26 1 write-only P27 Output Write Enable 27 1 write-only P28 Output Write Enable 28 1 write-only P29 Output Write Enable 29 1 write-only P3 Output Write Enable 3 1 write-only P30 Output Write Enable 30 1 write-only P31 Output Write Enable 31 1 write-only P4 Output Write Enable 4 1 write-only P5 Output Write Enable 5 1 write-only P6 Output Write Enable 6 1 write-only P7 Output Write Enable 7 1 write-only P8 Output Write Enable 8 1 write-only P9 Output Write Enable 9 1 write-only OWSR Output Write Status Register 0xA8 32 read-only n 0x0 P0 Output Write Status 0 1 read-only P1 Output Write Status 1 1 read-only P10 Output Write Status 10 1 read-only P11 Output Write Status 11 1 read-only P12 Output Write Status 12 1 read-only P13 Output Write Status 13 1 read-only P14 Output Write Status 14 1 read-only P15 Output Write Status 15 1 read-only P16 Output Write Status 16 1 read-only P17 Output Write Status 17 1 read-only P18 Output Write Status 18 1 read-only P19 Output Write Status 19 1 read-only P2 Output Write Status 2 1 read-only P20 Output Write Status 20 1 read-only P21 Output Write Status 21 1 read-only P22 Output Write Status 22 1 read-only P23 Output Write Status 23 1 read-only P24 Output Write Status 24 1 read-only P25 Output Write Status 25 1 read-only P26 Output Write Status 26 1 read-only P27 Output Write Status 27 1 read-only P28 Output Write Status 28 1 read-only P29 Output Write Status 29 1 read-only P3 Output Write Status 3 1 read-only P30 Output Write Status 30 1 read-only P31 Output Write Status 31 1 read-only P4 Output Write Status 4 1 read-only P5 Output Write Status 5 1 read-only P6 Output Write Status 6 1 read-only P7 Output Write Status 7 1 read-only P8 Output Write Status 8 1 read-only P9 Output Write Status 9 1 read-only PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 write-only ENDRX End of Reception Transfer Interrupt Disable 2 1 write-only OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 write-only RXBUFF Reception Buffer Full Interrupt Disable 3 1 write-only PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 write-only ENDRX End of Reception Transfer Interrupt Enable 2 1 write-only OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 write-only RXBUFF Reception Buffer Full Interrupt Enable 3 1 write-only PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 read-only ENDRX End of Reception Transfer Interrupt Mask 2 1 read-only OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 read-only RXBUFF Reception Buffer Full Interrupt Mask 3 1 read-only PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 DRDY Parallel Capture Mode Data Ready 0 1 read-only OVRE Parallel Capture Mode Overrun Error 1 1 read-only PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 read-write DSIZE Parallel Capture Mode Data Size 4 2 read-write BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0x0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 0x1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 0x2 FRSTS Parallel Capture Mode First Sample 11 1 read-write HALFS Parallel Capture Mode Half Sampling 10 1 read-write PCEN Parallel Capture Mode Enable 0 1 read-write PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 RDATA Parallel Capture Mode Reception Data 0 32 read-only PDR PIO Disable Register 0x4 32 write-only n P0 PIO Disable 0 1 write-only P1 PIO Disable 1 1 write-only P10 PIO Disable 10 1 write-only P11 PIO Disable 11 1 write-only P12 PIO Disable 12 1 write-only P13 PIO Disable 13 1 write-only P14 PIO Disable 14 1 write-only P15 PIO Disable 15 1 write-only P16 PIO Disable 16 1 write-only P17 PIO Disable 17 1 write-only P18 PIO Disable 18 1 write-only P19 PIO Disable 19 1 write-only P2 PIO Disable 2 1 write-only P20 PIO Disable 20 1 write-only P21 PIO Disable 21 1 write-only P22 PIO Disable 22 1 write-only P23 PIO Disable 23 1 write-only P24 PIO Disable 24 1 write-only P25 PIO Disable 25 1 write-only P26 PIO Disable 26 1 write-only P27 PIO Disable 27 1 write-only P28 PIO Disable 28 1 write-only P29 PIO Disable 29 1 write-only P3 PIO Disable 3 1 write-only P30 PIO Disable 30 1 write-only P31 PIO Disable 31 1 write-only P4 PIO Disable 4 1 write-only P5 PIO Disable 5 1 write-only P6 PIO Disable 6 1 write-only P7 PIO Disable 7 1 write-only P8 PIO Disable 8 1 write-only P9 PIO Disable 9 1 write-only PDSR Pin Data Status Register 0x3C 32 read-only n P0 Output Data Status 0 1 read-only P1 Output Data Status 1 1 read-only P10 Output Data Status 10 1 read-only P11 Output Data Status 11 1 read-only P12 Output Data Status 12 1 read-only P13 Output Data Status 13 1 read-only P14 Output Data Status 14 1 read-only P15 Output Data Status 15 1 read-only P16 Output Data Status 16 1 read-only P17 Output Data Status 17 1 read-only P18 Output Data Status 18 1 read-only P19 Output Data Status 19 1 read-only P2 Output Data Status 2 1 read-only P20 Output Data Status 20 1 read-only P21 Output Data Status 21 1 read-only P22 Output Data Status 22 1 read-only P23 Output Data Status 23 1 read-only P24 Output Data Status 24 1 read-only P25 Output Data Status 25 1 read-only P26 Output Data Status 26 1 read-only P27 Output Data Status 27 1 read-only P28 Output Data Status 28 1 read-only P29 Output Data Status 29 1 read-only P3 Output Data Status 3 1 read-only P30 Output Data Status 30 1 read-only P31 Output Data Status 31 1 read-only P4 Output Data Status 4 1 read-only P5 Output Data Status 5 1 read-only P6 Output Data Status 6 1 read-only P7 Output Data Status 7 1 read-only P8 Output Data Status 8 1 read-only P9 Output Data Status 9 1 read-only PER PIO Enable Register 0x0 32 write-only n P0 PIO Enable 0 1 write-only P1 PIO Enable 1 1 write-only P10 PIO Enable 10 1 write-only P11 PIO Enable 11 1 write-only P12 PIO Enable 12 1 write-only P13 PIO Enable 13 1 write-only P14 PIO Enable 14 1 write-only P15 PIO Enable 15 1 write-only P16 PIO Enable 16 1 write-only P17 PIO Enable 17 1 write-only P18 PIO Enable 18 1 write-only P19 PIO Enable 19 1 write-only P2 PIO Enable 2 1 write-only P20 PIO Enable 20 1 write-only P21 PIO Enable 21 1 write-only P22 PIO Enable 22 1 write-only P23 PIO Enable 23 1 write-only P24 PIO Enable 24 1 write-only P25 PIO Enable 25 1 write-only P26 PIO Enable 26 1 write-only P27 PIO Enable 27 1 write-only P28 PIO Enable 28 1 write-only P29 PIO Enable 29 1 write-only P3 PIO Enable 3 1 write-only P30 PIO Enable 30 1 write-only P31 PIO Enable 31 1 write-only P4 PIO Enable 4 1 write-only P5 PIO Enable 5 1 write-only P6 PIO Enable 6 1 write-only P7 PIO Enable 7 1 write-only P8 PIO Enable 8 1 write-only P9 PIO Enable 9 1 write-only PIO_PIO_ABCDSR[0] Peripheral ABCD Select Register 0 0xE0 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_PIO_ABCDSR[1] Peripheral ABCD Select Register 0 0x154 32 read-write n 0x0 0x0 P0 Peripheral Select 0 1 P1 Peripheral Select 1 1 P10 Peripheral Select 10 1 P11 Peripheral Select 11 1 P12 Peripheral Select 12 1 P13 Peripheral Select 13 1 P14 Peripheral Select 14 1 P15 Peripheral Select 15 1 P16 Peripheral Select 16 1 P17 Peripheral Select 17 1 P18 Peripheral Select 18 1 P19 Peripheral Select 19 1 P2 Peripheral Select 2 1 P20 Peripheral Select 20 1 P21 Peripheral Select 21 1 P22 Peripheral Select 22 1 P23 Peripheral Select 23 1 P24 Peripheral Select 24 1 P25 Peripheral Select 25 1 P26 Peripheral Select 26 1 P27 Peripheral Select 27 1 P28 Peripheral Select 28 1 P29 Peripheral Select 29 1 P3 Peripheral Select 3 1 P30 Peripheral Select 30 1 P31 Peripheral Select 31 1 P4 Peripheral Select 4 1 P5 Peripheral Select 5 1 P6 Peripheral Select 6 1 P7 Peripheral Select 7 1 P8 Peripheral Select 8 1 P9 Peripheral Select 9 1 PIO_PIO_AIMDR Additional Interrupt Modes Disable Register 0xB4 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Disable 0 1 P1 Additional Interrupt Modes Disable 1 1 P10 Additional Interrupt Modes Disable 10 1 P11 Additional Interrupt Modes Disable 11 1 P12 Additional Interrupt Modes Disable 12 1 P13 Additional Interrupt Modes Disable 13 1 P14 Additional Interrupt Modes Disable 14 1 P15 Additional Interrupt Modes Disable 15 1 P16 Additional Interrupt Modes Disable 16 1 P17 Additional Interrupt Modes Disable 17 1 P18 Additional Interrupt Modes Disable 18 1 P19 Additional Interrupt Modes Disable 19 1 P2 Additional Interrupt Modes Disable 2 1 P20 Additional Interrupt Modes Disable 20 1 P21 Additional Interrupt Modes Disable 21 1 P22 Additional Interrupt Modes Disable 22 1 P23 Additional Interrupt Modes Disable 23 1 P24 Additional Interrupt Modes Disable 24 1 P25 Additional Interrupt Modes Disable 25 1 P26 Additional Interrupt Modes Disable 26 1 P27 Additional Interrupt Modes Disable 27 1 P28 Additional Interrupt Modes Disable 28 1 P29 Additional Interrupt Modes Disable 29 1 P3 Additional Interrupt Modes Disable 3 1 P30 Additional Interrupt Modes Disable 30 1 P31 Additional Interrupt Modes Disable 31 1 P4 Additional Interrupt Modes Disable 4 1 P5 Additional Interrupt Modes Disable 5 1 P6 Additional Interrupt Modes Disable 6 1 P7 Additional Interrupt Modes Disable 7 1 P8 Additional Interrupt Modes Disable 8 1 P9 Additional Interrupt Modes Disable 9 1 PIO_PIO_AIMER Additional Interrupt Modes Enable Register 0xB0 32 write-only n 0x0 0x0 P0 Additional Interrupt Modes Enable 0 1 P1 Additional Interrupt Modes Enable 1 1 P10 Additional Interrupt Modes Enable 10 1 P11 Additional Interrupt Modes Enable 11 1 P12 Additional Interrupt Modes Enable 12 1 P13 Additional Interrupt Modes Enable 13 1 P14 Additional Interrupt Modes Enable 14 1 P15 Additional Interrupt Modes Enable 15 1 P16 Additional Interrupt Modes Enable 16 1 P17 Additional Interrupt Modes Enable 17 1 P18 Additional Interrupt Modes Enable 18 1 P19 Additional Interrupt Modes Enable 19 1 P2 Additional Interrupt Modes Enable 2 1 P20 Additional Interrupt Modes Enable 20 1 P21 Additional Interrupt Modes Enable 21 1 P22 Additional Interrupt Modes Enable 22 1 P23 Additional Interrupt Modes Enable 23 1 P24 Additional Interrupt Modes Enable 24 1 P25 Additional Interrupt Modes Enable 25 1 P26 Additional Interrupt Modes Enable 26 1 P27 Additional Interrupt Modes Enable 27 1 P28 Additional Interrupt Modes Enable 28 1 P29 Additional Interrupt Modes Enable 29 1 P3 Additional Interrupt Modes Enable 3 1 P30 Additional Interrupt Modes Enable 30 1 P31 Additional Interrupt Modes Enable 31 1 P4 Additional Interrupt Modes Enable 4 1 P5 Additional Interrupt Modes Enable 5 1 P6 Additional Interrupt Modes Enable 6 1 P7 Additional Interrupt Modes Enable 7 1 P8 Additional Interrupt Modes Enable 8 1 P9 Additional Interrupt Modes Enable 9 1 PIO_PIO_AIMMR Additional Interrupt Modes Mask Register 0xB8 32 read-only n 0x0 0x0 P0 IO Line Index 0 1 P1 IO Line Index 1 1 P10 IO Line Index 10 1 P11 IO Line Index 11 1 P12 IO Line Index 12 1 P13 IO Line Index 13 1 P14 IO Line Index 14 1 P15 IO Line Index 15 1 P16 IO Line Index 16 1 P17 IO Line Index 17 1 P18 IO Line Index 18 1 P19 IO Line Index 19 1 P2 IO Line Index 2 1 P20 IO Line Index 20 1 P21 IO Line Index 21 1 P22 IO Line Index 22 1 P23 IO Line Index 23 1 P24 IO Line Index 24 1 P25 IO Line Index 25 1 P26 IO Line Index 26 1 P27 IO Line Index 27 1 P28 IO Line Index 28 1 P29 IO Line Index 29 1 P3 IO Line Index 3 1 P30 IO Line Index 30 1 P31 IO Line Index 31 1 P4 IO Line Index 4 1 P5 IO Line Index 5 1 P6 IO Line Index 6 1 P7 IO Line Index 7 1 P8 IO Line Index 8 1 P9 IO Line Index 9 1 PIO_PIO_CODR Clear Output Data Register 0x34 32 write-only n 0x0 0x0 P0 Clear Output Data 0 1 P1 Clear Output Data 1 1 P10 Clear Output Data 10 1 P11 Clear Output Data 11 1 P12 Clear Output Data 12 1 P13 Clear Output Data 13 1 P14 Clear Output Data 14 1 P15 Clear Output Data 15 1 P16 Clear Output Data 16 1 P17 Clear Output Data 17 1 P18 Clear Output Data 18 1 P19 Clear Output Data 19 1 P2 Clear Output Data 2 1 P20 Clear Output Data 20 1 P21 Clear Output Data 21 1 P22 Clear Output Data 22 1 P23 Clear Output Data 23 1 P24 Clear Output Data 24 1 P25 Clear Output Data 25 1 P26 Clear Output Data 26 1 P27 Clear Output Data 27 1 P28 Clear Output Data 28 1 P29 Clear Output Data 29 1 P3 Clear Output Data 3 1 P30 Clear Output Data 30 1 P31 Clear Output Data 31 1 P4 Clear Output Data 4 1 P5 Clear Output Data 5 1 P6 Clear Output Data 6 1 P7 Clear Output Data 7 1 P8 Clear Output Data 8 1 P9 Clear Output Data 9 1 PIO_PIO_DRIVER I/O Drive Register 0x118 32 read-write n 0x0 0x0 LINE0 Drive of PIO Line 0 0 1 LINE0Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE1 Drive of PIO Line 1 1 1 LINE1Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE10 Drive of PIO Line 10 10 1 LINE10Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE11 Drive of PIO Line 11 11 1 LINE11Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE12 Drive of PIO Line 12 12 1 LINE12Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE13 Drive of PIO Line 13 13 1 LINE13Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE14 Drive of PIO Line 14 14 1 LINE14Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE15 Drive of PIO Line 15 15 1 LINE15Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE16 Drive of PIO Line 16 16 1 LINE16Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE17 Drive of PIO Line 17 17 1 LINE17Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE18 Drive of PIO Line 18 18 1 LINE18Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE19 Drive of PIO Line 19 19 1 LINE19Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE2 Drive of PIO Line 2 2 1 LINE2Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE20 Drive of PIO Line 20 20 1 LINE20Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE21 Drive of PIO Line 21 21 1 LINE21Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE22 Drive of PIO Line 22 22 1 LINE22Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE23 Drive of PIO Line 23 23 1 LINE23Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE24 Drive of PIO Line 24 24 1 LINE24Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE25 Drive of PIO Line 25 25 1 LINE25Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE26 Drive of PIO Line 26 26 1 LINE26Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE27 Drive of PIO Line 27 27 1 LINE27Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE28 Drive of PIO Line 28 28 1 LINE28Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE29 Drive of PIO Line 29 29 1 LINE29Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE3 Drive of PIO Line 3 3 1 LINE3Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE30 Drive of PIO Line 30 30 1 LINE30Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE31 Drive of PIO Line 31 31 1 LINE31Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE4 Drive of PIO Line 4 4 1 LINE4Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE5 Drive of PIO Line 5 5 1 LINE5Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE6 Drive of PIO Line 6 6 1 LINE6Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE7 Drive of PIO Line 7 7 1 LINE7Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE8 Drive of PIO Line 8 8 1 LINE8Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 LINE9 Drive of PIO Line 9 9 1 LINE9Select LOW_DRIVE Lowest drive 0 HIGH_DRIVE Highest drive 1 PIO_PIO_ELSR Edge/Level Status Register 0xC8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_PIO_ESR Edge Select Register 0xC0 32 write-only n 0x0 0x0 P0 Edge Interrupt Selection 0 1 P1 Edge Interrupt Selection 1 1 P10 Edge Interrupt Selection 10 1 P11 Edge Interrupt Selection 11 1 P12 Edge Interrupt Selection 12 1 P13 Edge Interrupt Selection 13 1 P14 Edge Interrupt Selection 14 1 P15 Edge Interrupt Selection 15 1 P16 Edge Interrupt Selection 16 1 P17 Edge Interrupt Selection 17 1 P18 Edge Interrupt Selection 18 1 P19 Edge Interrupt Selection 19 1 P2 Edge Interrupt Selection 2 1 P20 Edge Interrupt Selection 20 1 P21 Edge Interrupt Selection 21 1 P22 Edge Interrupt Selection 22 1 P23 Edge Interrupt Selection 23 1 P24 Edge Interrupt Selection 24 1 P25 Edge Interrupt Selection 25 1 P26 Edge Interrupt Selection 26 1 P27 Edge Interrupt Selection 27 1 P28 Edge Interrupt Selection 28 1 P29 Edge Interrupt Selection 29 1 P3 Edge Interrupt Selection 3 1 P30 Edge Interrupt Selection 30 1 P31 Edge Interrupt Selection 31 1 P4 Edge Interrupt Selection 4 1 P5 Edge Interrupt Selection 5 1 P6 Edge Interrupt Selection 6 1 P7 Edge Interrupt Selection 7 1 P8 Edge Interrupt Selection 8 1 P9 Edge Interrupt Selection 9 1 PIO_PIO_FELLSR Falling Edge/Low-Level Select Register 0xD0 32 write-only n 0x0 0x0 P0 Falling Edge/Low-Level Interrupt Selection 0 1 P1 Falling Edge/Low-Level Interrupt Selection 1 1 P10 Falling Edge/Low-Level Interrupt Selection 10 1 P11 Falling Edge/Low-Level Interrupt Selection 11 1 P12 Falling Edge/Low-Level Interrupt Selection 12 1 P13 Falling Edge/Low-Level Interrupt Selection 13 1 P14 Falling Edge/Low-Level Interrupt Selection 14 1 P15 Falling Edge/Low-Level Interrupt Selection 15 1 P16 Falling Edge/Low-Level Interrupt Selection 16 1 P17 Falling Edge/Low-Level Interrupt Selection 17 1 P18 Falling Edge/Low-Level Interrupt Selection 18 1 P19 Falling Edge/Low-Level Interrupt Selection 19 1 P2 Falling Edge/Low-Level Interrupt Selection 2 1 P20 Falling Edge/Low-Level Interrupt Selection 20 1 P21 Falling Edge/Low-Level Interrupt Selection 21 1 P22 Falling Edge/Low-Level Interrupt Selection 22 1 P23 Falling Edge/Low-Level Interrupt Selection 23 1 P24 Falling Edge/Low-Level Interrupt Selection 24 1 P25 Falling Edge/Low-Level Interrupt Selection 25 1 P26 Falling Edge/Low-Level Interrupt Selection 26 1 P27 Falling Edge/Low-Level Interrupt Selection 27 1 P28 Falling Edge/Low-Level Interrupt Selection 28 1 P29 Falling Edge/Low-Level Interrupt Selection 29 1 P3 Falling Edge/Low-Level Interrupt Selection 3 1 P30 Falling Edge/Low-Level Interrupt Selection 30 1 P31 Falling Edge/Low-Level Interrupt Selection 31 1 P4 Falling Edge/Low-Level Interrupt Selection 4 1 P5 Falling Edge/Low-Level Interrupt Selection 5 1 P6 Falling Edge/Low-Level Interrupt Selection 6 1 P7 Falling Edge/Low-Level Interrupt Selection 7 1 P8 Falling Edge/Low-Level Interrupt Selection 8 1 P9 Falling Edge/Low-Level Interrupt Selection 9 1 PIO_PIO_FRLHSR Fall/Rise - Low/High Status Register 0xD8 32 read-only n 0x0 0x0 P0 Edge/Level Interrupt Source Selection 0 1 P1 Edge/Level Interrupt Source Selection 1 1 P10 Edge/Level Interrupt Source Selection 10 1 P11 Edge/Level Interrupt Source Selection 11 1 P12 Edge/Level Interrupt Source Selection 12 1 P13 Edge/Level Interrupt Source Selection 13 1 P14 Edge/Level Interrupt Source Selection 14 1 P15 Edge/Level Interrupt Source Selection 15 1 P16 Edge/Level Interrupt Source Selection 16 1 P17 Edge/Level Interrupt Source Selection 17 1 P18 Edge/Level Interrupt Source Selection 18 1 P19 Edge/Level Interrupt Source Selection 19 1 P2 Edge/Level Interrupt Source Selection 2 1 P20 Edge/Level Interrupt Source Selection 20 1 P21 Edge/Level Interrupt Source Selection 21 1 P22 Edge/Level Interrupt Source Selection 22 1 P23 Edge/Level Interrupt Source Selection 23 1 P24 Edge/Level Interrupt Source Selection 24 1 P25 Edge/Level Interrupt Source Selection 25 1 P26 Edge/Level Interrupt Source Selection 26 1 P27 Edge/Level Interrupt Source Selection 27 1 P28 Edge/Level Interrupt Source Selection 28 1 P29 Edge/Level Interrupt Source Selection 29 1 P3 Edge/Level Interrupt Source Selection 3 1 P30 Edge/Level Interrupt Source Selection 30 1 P31 Edge/Level Interrupt Source Selection 31 1 P4 Edge/Level Interrupt Source Selection 4 1 P5 Edge/Level Interrupt Source Selection 5 1 P6 Edge/Level Interrupt Source Selection 6 1 P7 Edge/Level Interrupt Source Selection 7 1 P8 Edge/Level Interrupt Source Selection 8 1 P9 Edge/Level Interrupt Source Selection 9 1 PIO_PIO_IDR Interrupt Disable Register 0x44 32 write-only n 0x0 0x0 P0 Input Change Interrupt Disable 0 1 P1 Input Change Interrupt Disable 1 1 P10 Input Change Interrupt Disable 10 1 P11 Input Change Interrupt Disable 11 1 P12 Input Change Interrupt Disable 12 1 P13 Input Change Interrupt Disable 13 1 P14 Input Change Interrupt Disable 14 1 P15 Input Change Interrupt Disable 15 1 P16 Input Change Interrupt Disable 16 1 P17 Input Change Interrupt Disable 17 1 P18 Input Change Interrupt Disable 18 1 P19 Input Change Interrupt Disable 19 1 P2 Input Change Interrupt Disable 2 1 P20 Input Change Interrupt Disable 20 1 P21 Input Change Interrupt Disable 21 1 P22 Input Change Interrupt Disable 22 1 P23 Input Change Interrupt Disable 23 1 P24 Input Change Interrupt Disable 24 1 P25 Input Change Interrupt Disable 25 1 P26 Input Change Interrupt Disable 26 1 P27 Input Change Interrupt Disable 27 1 P28 Input Change Interrupt Disable 28 1 P29 Input Change Interrupt Disable 29 1 P3 Input Change Interrupt Disable 3 1 P30 Input Change Interrupt Disable 30 1 P31 Input Change Interrupt Disable 31 1 P4 Input Change Interrupt Disable 4 1 P5 Input Change Interrupt Disable 5 1 P6 Input Change Interrupt Disable 6 1 P7 Input Change Interrupt Disable 7 1 P8 Input Change Interrupt Disable 8 1 P9 Input Change Interrupt Disable 9 1 PIO_PIO_IER Interrupt Enable Register 0x40 32 write-only n 0x0 0x0 P0 Input Change Interrupt Enable 0 1 P1 Input Change Interrupt Enable 1 1 P10 Input Change Interrupt Enable 10 1 P11 Input Change Interrupt Enable 11 1 P12 Input Change Interrupt Enable 12 1 P13 Input Change Interrupt Enable 13 1 P14 Input Change Interrupt Enable 14 1 P15 Input Change Interrupt Enable 15 1 P16 Input Change Interrupt Enable 16 1 P17 Input Change Interrupt Enable 17 1 P18 Input Change Interrupt Enable 18 1 P19 Input Change Interrupt Enable 19 1 P2 Input Change Interrupt Enable 2 1 P20 Input Change Interrupt Enable 20 1 P21 Input Change Interrupt Enable 21 1 P22 Input Change Interrupt Enable 22 1 P23 Input Change Interrupt Enable 23 1 P24 Input Change Interrupt Enable 24 1 P25 Input Change Interrupt Enable 25 1 P26 Input Change Interrupt Enable 26 1 P27 Input Change Interrupt Enable 27 1 P28 Input Change Interrupt Enable 28 1 P29 Input Change Interrupt Enable 29 1 P3 Input Change Interrupt Enable 3 1 P30 Input Change Interrupt Enable 30 1 P31 Input Change Interrupt Enable 31 1 P4 Input Change Interrupt Enable 4 1 P5 Input Change Interrupt Enable 5 1 P6 Input Change Interrupt Enable 6 1 P7 Input Change Interrupt Enable 7 1 P8 Input Change Interrupt Enable 8 1 P9 Input Change Interrupt Enable 9 1 PIO_PIO_IFDR Glitch Input Filter Disable Register 0x24 32 write-only n 0x0 0x0 P0 Input Filter Disable 0 1 P1 Input Filter Disable 1 1 P10 Input Filter Disable 10 1 P11 Input Filter Disable 11 1 P12 Input Filter Disable 12 1 P13 Input Filter Disable 13 1 P14 Input Filter Disable 14 1 P15 Input Filter Disable 15 1 P16 Input Filter Disable 16 1 P17 Input Filter Disable 17 1 P18 Input Filter Disable 18 1 P19 Input Filter Disable 19 1 P2 Input Filter Disable 2 1 P20 Input Filter Disable 20 1 P21 Input Filter Disable 21 1 P22 Input Filter Disable 22 1 P23 Input Filter Disable 23 1 P24 Input Filter Disable 24 1 P25 Input Filter Disable 25 1 P26 Input Filter Disable 26 1 P27 Input Filter Disable 27 1 P28 Input Filter Disable 28 1 P29 Input Filter Disable 29 1 P3 Input Filter Disable 3 1 P30 Input Filter Disable 30 1 P31 Input Filter Disable 31 1 P4 Input Filter Disable 4 1 P5 Input Filter Disable 5 1 P6 Input Filter Disable 6 1 P7 Input Filter Disable 7 1 P8 Input Filter Disable 8 1 P9 Input Filter Disable 9 1 PIO_PIO_IFER Glitch Input Filter Enable Register 0x20 32 write-only n 0x0 0x0 P0 Input Filter Enable 0 1 P1 Input Filter Enable 1 1 P10 Input Filter Enable 10 1 P11 Input Filter Enable 11 1 P12 Input Filter Enable 12 1 P13 Input Filter Enable 13 1 P14 Input Filter Enable 14 1 P15 Input Filter Enable 15 1 P16 Input Filter Enable 16 1 P17 Input Filter Enable 17 1 P18 Input Filter Enable 18 1 P19 Input Filter Enable 19 1 P2 Input Filter Enable 2 1 P20 Input Filter Enable 20 1 P21 Input Filter Enable 21 1 P22 Input Filter Enable 22 1 P23 Input Filter Enable 23 1 P24 Input Filter Enable 24 1 P25 Input Filter Enable 25 1 P26 Input Filter Enable 26 1 P27 Input Filter Enable 27 1 P28 Input Filter Enable 28 1 P29 Input Filter Enable 29 1 P3 Input Filter Enable 3 1 P30 Input Filter Enable 30 1 P31 Input Filter Enable 31 1 P4 Input Filter Enable 4 1 P5 Input Filter Enable 5 1 P6 Input Filter Enable 6 1 P7 Input Filter Enable 7 1 P8 Input Filter Enable 8 1 P9 Input Filter Enable 9 1 PIO_PIO_IFSCDR Input Filter Slow Clock Disable Register 0x80 32 write-only n 0x0 0x0 P0 Peripheral Clock Glitch Filtering Select 0 1 P1 Peripheral Clock Glitch Filtering Select 1 1 P10 Peripheral Clock Glitch Filtering Select 10 1 P11 Peripheral Clock Glitch Filtering Select 11 1 P12 Peripheral Clock Glitch Filtering Select 12 1 P13 Peripheral Clock Glitch Filtering Select 13 1 P14 Peripheral Clock Glitch Filtering Select 14 1 P15 Peripheral Clock Glitch Filtering Select 15 1 P16 Peripheral Clock Glitch Filtering Select 16 1 P17 Peripheral Clock Glitch Filtering Select 17 1 P18 Peripheral Clock Glitch Filtering Select 18 1 P19 Peripheral Clock Glitch Filtering Select 19 1 P2 Peripheral Clock Glitch Filtering Select 2 1 P20 Peripheral Clock Glitch Filtering Select 20 1 P21 Peripheral Clock Glitch Filtering Select 21 1 P22 Peripheral Clock Glitch Filtering Select 22 1 P23 Peripheral Clock Glitch Filtering Select 23 1 P24 Peripheral Clock Glitch Filtering Select 24 1 P25 Peripheral Clock Glitch Filtering Select 25 1 P26 Peripheral Clock Glitch Filtering Select 26 1 P27 Peripheral Clock Glitch Filtering Select 27 1 P28 Peripheral Clock Glitch Filtering Select 28 1 P29 Peripheral Clock Glitch Filtering Select 29 1 P3 Peripheral Clock Glitch Filtering Select 3 1 P30 Peripheral Clock Glitch Filtering Select 30 1 P31 Peripheral Clock Glitch Filtering Select 31 1 P4 Peripheral Clock Glitch Filtering Select 4 1 P5 Peripheral Clock Glitch Filtering Select 5 1 P6 Peripheral Clock Glitch Filtering Select 6 1 P7 Peripheral Clock Glitch Filtering Select 7 1 P8 Peripheral Clock Glitch Filtering Select 8 1 P9 Peripheral Clock Glitch Filtering Select 9 1 PIO_PIO_IFSCER Input Filter Slow Clock Enable Register 0x84 32 write-only n 0x0 0x0 P0 Slow Clock Debouncing Filtering Select 0 1 P1 Slow Clock Debouncing Filtering Select 1 1 P10 Slow Clock Debouncing Filtering Select 10 1 P11 Slow Clock Debouncing Filtering Select 11 1 P12 Slow Clock Debouncing Filtering Select 12 1 P13 Slow Clock Debouncing Filtering Select 13 1 P14 Slow Clock Debouncing Filtering Select 14 1 P15 Slow Clock Debouncing Filtering Select 15 1 P16 Slow Clock Debouncing Filtering Select 16 1 P17 Slow Clock Debouncing Filtering Select 17 1 P18 Slow Clock Debouncing Filtering Select 18 1 P19 Slow Clock Debouncing Filtering Select 19 1 P2 Slow Clock Debouncing Filtering Select 2 1 P20 Slow Clock Debouncing Filtering Select 20 1 P21 Slow Clock Debouncing Filtering Select 21 1 P22 Slow Clock Debouncing Filtering Select 22 1 P23 Slow Clock Debouncing Filtering Select 23 1 P24 Slow Clock Debouncing Filtering Select 24 1 P25 Slow Clock Debouncing Filtering Select 25 1 P26 Slow Clock Debouncing Filtering Select 26 1 P27 Slow Clock Debouncing Filtering Select 27 1 P28 Slow Clock Debouncing Filtering Select 28 1 P29 Slow Clock Debouncing Filtering Select 29 1 P3 Slow Clock Debouncing Filtering Select 3 1 P30 Slow Clock Debouncing Filtering Select 30 1 P31 Slow Clock Debouncing Filtering Select 31 1 P4 Slow Clock Debouncing Filtering Select 4 1 P5 Slow Clock Debouncing Filtering Select 5 1 P6 Slow Clock Debouncing Filtering Select 6 1 P7 Slow Clock Debouncing Filtering Select 7 1 P8 Slow Clock Debouncing Filtering Select 8 1 P9 Slow Clock Debouncing Filtering Select 9 1 PIO_PIO_IFSCSR Input Filter Slow Clock Status Register 0x88 32 read-only n 0x0 0x0 P0 Glitch or Debouncing Filter Selection Status 0 1 P1 Glitch or Debouncing Filter Selection Status 1 1 P10 Glitch or Debouncing Filter Selection Status 10 1 P11 Glitch or Debouncing Filter Selection Status 11 1 P12 Glitch or Debouncing Filter Selection Status 12 1 P13 Glitch or Debouncing Filter Selection Status 13 1 P14 Glitch or Debouncing Filter Selection Status 14 1 P15 Glitch or Debouncing Filter Selection Status 15 1 P16 Glitch or Debouncing Filter Selection Status 16 1 P17 Glitch or Debouncing Filter Selection Status 17 1 P18 Glitch or Debouncing Filter Selection Status 18 1 P19 Glitch or Debouncing Filter Selection Status 19 1 P2 Glitch or Debouncing Filter Selection Status 2 1 P20 Glitch or Debouncing Filter Selection Status 20 1 P21 Glitch or Debouncing Filter Selection Status 21 1 P22 Glitch or Debouncing Filter Selection Status 22 1 P23 Glitch or Debouncing Filter Selection Status 23 1 P24 Glitch or Debouncing Filter Selection Status 24 1 P25 Glitch or Debouncing Filter Selection Status 25 1 P26 Glitch or Debouncing Filter Selection Status 26 1 P27 Glitch or Debouncing Filter Selection Status 27 1 P28 Glitch or Debouncing Filter Selection Status 28 1 P29 Glitch or Debouncing Filter Selection Status 29 1 P3 Glitch or Debouncing Filter Selection Status 3 1 P30 Glitch or Debouncing Filter Selection Status 30 1 P31 Glitch or Debouncing Filter Selection Status 31 1 P4 Glitch or Debouncing Filter Selection Status 4 1 P5 Glitch or Debouncing Filter Selection Status 5 1 P6 Glitch or Debouncing Filter Selection Status 6 1 P7 Glitch or Debouncing Filter Selection Status 7 1 P8 Glitch or Debouncing Filter Selection Status 8 1 P9 Glitch or Debouncing Filter Selection Status 9 1 PIO_PIO_IFSR Glitch Input Filter Status Register 0x28 32 read-only n 0x0 0x0 P0 Input Filter Status 0 1 P1 Input Filter Status 1 1 P10 Input Filter Status 10 1 P11 Input Filter Status 11 1 P12 Input Filter Status 12 1 P13 Input Filter Status 13 1 P14 Input Filter Status 14 1 P15 Input Filter Status 15 1 P16 Input Filter Status 16 1 P17 Input Filter Status 17 1 P18 Input Filter Status 18 1 P19 Input Filter Status 19 1 P2 Input Filter Status 2 1 P20 Input Filter Status 20 1 P21 Input Filter Status 21 1 P22 Input Filter Status 22 1 P23 Input Filter Status 23 1 P24 Input Filter Status 24 1 P25 Input Filter Status 25 1 P26 Input Filter Status 26 1 P27 Input Filter Status 27 1 P28 Input Filter Status 28 1 P29 Input Filter Status 29 1 P3 Input Filter Status 3 1 P30 Input Filter Status 30 1 P31 Input Filter Status 31 1 P4 Input Filter Status 4 1 P5 Input Filter Status 5 1 P6 Input Filter Status 6 1 P7 Input Filter Status 7 1 P8 Input Filter Status 8 1 P9 Input Filter Status 9 1 PIO_PIO_IMR Interrupt Mask Register 0x48 32 read-only n 0x0 0x0 P0 Input Change Interrupt Mask 0 1 P1 Input Change Interrupt Mask 1 1 P10 Input Change Interrupt Mask 10 1 P11 Input Change Interrupt Mask 11 1 P12 Input Change Interrupt Mask 12 1 P13 Input Change Interrupt Mask 13 1 P14 Input Change Interrupt Mask 14 1 P15 Input Change Interrupt Mask 15 1 P16 Input Change Interrupt Mask 16 1 P17 Input Change Interrupt Mask 17 1 P18 Input Change Interrupt Mask 18 1 P19 Input Change Interrupt Mask 19 1 P2 Input Change Interrupt Mask 2 1 P20 Input Change Interrupt Mask 20 1 P21 Input Change Interrupt Mask 21 1 P22 Input Change Interrupt Mask 22 1 P23 Input Change Interrupt Mask 23 1 P24 Input Change Interrupt Mask 24 1 P25 Input Change Interrupt Mask 25 1 P26 Input Change Interrupt Mask 26 1 P27 Input Change Interrupt Mask 27 1 P28 Input Change Interrupt Mask 28 1 P29 Input Change Interrupt Mask 29 1 P3 Input Change Interrupt Mask 3 1 P30 Input Change Interrupt Mask 30 1 P31 Input Change Interrupt Mask 31 1 P4 Input Change Interrupt Mask 4 1 P5 Input Change Interrupt Mask 5 1 P6 Input Change Interrupt Mask 6 1 P7 Input Change Interrupt Mask 7 1 P8 Input Change Interrupt Mask 8 1 P9 Input Change Interrupt Mask 9 1 PIO_PIO_ISR Interrupt Status Register 0x4C 32 read-only n 0x0 0x0 P0 Input Change Interrupt Status 0 1 P1 Input Change Interrupt Status 1 1 P10 Input Change Interrupt Status 10 1 P11 Input Change Interrupt Status 11 1 P12 Input Change Interrupt Status 12 1 P13 Input Change Interrupt Status 13 1 P14 Input Change Interrupt Status 14 1 P15 Input Change Interrupt Status 15 1 P16 Input Change Interrupt Status 16 1 P17 Input Change Interrupt Status 17 1 P18 Input Change Interrupt Status 18 1 P19 Input Change Interrupt Status 19 1 P2 Input Change Interrupt Status 2 1 P20 Input Change Interrupt Status 20 1 P21 Input Change Interrupt Status 21 1 P22 Input Change Interrupt Status 22 1 P23 Input Change Interrupt Status 23 1 P24 Input Change Interrupt Status 24 1 P25 Input Change Interrupt Status 25 1 P26 Input Change Interrupt Status 26 1 P27 Input Change Interrupt Status 27 1 P28 Input Change Interrupt Status 28 1 P29 Input Change Interrupt Status 29 1 P3 Input Change Interrupt Status 3 1 P30 Input Change Interrupt Status 30 1 P31 Input Change Interrupt Status 31 1 P4 Input Change Interrupt Status 4 1 P5 Input Change Interrupt Status 5 1 P6 Input Change Interrupt Status 6 1 P7 Input Change Interrupt Status 7 1 P8 Input Change Interrupt Status 8 1 P9 Input Change Interrupt Status 9 1 PIO_PIO_LOCKSR Lock Status 0xE0 32 read-only n 0x0 0x0 P0 Lock Status 0 1 P1 Lock Status 1 1 P10 Lock Status 10 1 P11 Lock Status 11 1 P12 Lock Status 12 1 P13 Lock Status 13 1 P14 Lock Status 14 1 P15 Lock Status 15 1 P16 Lock Status 16 1 P17 Lock Status 17 1 P18 Lock Status 18 1 P19 Lock Status 19 1 P2 Lock Status 2 1 P20 Lock Status 20 1 P21 Lock Status 21 1 P22 Lock Status 22 1 P23 Lock Status 23 1 P24 Lock Status 24 1 P25 Lock Status 25 1 P26 Lock Status 26 1 P27 Lock Status 27 1 P28 Lock Status 28 1 P29 Lock Status 29 1 P3 Lock Status 3 1 P30 Lock Status 30 1 P31 Lock Status 31 1 P4 Lock Status 4 1 P5 Lock Status 5 1 P6 Lock Status 6 1 P7 Lock Status 7 1 P8 Lock Status 8 1 P9 Lock Status 9 1 PIO_PIO_LSR Level Select Register 0xC4 32 write-only n 0x0 0x0 P0 Level Interrupt Selection 0 1 P1 Level Interrupt Selection 1 1 P10 Level Interrupt Selection 10 1 P11 Level Interrupt Selection 11 1 P12 Level Interrupt Selection 12 1 P13 Level Interrupt Selection 13 1 P14 Level Interrupt Selection 14 1 P15 Level Interrupt Selection 15 1 P16 Level Interrupt Selection 16 1 P17 Level Interrupt Selection 17 1 P18 Level Interrupt Selection 18 1 P19 Level Interrupt Selection 19 1 P2 Level Interrupt Selection 2 1 P20 Level Interrupt Selection 20 1 P21 Level Interrupt Selection 21 1 P22 Level Interrupt Selection 22 1 P23 Level Interrupt Selection 23 1 P24 Level Interrupt Selection 24 1 P25 Level Interrupt Selection 25 1 P26 Level Interrupt Selection 26 1 P27 Level Interrupt Selection 27 1 P28 Level Interrupt Selection 28 1 P29 Level Interrupt Selection 29 1 P3 Level Interrupt Selection 3 1 P30 Level Interrupt Selection 30 1 P31 Level Interrupt Selection 31 1 P4 Level Interrupt Selection 4 1 P5 Level Interrupt Selection 5 1 P6 Level Interrupt Selection 6 1 P7 Level Interrupt Selection 7 1 P8 Level Interrupt Selection 8 1 P9 Level Interrupt Selection 9 1 PIO_PIO_MDDR Multi-driver Disable Register 0x54 32 write-only n 0x0 0x0 P0 Multi-drive Disable 0 1 P1 Multi-drive Disable 1 1 P10 Multi-drive Disable 10 1 P11 Multi-drive Disable 11 1 P12 Multi-drive Disable 12 1 P13 Multi-drive Disable 13 1 P14 Multi-drive Disable 14 1 P15 Multi-drive Disable 15 1 P16 Multi-drive Disable 16 1 P17 Multi-drive Disable 17 1 P18 Multi-drive Disable 18 1 P19 Multi-drive Disable 19 1 P2 Multi-drive Disable 2 1 P20 Multi-drive Disable 20 1 P21 Multi-drive Disable 21 1 P22 Multi-drive Disable 22 1 P23 Multi-drive Disable 23 1 P24 Multi-drive Disable 24 1 P25 Multi-drive Disable 25 1 P26 Multi-drive Disable 26 1 P27 Multi-drive Disable 27 1 P28 Multi-drive Disable 28 1 P29 Multi-drive Disable 29 1 P3 Multi-drive Disable 3 1 P30 Multi-drive Disable 30 1 P31 Multi-drive Disable 31 1 P4 Multi-drive Disable 4 1 P5 Multi-drive Disable 5 1 P6 Multi-drive Disable 6 1 P7 Multi-drive Disable 7 1 P8 Multi-drive Disable 8 1 P9 Multi-drive Disable 9 1 PIO_PIO_MDER Multi-driver Enable Register 0x50 32 write-only n 0x0 0x0 P0 Multi-drive Enable 0 1 P1 Multi-drive Enable 1 1 P10 Multi-drive Enable 10 1 P11 Multi-drive Enable 11 1 P12 Multi-drive Enable 12 1 P13 Multi-drive Enable 13 1 P14 Multi-drive Enable 14 1 P15 Multi-drive Enable 15 1 P16 Multi-drive Enable 16 1 P17 Multi-drive Enable 17 1 P18 Multi-drive Enable 18 1 P19 Multi-drive Enable 19 1 P2 Multi-drive Enable 2 1 P20 Multi-drive Enable 20 1 P21 Multi-drive Enable 21 1 P22 Multi-drive Enable 22 1 P23 Multi-drive Enable 23 1 P24 Multi-drive Enable 24 1 P25 Multi-drive Enable 25 1 P26 Multi-drive Enable 26 1 P27 Multi-drive Enable 27 1 P28 Multi-drive Enable 28 1 P29 Multi-drive Enable 29 1 P3 Multi-drive Enable 3 1 P30 Multi-drive Enable 30 1 P31 Multi-drive Enable 31 1 P4 Multi-drive Enable 4 1 P5 Multi-drive Enable 5 1 P6 Multi-drive Enable 6 1 P7 Multi-drive Enable 7 1 P8 Multi-drive Enable 8 1 P9 Multi-drive Enable 9 1 PIO_PIO_MDSR Multi-driver Status Register 0x58 32 read-only n 0x0 0x0 P0 Multi-drive Status 0 1 P1 Multi-drive Status 1 1 P10 Multi-drive Status 10 1 P11 Multi-drive Status 11 1 P12 Multi-drive Status 12 1 P13 Multi-drive Status 13 1 P14 Multi-drive Status 14 1 P15 Multi-drive Status 15 1 P16 Multi-drive Status 16 1 P17 Multi-drive Status 17 1 P18 Multi-drive Status 18 1 P19 Multi-drive Status 19 1 P2 Multi-drive Status 2 1 P20 Multi-drive Status 20 1 P21 Multi-drive Status 21 1 P22 Multi-drive Status 22 1 P23 Multi-drive Status 23 1 P24 Multi-drive Status 24 1 P25 Multi-drive Status 25 1 P26 Multi-drive Status 26 1 P27 Multi-drive Status 27 1 P28 Multi-drive Status 28 1 P29 Multi-drive Status 29 1 P3 Multi-drive Status 3 1 P30 Multi-drive Status 30 1 P31 Multi-drive Status 31 1 P4 Multi-drive Status 4 1 P5 Multi-drive Status 5 1 P6 Multi-drive Status 6 1 P7 Multi-drive Status 7 1 P8 Multi-drive Status 8 1 P9 Multi-drive Status 9 1 PIO_PIO_ODR Output Disable Register 0x14 32 write-only n 0x0 0x0 P0 Output Disable 0 1 P1 Output Disable 1 1 P10 Output Disable 10 1 P11 Output Disable 11 1 P12 Output Disable 12 1 P13 Output Disable 13 1 P14 Output Disable 14 1 P15 Output Disable 15 1 P16 Output Disable 16 1 P17 Output Disable 17 1 P18 Output Disable 18 1 P19 Output Disable 19 1 P2 Output Disable 2 1 P20 Output Disable 20 1 P21 Output Disable 21 1 P22 Output Disable 22 1 P23 Output Disable 23 1 P24 Output Disable 24 1 P25 Output Disable 25 1 P26 Output Disable 26 1 P27 Output Disable 27 1 P28 Output Disable 28 1 P29 Output Disable 29 1 P3 Output Disable 3 1 P30 Output Disable 30 1 P31 Output Disable 31 1 P4 Output Disable 4 1 P5 Output Disable 5 1 P6 Output Disable 6 1 P7 Output Disable 7 1 P8 Output Disable 8 1 P9 Output Disable 9 1 PIO_PIO_ODSR Output Data Status Register 0x38 32 read-write n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PIO_OER Output Enable Register 0x10 32 write-only n 0x0 0x0 P0 Output Enable 0 1 P1 Output Enable 1 1 P10 Output Enable 10 1 P11 Output Enable 11 1 P12 Output Enable 12 1 P13 Output Enable 13 1 P14 Output Enable 14 1 P15 Output Enable 15 1 P16 Output Enable 16 1 P17 Output Enable 17 1 P18 Output Enable 18 1 P19 Output Enable 19 1 P2 Output Enable 2 1 P20 Output Enable 20 1 P21 Output Enable 21 1 P22 Output Enable 22 1 P23 Output Enable 23 1 P24 Output Enable 24 1 P25 Output Enable 25 1 P26 Output Enable 26 1 P27 Output Enable 27 1 P28 Output Enable 28 1 P29 Output Enable 29 1 P3 Output Enable 3 1 P30 Output Enable 30 1 P31 Output Enable 31 1 P4 Output Enable 4 1 P5 Output Enable 5 1 P6 Output Enable 6 1 P7 Output Enable 7 1 P8 Output Enable 8 1 P9 Output Enable 9 1 PIO_PIO_OSR Output Status Register 0x18 32 read-only n 0x0 0x0 P0 Output Status 0 1 P1 Output Status 1 1 P10 Output Status 10 1 P11 Output Status 11 1 P12 Output Status 12 1 P13 Output Status 13 1 P14 Output Status 14 1 P15 Output Status 15 1 P16 Output Status 16 1 P17 Output Status 17 1 P18 Output Status 18 1 P19 Output Status 19 1 P2 Output Status 2 1 P20 Output Status 20 1 P21 Output Status 21 1 P22 Output Status 22 1 P23 Output Status 23 1 P24 Output Status 24 1 P25 Output Status 25 1 P26 Output Status 26 1 P27 Output Status 27 1 P28 Output Status 28 1 P29 Output Status 29 1 P3 Output Status 3 1 P30 Output Status 30 1 P31 Output Status 31 1 P4 Output Status 4 1 P5 Output Status 5 1 P6 Output Status 6 1 P7 Output Status 7 1 P8 Output Status 8 1 P9 Output Status 9 1 PIO_PIO_OWDR Output Write Disable 0xA4 32 write-only n 0x0 0x0 P0 Output Write Disable 0 1 P1 Output Write Disable 1 1 P10 Output Write Disable 10 1 P11 Output Write Disable 11 1 P12 Output Write Disable 12 1 P13 Output Write Disable 13 1 P14 Output Write Disable 14 1 P15 Output Write Disable 15 1 P16 Output Write Disable 16 1 P17 Output Write Disable 17 1 P18 Output Write Disable 18 1 P19 Output Write Disable 19 1 P2 Output Write Disable 2 1 P20 Output Write Disable 20 1 P21 Output Write Disable 21 1 P22 Output Write Disable 22 1 P23 Output Write Disable 23 1 P24 Output Write Disable 24 1 P25 Output Write Disable 25 1 P26 Output Write Disable 26 1 P27 Output Write Disable 27 1 P28 Output Write Disable 28 1 P29 Output Write Disable 29 1 P3 Output Write Disable 3 1 P30 Output Write Disable 30 1 P31 Output Write Disable 31 1 P4 Output Write Disable 4 1 P5 Output Write Disable 5 1 P6 Output Write Disable 6 1 P7 Output Write Disable 7 1 P8 Output Write Disable 8 1 P9 Output Write Disable 9 1 PIO_PIO_OWER Output Write Enable 0xA0 32 write-only n 0x0 0x0 P0 Output Write Enable 0 1 P1 Output Write Enable 1 1 P10 Output Write Enable 10 1 P11 Output Write Enable 11 1 P12 Output Write Enable 12 1 P13 Output Write Enable 13 1 P14 Output Write Enable 14 1 P15 Output Write Enable 15 1 P16 Output Write Enable 16 1 P17 Output Write Enable 17 1 P18 Output Write Enable 18 1 P19 Output Write Enable 19 1 P2 Output Write Enable 2 1 P20 Output Write Enable 20 1 P21 Output Write Enable 21 1 P22 Output Write Enable 22 1 P23 Output Write Enable 23 1 P24 Output Write Enable 24 1 P25 Output Write Enable 25 1 P26 Output Write Enable 26 1 P27 Output Write Enable 27 1 P28 Output Write Enable 28 1 P29 Output Write Enable 29 1 P3 Output Write Enable 3 1 P30 Output Write Enable 30 1 P31 Output Write Enable 31 1 P4 Output Write Enable 4 1 P5 Output Write Enable 5 1 P6 Output Write Enable 6 1 P7 Output Write Enable 7 1 P8 Output Write Enable 8 1 P9 Output Write Enable 9 1 PIO_PIO_OWSR Output Write Status Register 0xA8 32 read-only n 0x0 0x0 P0 Output Write Status 0 1 P1 Output Write Status 1 1 P10 Output Write Status 10 1 P11 Output Write Status 11 1 P12 Output Write Status 12 1 P13 Output Write Status 13 1 P14 Output Write Status 14 1 P15 Output Write Status 15 1 P16 Output Write Status 16 1 P17 Output Write Status 17 1 P18 Output Write Status 18 1 P19 Output Write Status 19 1 P2 Output Write Status 2 1 P20 Output Write Status 20 1 P21 Output Write Status 21 1 P22 Output Write Status 22 1 P23 Output Write Status 23 1 P24 Output Write Status 24 1 P25 Output Write Status 25 1 P26 Output Write Status 26 1 P27 Output Write Status 27 1 P28 Output Write Status 28 1 P29 Output Write Status 29 1 P3 Output Write Status 3 1 P30 Output Write Status 30 1 P31 Output Write Status 31 1 P4 Output Write Status 4 1 P5 Output Write Status 5 1 P6 Output Write Status 6 1 P7 Output Write Status 7 1 P8 Output Write Status 8 1 P9 Output Write Status 9 1 PIO_PIO_PCIDR Parallel Capture Interrupt Disable Register 0x158 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Disable 0 1 ENDRX End of Reception Transfer Interrupt Disable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Disable 1 1 RXBUFF Reception Buffer Full Interrupt Disable 3 1 PIO_PIO_PCIER Parallel Capture Interrupt Enable Register 0x154 32 write-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Enable 0 1 ENDRX End of Reception Transfer Interrupt Enable 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Enable 1 1 RXBUFF Reception Buffer Full Interrupt Enable 3 1 PIO_PIO_PCIMR Parallel Capture Interrupt Mask Register 0x15C 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready Interrupt Mask 0 1 ENDRX End of Reception Transfer Interrupt Mask 2 1 OVRE Parallel Capture Mode Overrun Error Interrupt Mask 1 1 RXBUFF Reception Buffer Full Interrupt Mask 3 1 PIO_PIO_PCISR Parallel Capture Interrupt Status Register 0x160 32 read-only n 0x0 0x0 DRDY Parallel Capture Mode Data Ready 0 1 OVRE Parallel Capture Mode Overrun Error 1 1 PIO_PIO_PCMR Parallel Capture Mode Register 0x150 32 read-write n 0x0 0x0 ALWYS Parallel Capture Mode Always Sampling 9 1 DSIZE Parallel Capture Mode Data Size 4 2 DSIZESelect BYTE The reception data in the PIO_PCRHR is a byte (8-bit) 0 HALFWORD The reception data in the PIO_PCRHR is a half-word (16-bit) 1 WORD The reception data in the PIO_PCRHR is a word (32-bit) 2 FRSTS Parallel Capture Mode First Sample 11 1 HALFS Parallel Capture Mode Half Sampling 10 1 PCEN Parallel Capture Mode Enable 0 1 PIO_PIO_PCRHR Parallel Capture Reception Holding Register 0x164 32 read-only n 0x0 0x0 RDATA Parallel Capture Mode Reception Data 0 32 PIO_PIO_PDR PIO Disable Register 0x4 32 write-only n 0x0 0x0 P0 PIO Disable 0 1 P1 PIO Disable 1 1 P10 PIO Disable 10 1 P11 PIO Disable 11 1 P12 PIO Disable 12 1 P13 PIO Disable 13 1 P14 PIO Disable 14 1 P15 PIO Disable 15 1 P16 PIO Disable 16 1 P17 PIO Disable 17 1 P18 PIO Disable 18 1 P19 PIO Disable 19 1 P2 PIO Disable 2 1 P20 PIO Disable 20 1 P21 PIO Disable 21 1 P22 PIO Disable 22 1 P23 PIO Disable 23 1 P24 PIO Disable 24 1 P25 PIO Disable 25 1 P26 PIO Disable 26 1 P27 PIO Disable 27 1 P28 PIO Disable 28 1 P29 PIO Disable 29 1 P3 PIO Disable 3 1 P30 PIO Disable 30 1 P31 PIO Disable 31 1 P4 PIO Disable 4 1 P5 PIO Disable 5 1 P6 PIO Disable 6 1 P7 PIO Disable 7 1 P8 PIO Disable 8 1 P9 PIO Disable 9 1 PIO_PIO_PDSR Pin Data Status Register 0x3C 32 read-only n 0x0 0x0 P0 Output Data Status 0 1 P1 Output Data Status 1 1 P10 Output Data Status 10 1 P11 Output Data Status 11 1 P12 Output Data Status 12 1 P13 Output Data Status 13 1 P14 Output Data Status 14 1 P15 Output Data Status 15 1 P16 Output Data Status 16 1 P17 Output Data Status 17 1 P18 Output Data Status 18 1 P19 Output Data Status 19 1 P2 Output Data Status 2 1 P20 Output Data Status 20 1 P21 Output Data Status 21 1 P22 Output Data Status 22 1 P23 Output Data Status 23 1 P24 Output Data Status 24 1 P25 Output Data Status 25 1 P26 Output Data Status 26 1 P27 Output Data Status 27 1 P28 Output Data Status 28 1 P29 Output Data Status 29 1 P3 Output Data Status 3 1 P30 Output Data Status 30 1 P31 Output Data Status 31 1 P4 Output Data Status 4 1 P5 Output Data Status 5 1 P6 Output Data Status 6 1 P7 Output Data Status 7 1 P8 Output Data Status 8 1 P9 Output Data Status 9 1 PIO_PIO_PER PIO Enable Register 0x0 32 write-only n 0x0 0x0 P0 PIO Enable 0 1 P1 PIO Enable 1 1 P10 PIO Enable 10 1 P11 PIO Enable 11 1 P12 PIO Enable 12 1 P13 PIO Enable 13 1 P14 PIO Enable 14 1 P15 PIO Enable 15 1 P16 PIO Enable 16 1 P17 PIO Enable 17 1 P18 PIO Enable 18 1 P19 PIO Enable 19 1 P2 PIO Enable 2 1 P20 PIO Enable 20 1 P21 PIO Enable 21 1 P22 PIO Enable 22 1 P23 PIO Enable 23 1 P24 PIO Enable 24 1 P25 PIO Enable 25 1 P26 PIO Enable 26 1 P27 PIO Enable 27 1 P28 PIO Enable 28 1 P29 PIO Enable 29 1 P3 PIO Enable 3 1 P30 PIO Enable 30 1 P31 PIO Enable 31 1 P4 PIO Enable 4 1 P5 PIO Enable 5 1 P6 PIO Enable 6 1 P7 PIO Enable 7 1 P8 PIO Enable 8 1 P9 PIO Enable 9 1 PIO_PIO_PPDDR Pad Pull-down Disable Register 0x90 32 write-only n 0x0 0x0 P0 Pull-Down Disable 0 1 P1 Pull-Down Disable 1 1 P10 Pull-Down Disable 10 1 P11 Pull-Down Disable 11 1 P12 Pull-Down Disable 12 1 P13 Pull-Down Disable 13 1 P14 Pull-Down Disable 14 1 P15 Pull-Down Disable 15 1 P16 Pull-Down Disable 16 1 P17 Pull-Down Disable 17 1 P18 Pull-Down Disable 18 1 P19 Pull-Down Disable 19 1 P2 Pull-Down Disable 2 1 P20 Pull-Down Disable 20 1 P21 Pull-Down Disable 21 1 P22 Pull-Down Disable 22 1 P23 Pull-Down Disable 23 1 P24 Pull-Down Disable 24 1 P25 Pull-Down Disable 25 1 P26 Pull-Down Disable 26 1 P27 Pull-Down Disable 27 1 P28 Pull-Down Disable 28 1 P29 Pull-Down Disable 29 1 P3 Pull-Down Disable 3 1 P30 Pull-Down Disable 30 1 P31 Pull-Down Disable 31 1 P4 Pull-Down Disable 4 1 P5 Pull-Down Disable 5 1 P6 Pull-Down Disable 6 1 P7 Pull-Down Disable 7 1 P8 Pull-Down Disable 8 1 P9 Pull-Down Disable 9 1 PIO_PIO_PPDER Pad Pull-down Enable Register 0x94 32 write-only n 0x0 0x0 P0 Pull-Down Enable 0 1 P1 Pull-Down Enable 1 1 P10 Pull-Down Enable 10 1 P11 Pull-Down Enable 11 1 P12 Pull-Down Enable 12 1 P13 Pull-Down Enable 13 1 P14 Pull-Down Enable 14 1 P15 Pull-Down Enable 15 1 P16 Pull-Down Enable 16 1 P17 Pull-Down Enable 17 1 P18 Pull-Down Enable 18 1 P19 Pull-Down Enable 19 1 P2 Pull-Down Enable 2 1 P20 Pull-Down Enable 20 1 P21 Pull-Down Enable 21 1 P22 Pull-Down Enable 22 1 P23 Pull-Down Enable 23 1 P24 Pull-Down Enable 24 1 P25 Pull-Down Enable 25 1 P26 Pull-Down Enable 26 1 P27 Pull-Down Enable 27 1 P28 Pull-Down Enable 28 1 P29 Pull-Down Enable 29 1 P3 Pull-Down Enable 3 1 P30 Pull-Down Enable 30 1 P31 Pull-Down Enable 31 1 P4 Pull-Down Enable 4 1 P5 Pull-Down Enable 5 1 P6 Pull-Down Enable 6 1 P7 Pull-Down Enable 7 1 P8 Pull-Down Enable 8 1 P9 Pull-Down Enable 9 1 PIO_PIO_PPDSR Pad Pull-down Status Register 0x98 32 read-only n 0x0 0x0 P0 Pull-Down Status 0 1 P1 Pull-Down Status 1 1 P10 Pull-Down Status 10 1 P11 Pull-Down Status 11 1 P12 Pull-Down Status 12 1 P13 Pull-Down Status 13 1 P14 Pull-Down Status 14 1 P15 Pull-Down Status 15 1 P16 Pull-Down Status 16 1 P17 Pull-Down Status 17 1 P18 Pull-Down Status 18 1 P19 Pull-Down Status 19 1 P2 Pull-Down Status 2 1 P20 Pull-Down Status 20 1 P21 Pull-Down Status 21 1 P22 Pull-Down Status 22 1 P23 Pull-Down Status 23 1 P24 Pull-Down Status 24 1 P25 Pull-Down Status 25 1 P26 Pull-Down Status 26 1 P27 Pull-Down Status 27 1 P28 Pull-Down Status 28 1 P29 Pull-Down Status 29 1 P3 Pull-Down Status 3 1 P30 Pull-Down Status 30 1 P31 Pull-Down Status 31 1 P4 Pull-Down Status 4 1 P5 Pull-Down Status 5 1 P6 Pull-Down Status 6 1 P7 Pull-Down Status 7 1 P8 Pull-Down Status 8 1 P9 Pull-Down Status 9 1 PIO_PIO_PSR PIO Status Register 0x8 32 read-only n 0x0 0x0 P0 PIO Status 0 1 P1 PIO Status 1 1 P10 PIO Status 10 1 P11 PIO Status 11 1 P12 PIO Status 12 1 P13 PIO Status 13 1 P14 PIO Status 14 1 P15 PIO Status 15 1 P16 PIO Status 16 1 P17 PIO Status 17 1 P18 PIO Status 18 1 P19 PIO Status 19 1 P2 PIO Status 2 1 P20 PIO Status 20 1 P21 PIO Status 21 1 P22 PIO Status 22 1 P23 PIO Status 23 1 P24 PIO Status 24 1 P25 PIO Status 25 1 P26 PIO Status 26 1 P27 PIO Status 27 1 P28 PIO Status 28 1 P29 PIO Status 29 1 P3 PIO Status 3 1 P30 PIO Status 30 1 P31 PIO Status 31 1 P4 PIO Status 4 1 P5 PIO Status 5 1 P6 PIO Status 6 1 P7 PIO Status 7 1 P8 PIO Status 8 1 P9 PIO Status 9 1 PIO_PIO_PUDR Pull-up Disable Register 0x60 32 write-only n 0x0 0x0 P0 Pull-Up Disable 0 1 P1 Pull-Up Disable 1 1 P10 Pull-Up Disable 10 1 P11 Pull-Up Disable 11 1 P12 Pull-Up Disable 12 1 P13 Pull-Up Disable 13 1 P14 Pull-Up Disable 14 1 P15 Pull-Up Disable 15 1 P16 Pull-Up Disable 16 1 P17 Pull-Up Disable 17 1 P18 Pull-Up Disable 18 1 P19 Pull-Up Disable 19 1 P2 Pull-Up Disable 2 1 P20 Pull-Up Disable 20 1 P21 Pull-Up Disable 21 1 P22 Pull-Up Disable 22 1 P23 Pull-Up Disable 23 1 P24 Pull-Up Disable 24 1 P25 Pull-Up Disable 25 1 P26 Pull-Up Disable 26 1 P27 Pull-Up Disable 27 1 P28 Pull-Up Disable 28 1 P29 Pull-Up Disable 29 1 P3 Pull-Up Disable 3 1 P30 Pull-Up Disable 30 1 P31 Pull-Up Disable 31 1 P4 Pull-Up Disable 4 1 P5 Pull-Up Disable 5 1 P6 Pull-Up Disable 6 1 P7 Pull-Up Disable 7 1 P8 Pull-Up Disable 8 1 P9 Pull-Up Disable 9 1 PIO_PIO_PUER Pull-up Enable Register 0x64 32 write-only n 0x0 0x0 P0 Pull-Up Enable 0 1 P1 Pull-Up Enable 1 1 P10 Pull-Up Enable 10 1 P11 Pull-Up Enable 11 1 P12 Pull-Up Enable 12 1 P13 Pull-Up Enable 13 1 P14 Pull-Up Enable 14 1 P15 Pull-Up Enable 15 1 P16 Pull-Up Enable 16 1 P17 Pull-Up Enable 17 1 P18 Pull-Up Enable 18 1 P19 Pull-Up Enable 19 1 P2 Pull-Up Enable 2 1 P20 Pull-Up Enable 20 1 P21 Pull-Up Enable 21 1 P22 Pull-Up Enable 22 1 P23 Pull-Up Enable 23 1 P24 Pull-Up Enable 24 1 P25 Pull-Up Enable 25 1 P26 Pull-Up Enable 26 1 P27 Pull-Up Enable 27 1 P28 Pull-Up Enable 28 1 P29 Pull-Up Enable 29 1 P3 Pull-Up Enable 3 1 P30 Pull-Up Enable 30 1 P31 Pull-Up Enable 31 1 P4 Pull-Up Enable 4 1 P5 Pull-Up Enable 5 1 P6 Pull-Up Enable 6 1 P7 Pull-Up Enable 7 1 P8 Pull-Up Enable 8 1 P9 Pull-Up Enable 9 1 PIO_PIO_PUSR Pad Pull-up Status Register 0x68 32 read-only n 0x0 0x0 P0 Pull-Up Status 0 1 P1 Pull-Up Status 1 1 P10 Pull-Up Status 10 1 P11 Pull-Up Status 11 1 P12 Pull-Up Status 12 1 P13 Pull-Up Status 13 1 P14 Pull-Up Status 14 1 P15 Pull-Up Status 15 1 P16 Pull-Up Status 16 1 P17 Pull-Up Status 17 1 P18 Pull-Up Status 18 1 P19 Pull-Up Status 19 1 P2 Pull-Up Status 2 1 P20 Pull-Up Status 20 1 P21 Pull-Up Status 21 1 P22 Pull-Up Status 22 1 P23 Pull-Up Status 23 1 P24 Pull-Up Status 24 1 P25 Pull-Up Status 25 1 P26 Pull-Up Status 26 1 P27 Pull-Up Status 27 1 P28 Pull-Up Status 28 1 P29 Pull-Up Status 29 1 P3 Pull-Up Status 3 1 P30 Pull-Up Status 30 1 P31 Pull-Up Status 31 1 P4 Pull-Up Status 4 1 P5 Pull-Up Status 5 1 P6 Pull-Up Status 6 1 P7 Pull-Up Status 7 1 P8 Pull-Up Status 8 1 P9 Pull-Up Status 9 1 PIO_PIO_REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n 0x0 0x0 P0 Rising Edge/High-Level Interrupt Selection 0 1 P1 Rising Edge/High-Level Interrupt Selection 1 1 P10 Rising Edge/High-Level Interrupt Selection 10 1 P11 Rising Edge/High-Level Interrupt Selection 11 1 P12 Rising Edge/High-Level Interrupt Selection 12 1 P13 Rising Edge/High-Level Interrupt Selection 13 1 P14 Rising Edge/High-Level Interrupt Selection 14 1 P15 Rising Edge/High-Level Interrupt Selection 15 1 P16 Rising Edge/High-Level Interrupt Selection 16 1 P17 Rising Edge/High-Level Interrupt Selection 17 1 P18 Rising Edge/High-Level Interrupt Selection 18 1 P19 Rising Edge/High-Level Interrupt Selection 19 1 P2 Rising Edge/High-Level Interrupt Selection 2 1 P20 Rising Edge/High-Level Interrupt Selection 20 1 P21 Rising Edge/High-Level Interrupt Selection 21 1 P22 Rising Edge/High-Level Interrupt Selection 22 1 P23 Rising Edge/High-Level Interrupt Selection 23 1 P24 Rising Edge/High-Level Interrupt Selection 24 1 P25 Rising Edge/High-Level Interrupt Selection 25 1 P26 Rising Edge/High-Level Interrupt Selection 26 1 P27 Rising Edge/High-Level Interrupt Selection 27 1 P28 Rising Edge/High-Level Interrupt Selection 28 1 P29 Rising Edge/High-Level Interrupt Selection 29 1 P3 Rising Edge/High-Level Interrupt Selection 3 1 P30 Rising Edge/High-Level Interrupt Selection 30 1 P31 Rising Edge/High-Level Interrupt Selection 31 1 P4 Rising Edge/High-Level Interrupt Selection 4 1 P5 Rising Edge/High-Level Interrupt Selection 5 1 P6 Rising Edge/High-Level Interrupt Selection 6 1 P7 Rising Edge/High-Level Interrupt Selection 7 1 P8 Rising Edge/High-Level Interrupt Selection 8 1 P9 Rising Edge/High-Level Interrupt Selection 9 1 PIO_PIO_SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 PIO_PIO_SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 0x0 SCHMITT0 Schmitt Trigger Control 0 1 SCHMITT1 Schmitt Trigger Control 1 1 SCHMITT10 Schmitt Trigger Control 10 1 SCHMITT11 Schmitt Trigger Control 11 1 SCHMITT12 Schmitt Trigger Control 12 1 SCHMITT13 Schmitt Trigger Control 13 1 SCHMITT14 Schmitt Trigger Control 14 1 SCHMITT15 Schmitt Trigger Control 15 1 SCHMITT16 Schmitt Trigger Control 16 1 SCHMITT17 Schmitt Trigger Control 17 1 SCHMITT18 Schmitt Trigger Control 18 1 SCHMITT19 Schmitt Trigger Control 19 1 SCHMITT2 Schmitt Trigger Control 2 1 SCHMITT20 Schmitt Trigger Control 20 1 SCHMITT21 Schmitt Trigger Control 21 1 SCHMITT22 Schmitt Trigger Control 22 1 SCHMITT23 Schmitt Trigger Control 23 1 SCHMITT24 Schmitt Trigger Control 24 1 SCHMITT25 Schmitt Trigger Control 25 1 SCHMITT26 Schmitt Trigger Control 26 1 SCHMITT27 Schmitt Trigger Control 27 1 SCHMITT28 Schmitt Trigger Control 28 1 SCHMITT29 Schmitt Trigger Control 29 1 SCHMITT3 Schmitt Trigger Control 3 1 SCHMITT30 Schmitt Trigger Control 30 1 SCHMITT31 Schmitt Trigger Control 31 1 SCHMITT4 Schmitt Trigger Control 4 1 SCHMITT5 Schmitt Trigger Control 5 1 SCHMITT6 Schmitt Trigger Control 6 1 SCHMITT7 Schmitt Trigger Control 7 1 SCHMITT8 Schmitt Trigger Control 8 1 SCHMITT9 Schmitt Trigger Control 9 1 PIO_PIO_SODR Set Output Data Register 0x30 32 write-only n 0x0 0x0 P0 Set Output Data 0 1 P1 Set Output Data 1 1 P10 Set Output Data 10 1 P11 Set Output Data 11 1 P12 Set Output Data 12 1 P13 Set Output Data 13 1 P14 Set Output Data 14 1 P15 Set Output Data 15 1 P16 Set Output Data 16 1 P17 Set Output Data 17 1 P18 Set Output Data 18 1 P19 Set Output Data 19 1 P2 Set Output Data 2 1 P20 Set Output Data 20 1 P21 Set Output Data 21 1 P22 Set Output Data 22 1 P23 Set Output Data 23 1 P24 Set Output Data 24 1 P25 Set Output Data 25 1 P26 Set Output Data 26 1 P27 Set Output Data 27 1 P28 Set Output Data 28 1 P29 Set Output Data 29 1 P3 Set Output Data 3 1 P30 Set Output Data 30 1 P31 Set Output Data 31 1 P4 Set Output Data 4 1 P5 Set Output Data 5 1 P6 Set Output Data 6 1 P7 Set Output Data 7 1 P8 Set Output Data 8 1 P9 Set Output Data 9 1 PIO_PIO_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5261647 PIO_PIO_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PPDDR Pad Pull-down Disable Register 0x90 32 write-only n P0 Pull-Down Disable 0 1 write-only P1 Pull-Down Disable 1 1 write-only P10 Pull-Down Disable 10 1 write-only P11 Pull-Down Disable 11 1 write-only P12 Pull-Down Disable 12 1 write-only P13 Pull-Down Disable 13 1 write-only P14 Pull-Down Disable 14 1 write-only P15 Pull-Down Disable 15 1 write-only P16 Pull-Down Disable 16 1 write-only P17 Pull-Down Disable 17 1 write-only P18 Pull-Down Disable 18 1 write-only P19 Pull-Down Disable 19 1 write-only P2 Pull-Down Disable 2 1 write-only P20 Pull-Down Disable 20 1 write-only P21 Pull-Down Disable 21 1 write-only P22 Pull-Down Disable 22 1 write-only P23 Pull-Down Disable 23 1 write-only P24 Pull-Down Disable 24 1 write-only P25 Pull-Down Disable 25 1 write-only P26 Pull-Down Disable 26 1 write-only P27 Pull-Down Disable 27 1 write-only P28 Pull-Down Disable 28 1 write-only P29 Pull-Down Disable 29 1 write-only P3 Pull-Down Disable 3 1 write-only P30 Pull-Down Disable 30 1 write-only P31 Pull-Down Disable 31 1 write-only P4 Pull-Down Disable 4 1 write-only P5 Pull-Down Disable 5 1 write-only P6 Pull-Down Disable 6 1 write-only P7 Pull-Down Disable 7 1 write-only P8 Pull-Down Disable 8 1 write-only P9 Pull-Down Disable 9 1 write-only PPDER Pad Pull-down Enable Register 0x94 32 write-only n P0 Pull-Down Enable 0 1 write-only P1 Pull-Down Enable 1 1 write-only P10 Pull-Down Enable 10 1 write-only P11 Pull-Down Enable 11 1 write-only P12 Pull-Down Enable 12 1 write-only P13 Pull-Down Enable 13 1 write-only P14 Pull-Down Enable 14 1 write-only P15 Pull-Down Enable 15 1 write-only P16 Pull-Down Enable 16 1 write-only P17 Pull-Down Enable 17 1 write-only P18 Pull-Down Enable 18 1 write-only P19 Pull-Down Enable 19 1 write-only P2 Pull-Down Enable 2 1 write-only P20 Pull-Down Enable 20 1 write-only P21 Pull-Down Enable 21 1 write-only P22 Pull-Down Enable 22 1 write-only P23 Pull-Down Enable 23 1 write-only P24 Pull-Down Enable 24 1 write-only P25 Pull-Down Enable 25 1 write-only P26 Pull-Down Enable 26 1 write-only P27 Pull-Down Enable 27 1 write-only P28 Pull-Down Enable 28 1 write-only P29 Pull-Down Enable 29 1 write-only P3 Pull-Down Enable 3 1 write-only P30 Pull-Down Enable 30 1 write-only P31 Pull-Down Enable 31 1 write-only P4 Pull-Down Enable 4 1 write-only P5 Pull-Down Enable 5 1 write-only P6 Pull-Down Enable 6 1 write-only P7 Pull-Down Enable 7 1 write-only P8 Pull-Down Enable 8 1 write-only P9 Pull-Down Enable 9 1 write-only PPDSR Pad Pull-down Status Register 0x98 32 read-only n P0 Pull-Down Status 0 1 read-only P1 Pull-Down Status 1 1 read-only P10 Pull-Down Status 10 1 read-only P11 Pull-Down Status 11 1 read-only P12 Pull-Down Status 12 1 read-only P13 Pull-Down Status 13 1 read-only P14 Pull-Down Status 14 1 read-only P15 Pull-Down Status 15 1 read-only P16 Pull-Down Status 16 1 read-only P17 Pull-Down Status 17 1 read-only P18 Pull-Down Status 18 1 read-only P19 Pull-Down Status 19 1 read-only P2 Pull-Down Status 2 1 read-only P20 Pull-Down Status 20 1 read-only P21 Pull-Down Status 21 1 read-only P22 Pull-Down Status 22 1 read-only P23 Pull-Down Status 23 1 read-only P24 Pull-Down Status 24 1 read-only P25 Pull-Down Status 25 1 read-only P26 Pull-Down Status 26 1 read-only P27 Pull-Down Status 27 1 read-only P28 Pull-Down Status 28 1 read-only P29 Pull-Down Status 29 1 read-only P3 Pull-Down Status 3 1 read-only P30 Pull-Down Status 30 1 read-only P31 Pull-Down Status 31 1 read-only P4 Pull-Down Status 4 1 read-only P5 Pull-Down Status 5 1 read-only P6 Pull-Down Status 6 1 read-only P7 Pull-Down Status 7 1 read-only P8 Pull-Down Status 8 1 read-only P9 Pull-Down Status 9 1 read-only PSR PIO Status Register 0x8 32 read-only n P0 PIO Status 0 1 read-only P1 PIO Status 1 1 read-only P10 PIO Status 10 1 read-only P11 PIO Status 11 1 read-only P12 PIO Status 12 1 read-only P13 PIO Status 13 1 read-only P14 PIO Status 14 1 read-only P15 PIO Status 15 1 read-only P16 PIO Status 16 1 read-only P17 PIO Status 17 1 read-only P18 PIO Status 18 1 read-only P19 PIO Status 19 1 read-only P2 PIO Status 2 1 read-only P20 PIO Status 20 1 read-only P21 PIO Status 21 1 read-only P22 PIO Status 22 1 read-only P23 PIO Status 23 1 read-only P24 PIO Status 24 1 read-only P25 PIO Status 25 1 read-only P26 PIO Status 26 1 read-only P27 PIO Status 27 1 read-only P28 PIO Status 28 1 read-only P29 PIO Status 29 1 read-only P3 PIO Status 3 1 read-only P30 PIO Status 30 1 read-only P31 PIO Status 31 1 read-only P4 PIO Status 4 1 read-only P5 PIO Status 5 1 read-only P6 PIO Status 6 1 read-only P7 PIO Status 7 1 read-only P8 PIO Status 8 1 read-only P9 PIO Status 9 1 read-only PUDR Pull-up Disable Register 0x60 32 write-only n P0 Pull-Up Disable 0 1 write-only P1 Pull-Up Disable 1 1 write-only P10 Pull-Up Disable 10 1 write-only P11 Pull-Up Disable 11 1 write-only P12 Pull-Up Disable 12 1 write-only P13 Pull-Up Disable 13 1 write-only P14 Pull-Up Disable 14 1 write-only P15 Pull-Up Disable 15 1 write-only P16 Pull-Up Disable 16 1 write-only P17 Pull-Up Disable 17 1 write-only P18 Pull-Up Disable 18 1 write-only P19 Pull-Up Disable 19 1 write-only P2 Pull-Up Disable 2 1 write-only P20 Pull-Up Disable 20 1 write-only P21 Pull-Up Disable 21 1 write-only P22 Pull-Up Disable 22 1 write-only P23 Pull-Up Disable 23 1 write-only P24 Pull-Up Disable 24 1 write-only P25 Pull-Up Disable 25 1 write-only P26 Pull-Up Disable 26 1 write-only P27 Pull-Up Disable 27 1 write-only P28 Pull-Up Disable 28 1 write-only P29 Pull-Up Disable 29 1 write-only P3 Pull-Up Disable 3 1 write-only P30 Pull-Up Disable 30 1 write-only P31 Pull-Up Disable 31 1 write-only P4 Pull-Up Disable 4 1 write-only P5 Pull-Up Disable 5 1 write-only P6 Pull-Up Disable 6 1 write-only P7 Pull-Up Disable 7 1 write-only P8 Pull-Up Disable 8 1 write-only P9 Pull-Up Disable 9 1 write-only PUER Pull-up Enable Register 0x64 32 write-only n P0 Pull-Up Enable 0 1 write-only P1 Pull-Up Enable 1 1 write-only P10 Pull-Up Enable 10 1 write-only P11 Pull-Up Enable 11 1 write-only P12 Pull-Up Enable 12 1 write-only P13 Pull-Up Enable 13 1 write-only P14 Pull-Up Enable 14 1 write-only P15 Pull-Up Enable 15 1 write-only P16 Pull-Up Enable 16 1 write-only P17 Pull-Up Enable 17 1 write-only P18 Pull-Up Enable 18 1 write-only P19 Pull-Up Enable 19 1 write-only P2 Pull-Up Enable 2 1 write-only P20 Pull-Up Enable 20 1 write-only P21 Pull-Up Enable 21 1 write-only P22 Pull-Up Enable 22 1 write-only P23 Pull-Up Enable 23 1 write-only P24 Pull-Up Enable 24 1 write-only P25 Pull-Up Enable 25 1 write-only P26 Pull-Up Enable 26 1 write-only P27 Pull-Up Enable 27 1 write-only P28 Pull-Up Enable 28 1 write-only P29 Pull-Up Enable 29 1 write-only P3 Pull-Up Enable 3 1 write-only P30 Pull-Up Enable 30 1 write-only P31 Pull-Up Enable 31 1 write-only P4 Pull-Up Enable 4 1 write-only P5 Pull-Up Enable 5 1 write-only P6 Pull-Up Enable 6 1 write-only P7 Pull-Up Enable 7 1 write-only P8 Pull-Up Enable 8 1 write-only P9 Pull-Up Enable 9 1 write-only PUSR Pad Pull-up Status Register 0x68 32 read-only n P0 Pull-Up Status 0 1 read-only P1 Pull-Up Status 1 1 read-only P10 Pull-Up Status 10 1 read-only P11 Pull-Up Status 11 1 read-only P12 Pull-Up Status 12 1 read-only P13 Pull-Up Status 13 1 read-only P14 Pull-Up Status 14 1 read-only P15 Pull-Up Status 15 1 read-only P16 Pull-Up Status 16 1 read-only P17 Pull-Up Status 17 1 read-only P18 Pull-Up Status 18 1 read-only P19 Pull-Up Status 19 1 read-only P2 Pull-Up Status 2 1 read-only P20 Pull-Up Status 20 1 read-only P21 Pull-Up Status 21 1 read-only P22 Pull-Up Status 22 1 read-only P23 Pull-Up Status 23 1 read-only P24 Pull-Up Status 24 1 read-only P25 Pull-Up Status 25 1 read-only P26 Pull-Up Status 26 1 read-only P27 Pull-Up Status 27 1 read-only P28 Pull-Up Status 28 1 read-only P29 Pull-Up Status 29 1 read-only P3 Pull-Up Status 3 1 read-only P30 Pull-Up Status 30 1 read-only P31 Pull-Up Status 31 1 read-only P4 Pull-Up Status 4 1 read-only P5 Pull-Up Status 5 1 read-only P6 Pull-Up Status 6 1 read-only P7 Pull-Up Status 7 1 read-only P8 Pull-Up Status 8 1 read-only P9 Pull-Up Status 9 1 read-only REHLSR Rising Edge/High-Level Select Register 0xD4 32 write-only n P0 Rising Edge/High-Level Interrupt Selection 0 1 write-only P1 Rising Edge/High-Level Interrupt Selection 1 1 write-only P10 Rising Edge/High-Level Interrupt Selection 10 1 write-only P11 Rising Edge/High-Level Interrupt Selection 11 1 write-only P12 Rising Edge/High-Level Interrupt Selection 12 1 write-only P13 Rising Edge/High-Level Interrupt Selection 13 1 write-only P14 Rising Edge/High-Level Interrupt Selection 14 1 write-only P15 Rising Edge/High-Level Interrupt Selection 15 1 write-only P16 Rising Edge/High-Level Interrupt Selection 16 1 write-only P17 Rising Edge/High-Level Interrupt Selection 17 1 write-only P18 Rising Edge/High-Level Interrupt Selection 18 1 write-only P19 Rising Edge/High-Level Interrupt Selection 19 1 write-only P2 Rising Edge/High-Level Interrupt Selection 2 1 write-only P20 Rising Edge/High-Level Interrupt Selection 20 1 write-only P21 Rising Edge/High-Level Interrupt Selection 21 1 write-only P22 Rising Edge/High-Level Interrupt Selection 22 1 write-only P23 Rising Edge/High-Level Interrupt Selection 23 1 write-only P24 Rising Edge/High-Level Interrupt Selection 24 1 write-only P25 Rising Edge/High-Level Interrupt Selection 25 1 write-only P26 Rising Edge/High-Level Interrupt Selection 26 1 write-only P27 Rising Edge/High-Level Interrupt Selection 27 1 write-only P28 Rising Edge/High-Level Interrupt Selection 28 1 write-only P29 Rising Edge/High-Level Interrupt Selection 29 1 write-only P3 Rising Edge/High-Level Interrupt Selection 3 1 write-only P30 Rising Edge/High-Level Interrupt Selection 30 1 write-only P31 Rising Edge/High-Level Interrupt Selection 31 1 write-only P4 Rising Edge/High-Level Interrupt Selection 4 1 write-only P5 Rising Edge/High-Level Interrupt Selection 5 1 write-only P6 Rising Edge/High-Level Interrupt Selection 6 1 write-only P7 Rising Edge/High-Level Interrupt Selection 7 1 write-only P8 Rising Edge/High-Level Interrupt Selection 8 1 write-only P9 Rising Edge/High-Level Interrupt Selection 9 1 write-only SCDR Slow Clock Divider Debouncing Register 0x8C 32 read-write n 0x0 DIV Slow Clock Divider Selection for Debouncing 0 14 read-write SCHMITT Schmitt Trigger Register 0x100 32 read-write n 0x0 SCHMITT0 Schmitt Trigger Control 0 1 read-write SCHMITT1 Schmitt Trigger Control 1 1 read-write SCHMITT10 Schmitt Trigger Control 10 1 read-write SCHMITT11 Schmitt Trigger Control 11 1 read-write SCHMITT12 Schmitt Trigger Control 12 1 read-write SCHMITT13 Schmitt Trigger Control 13 1 read-write SCHMITT14 Schmitt Trigger Control 14 1 read-write SCHMITT15 Schmitt Trigger Control 15 1 read-write SCHMITT16 Schmitt Trigger Control 16 1 read-write SCHMITT17 Schmitt Trigger Control 17 1 read-write SCHMITT18 Schmitt Trigger Control 18 1 read-write SCHMITT19 Schmitt Trigger Control 19 1 read-write SCHMITT2 Schmitt Trigger Control 2 1 read-write SCHMITT20 Schmitt Trigger Control 20 1 read-write SCHMITT21 Schmitt Trigger Control 21 1 read-write SCHMITT22 Schmitt Trigger Control 22 1 read-write SCHMITT23 Schmitt Trigger Control 23 1 read-write SCHMITT24 Schmitt Trigger Control 24 1 read-write SCHMITT25 Schmitt Trigger Control 25 1 read-write SCHMITT26 Schmitt Trigger Control 26 1 read-write SCHMITT27 Schmitt Trigger Control 27 1 read-write SCHMITT28 Schmitt Trigger Control 28 1 read-write SCHMITT29 Schmitt Trigger Control 29 1 read-write SCHMITT3 Schmitt Trigger Control 3 1 read-write SCHMITT30 Schmitt Trigger Control 30 1 read-write SCHMITT31 Schmitt Trigger Control 31 1 read-write SCHMITT4 Schmitt Trigger Control 4 1 read-write SCHMITT5 Schmitt Trigger Control 5 1 read-write SCHMITT6 Schmitt Trigger Control 6 1 read-write SCHMITT7 Schmitt Trigger Control 7 1 read-write SCHMITT8 Schmitt Trigger Control 8 1 read-write SCHMITT9 Schmitt Trigger Control 9 1 read-write SODR Set Output Data Register 0x30 32 write-only n P0 Set Output Data 0 1 write-only P1 Set Output Data 1 1 write-only P10 Set Output Data 10 1 write-only P11 Set Output Data 11 1 write-only P12 Set Output Data 12 1 write-only P13 Set Output Data 13 1 write-only P14 Set Output Data 14 1 write-only P15 Set Output Data 15 1 write-only P16 Set Output Data 16 1 write-only P17 Set Output Data 17 1 write-only P18 Set Output Data 18 1 write-only P19 Set Output Data 19 1 write-only P2 Set Output Data 2 1 write-only P20 Set Output Data 20 1 write-only P21 Set Output Data 21 1 write-only P22 Set Output Data 22 1 write-only P23 Set Output Data 23 1 write-only P24 Set Output Data 24 1 write-only P25 Set Output Data 25 1 write-only P26 Set Output Data 26 1 write-only P27 Set Output Data 27 1 write-only P28 Set Output Data 28 1 write-only P29 Set Output Data 29 1 write-only P3 Set Output Data 3 1 write-only P30 Set Output Data 30 1 write-only P31 Set Output Data 31 1 write-only P4 Set Output Data 4 1 write-only P5 Set Output Data 5 1 write-only P6 Set Output Data 6 1 write-only P7 Set Output Data 7 1 write-only P8 Set Output Data 8 1 write-only P9 Set Output Data 9 1 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x50494F WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only PMC Power Management Controller PMC 0x0 0x0 0x200 registers n PMC 5 CKGR_MCFR Main Clock Frequency Register 0x24 32 read-write n 0x0 0x0 CCSS Counter Clock Source Selection 24 1 MAINF Main Clock Frequency 0 16 MAINFRDY Main Clock Frequency Measure Ready 16 1 RCMEAS RC Oscillator Frequency Measure (write-only) 20 1 CKGR_MOR Main Oscillator Register 0x20 32 read-write n 0x0 0x0 CFDEN Clock Failure Detector Enable 25 1 KEY Write Access Password 16 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 55 MOSCRCEN Main RC Oscillator Enable 3 1 MOSCRCF Main RC Oscillator Frequency Selection 4 3 MOSCRCFSelect _4_MHz The RC oscillator frequency is at 4 MHz 0 _8_MHz The RC oscillator frequency is at 8 MHz 1 _12_MHz The RC oscillator frequency is at 12 MHz 2 MOSCSEL Main Clock Oscillator Selection 24 1 MOSCXTBY Main Crystal Oscillator Bypass 1 1 MOSCXTEN Main Crystal Oscillator Enable 0 1 MOSCXTST Main Crystal Oscillator Startup Time 8 8 WAITMODE Wait Mode Command (Write-only) 2 1 XT32KFME 32.768 kHz Crystal Oscillator Frequency Monitoring Enable 26 1 CKGR_PLLAR PLLA Register 0x28 32 read-write n 0x0 0x0 DIVA PLLA Front End Divider 0 8 DIVASelect _0 Divider output is 0 and PLLA is disabled. 0 BYPASS Divider is bypassed (divide by 1) and PLLA is enabled. 1 MULA PLLA Multiplier 16 11 ONE Must Be Set to 1 29 1 PLLACOUNT PLLA Counter 8 6 CKGR_UCKR UTMI Clock Register 0x1C 32 read-write n 0x0 0x0 UPLLCOUNT UTMI PLL Start-up Time 20 4 UPLLEN UTMI PLL Enable 16 1 FOCR Fault Output Clear Register 0x78 32 write-only n 0x0 0x0 FOCLR Fault Output Clear 0 1 FSMR Fast Startup Mode Register 0x70 32 read-write n 0x0 0x0 FFLPM Force Flash Low-power Mode 23 1 FLPM Flash Low-power Mode 21 2 FLPMSelect FLASH_STANDBY Flash is in Standby Mode when system enters Wait Mode 0 FLASH_DEEP_POWERDOWN Flash is in Deep-power-down mode when system enters Wait Mode 1 FLASH_IDLE Idle mode 2 FSTT0 Fast Startup Input Enable 0 0 1 FSTT1 Fast Startup Input Enable 1 1 1 FSTT10 Fast Startup Input Enable 10 10 1 FSTT11 Fast Startup Input Enable 11 11 1 FSTT12 Fast Startup Input Enable 12 12 1 FSTT13 Fast Startup Input Enable 13 13 1 FSTT14 Fast Startup Input Enable 14 14 1 FSTT15 Fast Startup Input Enable 15 15 1 FSTT2 Fast Startup Input Enable 2 2 1 FSTT3 Fast Startup Input Enable 3 3 1 FSTT4 Fast Startup Input Enable 4 4 1 FSTT5 Fast Startup Input Enable 5 5 1 FSTT6 Fast Startup Input Enable 6 6 1 FSTT7 Fast Startup Input Enable 7 7 1 FSTT8 Fast Startup Input Enable 8 8 1 FSTT9 Fast Startup Input Enable 9 9 1 LPM Low-power Mode 20 1 RTCAL RTC Alarm Enable 17 1 RTTAL RTT Alarm Enable 16 1 USBAL USB Alarm Enable 18 1 FSPR Fast Startup Polarity Register 0x74 32 read-write n 0x0 0x0 FSTP0 Fast Startup Input Polarity 0 0 1 FSTP1 Fast Startup Input Polarity 1 1 1 FSTP10 Fast Startup Input Polarity 10 10 1 FSTP11 Fast Startup Input Polarity 11 11 1 FSTP12 Fast Startup Input Polarity 12 12 1 FSTP13 Fast Startup Input Polarity 13 13 1 FSTP14 Fast Startup Input Polarity 14 14 1 FSTP15 Fast Startup Input Polarity 15 15 1 FSTP2 Fast Startup Input Polarity 2 2 1 FSTP3 Fast Startup Input Polarity 3 3 1 FSTP4 Fast Startup Input Polarity 4 4 1 FSTP5 Fast Startup Input Polarity 5 5 1 FSTP6 Fast Startup Input Polarity 6 6 1 FSTP7 Fast Startup Input Polarity 7 7 1 FSTP8 Fast Startup Input Polarity 8 8 1 FSTP9 Fast Startup Input Polarity 9 9 1 IDR Interrupt Disable Register 0x64 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Disable 18 1 LOCKA PLLA Lock Interrupt Disable 1 1 LOCKU UTMI PLL Lock Interrupt Disable 6 1 MCKRDY Master Clock Ready Interrupt Disable 3 1 MOSCRCS Main RC Status Interrupt Disable 17 1 MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Disable 16 1 MOSCXTS Main Crystal Oscillator Status Interrupt Disable 0 1 PCKRDY0 Programmable Clock Ready 0 Interrupt Disable 8 1 PCKRDY1 Programmable Clock Ready 1 Interrupt Disable 9 1 PCKRDY2 Programmable Clock Ready 2 Interrupt Disable 10 1 PCKRDY3 Programmable Clock Ready 3 Interrupt Disable 11 1 PCKRDY4 Programmable Clock Ready 4 Interrupt Disable 12 1 PCKRDY5 Programmable Clock Ready 5 Interrupt Disable 13 1 PCKRDY6 Programmable Clock Ready 6 Interrupt Disable 14 1 XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Disable 21 1 IER Interrupt Enable Register 0x60 32 write-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Enable 18 1 LOCKA PLLA Lock Interrupt Enable 1 1 LOCKU UTMI PLL Lock Interrupt Enable 6 1 MCKRDY Master Clock Ready Interrupt Enable 3 1 MOSCRCS Main RC Oscillator Status Interrupt Enable 17 1 MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Enable 16 1 MOSCXTS Main Crystal Oscillator Status Interrupt Enable 0 1 PCKRDY0 Programmable Clock Ready 0 Interrupt Enable 8 1 PCKRDY1 Programmable Clock Ready 1 Interrupt Enable 9 1 PCKRDY2 Programmable Clock Ready 2 Interrupt Enable 10 1 PCKRDY3 Programmable Clock Ready 3 Interrupt Enable 11 1 PCKRDY4 Programmable Clock Ready 4 Interrupt Enable 12 1 PCKRDY5 Programmable Clock Ready 5 Interrupt Enable 13 1 PCKRDY6 Programmable Clock Ready 6 Interrupt Enable 14 1 XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Enable 21 1 IMR Interrupt Mask Register 0x6C 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event Interrupt Mask 18 1 LOCKA PLLA Lock Interrupt Mask 1 1 LOCKU UTMI PLL Lock Interrupt Mask 6 1 MCKRDY Master Clock Ready Interrupt Mask 3 1 MOSCRCS Main RC Status Interrupt Mask 17 1 MOSCSELS Main Clock Source Oscillator Selection Status Interrupt Mask 16 1 MOSCXTS Main Crystal Oscillator Status Interrupt Mask 0 1 PCKRDY0 Programmable Clock Ready 0 Interrupt Mask 8 1 PCKRDY1 Programmable Clock Ready 1 Interrupt Mask 9 1 PCKRDY2 Programmable Clock Ready 2 Interrupt Mask 10 1 PCKRDY3 Programmable Clock Ready 3 Interrupt Mask 11 1 PCKRDY4 Programmable Clock Ready 4 Interrupt Mask 12 1 PCKRDY5 Programmable Clock Ready 5 Interrupt Mask 13 1 PCKRDY6 Programmable Clock Ready 6 Interrupt Mask 14 1 XT32KERR 32.768 kHz Crystal Oscillator Error Interrupt Mask 21 1 MCKR Master Clock Register 0x30 32 read-write n 0x0 0x0 CSS Master Clock Source Selection 0 2 CSSSelect SLOW_CLK Slow Clock is selected 0 MAIN_CLK Main Clock is selected 1 PLLA_CLK PLLA Clock is selected 2 UPLL_CLK Divided UPLL Clock is selected 3 MDIV Master Clock Division 8 2 MDIVSelect EQ_PCK Master Clock is Prescaler Output Clock divided by 1. 0 PCK_DIV2 Master Clock is Prescaler Output Clock divided by 2. 1 PCK_DIV4 Master Clock is Prescaler Output Clock divided by 4. 2 PCK_DIV3 Master Clock is Prescaler Output Clock divided by 3. 3 PRES Processor Clock Prescaler 4 3 PRESSelect CLK_1 Selected clock 0 CLK_2 Selected clock divided by 2 1 CLK_4 Selected clock divided by 4 2 CLK_8 Selected clock divided by 8 3 CLK_16 Selected clock divided by 16 4 CLK_32 Selected clock divided by 32 5 CLK_64 Selected clock divided by 64 6 CLK_3 Selected clock divided by 3 7 UPLLDIV2 UPLL Divider by 2 13 1 OCR Oscillator Calibration Register 0x110 32 read-write n 0x0 0x0 CAL12 Main RC Oscillator Calibration Bits for 12 MHz 16 7 CAL4 Main RC Oscillator Calibration Bits for 4 MHz 0 7 CAL8 Main RC Oscillator Calibration Bits for 8 MHz 8 7 SEL12 Selection of Main RC Oscillator Calibration Bits for 12 MHz 23 1 SEL4 Selection of Main RC Oscillator Calibration Bits for 4 MHz 7 1 SEL8 Selection of Main RC Oscillator Calibration Bits for 8 MHz 15 1 PCDR0 Peripheral Clock Disable Register 0 0x14 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Disable 10 1 PID11 Peripheral Clock 11 Disable 11 1 PID12 Peripheral Clock 12 Disable 12 1 PID13 Peripheral Clock 13 Disable 13 1 PID14 Peripheral Clock 14 Disable 14 1 PID15 Peripheral Clock 15 Disable 15 1 PID16 Peripheral Clock 16 Disable 16 1 PID17 Peripheral Clock 17 Disable 17 1 PID18 Peripheral Clock 18 Disable 18 1 PID19 Peripheral Clock 19 Disable 19 1 PID20 Peripheral Clock 20 Disable 20 1 PID21 Peripheral Clock 21 Disable 21 1 PID22 Peripheral Clock 22 Disable 22 1 PID23 Peripheral Clock 23 Disable 23 1 PID24 Peripheral Clock 24 Disable 24 1 PID25 Peripheral Clock 25 Disable 25 1 PID26 Peripheral Clock 26 Disable 26 1 PID27 Peripheral Clock 27 Disable 27 1 PID28 Peripheral Clock 28 Disable 28 1 PID29 Peripheral Clock 29 Disable 29 1 PID30 Peripheral Clock 30 Disable 30 1 PID31 Peripheral Clock 31 Disable 31 1 PID7 Peripheral Clock 7 Disable 7 1 PID8 Peripheral Clock 8 Disable 8 1 PID9 Peripheral Clock 9 Disable 9 1 PCDR1 Peripheral Clock Disable Register 1 0x104 32 write-only n 0x0 0x0 PID32 Peripheral Clock 32 Disable 0 1 PID33 Peripheral Clock 33 Disable 1 1 PID34 Peripheral Clock 34 Disable 2 1 PID35 Peripheral Clock 35 Disable 3 1 PID37 Peripheral Clock 37 Disable 5 1 PID39 Peripheral Clock 39 Disable 7 1 PID40 Peripheral Clock 40 Disable 8 1 PID41 Peripheral Clock 41 Disable 9 1 PID42 Peripheral Clock 42 Disable 10 1 PID43 Peripheral Clock 43 Disable 11 1 PID44 Peripheral Clock 44 Disable 12 1 PID45 Peripheral Clock 45 Disable 13 1 PID46 Peripheral Clock 46 Disable 14 1 PID47 Peripheral Clock 47 Disable 15 1 PID48 Peripheral Clock 48 Disable 16 1 PID49 Peripheral Clock 49 Disable 17 1 PID50 Peripheral Clock 50 Disable 18 1 PID51 Peripheral Clock 51 Disable 19 1 PID52 Peripheral Clock 52 Disable 20 1 PID53 Peripheral Clock 53 Disable 21 1 PID56 Peripheral Clock 56 Disable 24 1 PID57 Peripheral Clock 57 Disable 25 1 PID58 Peripheral Clock 58 Disable 26 1 PID59 Peripheral Clock 59 Disable 27 1 PID60 Peripheral Clock 60 Disable 28 1 PCER0 Peripheral Clock Enable Register 0 0x10 32 write-only n 0x0 0x0 PID10 Peripheral Clock 10 Enable 10 1 PID11 Peripheral Clock 11 Enable 11 1 PID12 Peripheral Clock 12 Enable 12 1 PID13 Peripheral Clock 13 Enable 13 1 PID14 Peripheral Clock 14 Enable 14 1 PID15 Peripheral Clock 15 Enable 15 1 PID16 Peripheral Clock 16 Enable 16 1 PID17 Peripheral Clock 17 Enable 17 1 PID18 Peripheral Clock 18 Enable 18 1 PID19 Peripheral Clock 19 Enable 19 1 PID20 Peripheral Clock 20 Enable 20 1 PID21 Peripheral Clock 21 Enable 21 1 PID22 Peripheral Clock 22 Enable 22 1 PID23 Peripheral Clock 23 Enable 23 1 PID24 Peripheral Clock 24 Enable 24 1 PID25 Peripheral Clock 25 Enable 25 1 PID26 Peripheral Clock 26 Enable 26 1 PID27 Peripheral Clock 27 Enable 27 1 PID28 Peripheral Clock 28 Enable 28 1 PID29 Peripheral Clock 29 Enable 29 1 PID30 Peripheral Clock 30 Enable 30 1 PID31 Peripheral Clock 31 Enable 31 1 PID7 Peripheral Clock 7 Enable 7 1 PID8 Peripheral Clock 8 Enable 8 1 PID9 Peripheral Clock 9 Enable 9 1 PCER1 Peripheral Clock Enable Register 1 0x100 32 write-only n 0x0 0x0 PID32 Peripheral Clock 32 Enable 0 1 PID33 Peripheral Clock 33 Enable 1 1 PID34 Peripheral Clock 34 Enable 2 1 PID35 Peripheral Clock 35 Enable 3 1 PID37 Peripheral Clock 37 Enable 5 1 PID39 Peripheral Clock 39 Enable 7 1 PID40 Peripheral Clock 40 Enable 8 1 PID41 Peripheral Clock 41 Enable 9 1 PID42 Peripheral Clock 42 Enable 10 1 PID43 Peripheral Clock 43 Enable 11 1 PID44 Peripheral Clock 44 Enable 12 1 PID45 Peripheral Clock 45 Enable 13 1 PID46 Peripheral Clock 46 Enable 14 1 PID47 Peripheral Clock 47 Enable 15 1 PID48 Peripheral Clock 48 Enable 16 1 PID49 Peripheral Clock 49 Enable 17 1 PID50 Peripheral Clock 50 Enable 18 1 PID51 Peripheral Clock 51 Enable 19 1 PID52 Peripheral Clock 52 Enable 20 1 PID53 Peripheral Clock 53 Enable 21 1 PID56 Peripheral Clock 56 Enable 24 1 PID57 Peripheral Clock 57 Enable 25 1 PID58 Peripheral Clock 58 Enable 26 1 PID59 Peripheral Clock 59 Enable 27 1 PID60 Peripheral Clock 60 Enable 28 1 PCK0 Programmable Clock 0 Register 0x40 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK Divided UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 8 read-write PCK1 Programmable Clock 0 Register 0x44 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK Divided UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 8 read-write PCK2 Programmable Clock 0 Register 0x48 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK Divided UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 8 read-write PCK3 Programmable Clock 0 Register 0x4C 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK Divided UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 8 read-write PCK4 Programmable Clock 0 Register 0x50 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK Divided UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 8 read-write PCK5 Programmable Clock 0 Register 0x54 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK Divided UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 8 read-write PCK6 Programmable Clock 0 Register 0x58 32 read-write n CSS Master Clock Source Selection 0 3 read-write SLOW_CLK Slow Clock is selected 0x0 MAIN_CLK Main Clock is selected 0x1 PLLA_CLK PLLA Clock is selected 0x2 UPLL_CLK Divided UPLL Clock is selected 0x3 MCK Master Clock is selected 0x4 PRES Programmable Clock Prescaler 4 8 read-write PCK[0] Programmable Clock Register 0x80 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0 MAIN_CLK MAINCK is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLLCKDIV is selected 3 MCK MCK is selected 4 PRES Programmable Clock Prescaler 4 8 PCK[1] Programmable Clock Register 0xC4 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0 MAIN_CLK MAINCK is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLLCKDIV is selected 3 MCK MCK is selected 4 PRES Programmable Clock Prescaler 4 8 PCK[2] Programmable Clock Register 0x10C 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0 MAIN_CLK MAINCK is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLLCKDIV is selected 3 MCK MCK is selected 4 PRES Programmable Clock Prescaler 4 8 PCK[3] Programmable Clock Register 0x158 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0 MAIN_CLK MAINCK is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLLCKDIV is selected 3 MCK MCK is selected 4 PRES Programmable Clock Prescaler 4 8 PCK[4] Programmable Clock Register 0x1A8 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0 MAIN_CLK MAINCK is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLLCKDIV is selected 3 MCK MCK is selected 4 PRES Programmable Clock Prescaler 4 8 PCK[5] Programmable Clock Register 0x1FC 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0 MAIN_CLK MAINCK is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLLCKDIV is selected 3 MCK MCK is selected 4 PRES Programmable Clock Prescaler 4 8 PCK[6] Programmable Clock Register 0x254 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0 MAIN_CLK MAINCK is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLLCKDIV is selected 3 MCK MCK is selected 4 PRES Programmable Clock Prescaler 4 8 PCK[7] Programmable Clock Register 0x2B0 32 read-write n 0x0 0x0 CSS Programmable Clock Source Selection 0 3 CSSSelect SLOW_CLK SLCK is selected 0 MAIN_CLK MAINCK is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLLCKDIV is selected 3 MCK MCK is selected 4 PRES Programmable Clock Prescaler 4 8 PCR Peripheral Control Register 0x10C 32 read-write n 0x0 0x0 CMD Command 12 1 EN Enable 28 1 GCLKCSS Generic Clock Source Selection 8 3 GCLKCSSSelect SLOW_CLK Slow clock is selected 0 MAIN_CLK Main clock is selected 1 PLLA_CLK PLLACK is selected 2 UPLL_CLK UPLL Clock is selected 3 MCK_CLK Master Clock is selected 4 GCLKDIV Generic Clock Division Ratio 20 8 GCLKEN Generic Clock Enable 29 1 PID Peripheral ID 0 7 PCSR0 Peripheral Clock Status Register 0 0x18 32 read-only n 0x0 0x0 PID10 Peripheral Clock 10 Status 10 1 PID11 Peripheral Clock 11 Status 11 1 PID12 Peripheral Clock 12 Status 12 1 PID13 Peripheral Clock 13 Status 13 1 PID14 Peripheral Clock 14 Status 14 1 PID15 Peripheral Clock 15 Status 15 1 PID16 Peripheral Clock 16 Status 16 1 PID17 Peripheral Clock 17 Status 17 1 PID18 Peripheral Clock 18 Status 18 1 PID19 Peripheral Clock 19 Status 19 1 PID20 Peripheral Clock 20 Status 20 1 PID21 Peripheral Clock 21 Status 21 1 PID22 Peripheral Clock 22 Status 22 1 PID23 Peripheral Clock 23 Status 23 1 PID24 Peripheral Clock 24 Status 24 1 PID25 Peripheral Clock 25 Status 25 1 PID26 Peripheral Clock 26 Status 26 1 PID27 Peripheral Clock 27 Status 27 1 PID28 Peripheral Clock 28 Status 28 1 PID29 Peripheral Clock 29 Status 29 1 PID30 Peripheral Clock 30 Status 30 1 PID31 Peripheral Clock 31 Status 31 1 PID7 Peripheral Clock 7 Status 7 1 PID8 Peripheral Clock 8 Status 8 1 PID9 Peripheral Clock 9 Status 9 1 PCSR1 Peripheral Clock Status Register 1 0x108 32 read-only n 0x0 0x0 PID32 Peripheral Clock 32 Status 0 1 PID33 Peripheral Clock 33 Status 1 1 PID34 Peripheral Clock 34 Status 2 1 PID35 Peripheral Clock 35 Status 3 1 PID37 Peripheral Clock 37 Status 5 1 PID39 Peripheral Clock 39 Status 7 1 PID40 Peripheral Clock 40 Status 8 1 PID41 Peripheral Clock 41 Status 9 1 PID42 Peripheral Clock 42 Status 10 1 PID43 Peripheral Clock 43 Status 11 1 PID44 Peripheral Clock 44 Status 12 1 PID45 Peripheral Clock 45 Status 13 1 PID46 Peripheral Clock 46 Status 14 1 PID47 Peripheral Clock 47 Status 15 1 PID48 Peripheral Clock 48 Status 16 1 PID49 Peripheral Clock 49 Status 17 1 PID50 Peripheral Clock 50 Status 18 1 PID51 Peripheral Clock 51 Status 19 1 PID52 Peripheral Clock 52 Status 20 1 PID53 Peripheral Clock 53 Status 21 1 PID56 Peripheral Clock 56 Status 24 1 PID57 Peripheral Clock 57 Status 25 1 PID58 Peripheral Clock 58 Status 26 1 PID59 Peripheral Clock 59 Status 27 1 PID60 Peripheral Clock 60 Status 28 1 PMMR PLL Maximum Multiplier Value Register 0x130 32 read-write n 0x0 0x0 PLLA_MMAX PLLA Maximum Allowed Multiplier Value 0 11 SCDR System Clock Disable Register 0x4 32 write-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Disable 8 1 PCK1 Programmable Clock 1 Output Disable 9 1 PCK2 Programmable Clock 2 Output Disable 10 1 PCK3 Programmable Clock 3 Output Disable 11 1 PCK4 Programmable Clock 4 Output Disable 12 1 PCK5 Programmable Clock 5 Output Disable 13 1 PCK6 Programmable Clock 6 Output Disable 14 1 USBCLK Disable USB FS Clock 5 1 SCER System Clock Enable Register 0x0 32 write-only n 0x0 0x0 PCK0 Programmable Clock 0 Output Enable 8 1 PCK1 Programmable Clock 1 Output Enable 9 1 PCK2 Programmable Clock 2 Output Enable 10 1 PCK3 Programmable Clock 3 Output Enable 11 1 PCK4 Programmable Clock 4 Output Enable 12 1 PCK5 Programmable Clock 5 Output Enable 13 1 PCK6 Programmable Clock 6 Output Enable 14 1 USBCLK Enable USB FS Clock 5 1 SCSR System Clock Status Register 0x8 32 read-only n 0x0 0x0 HCLKS HCLK Status 0 1 PCK0 Programmable Clock 0 Output Status 8 1 PCK1 Programmable Clock 1 Output Status 9 1 PCK2 Programmable Clock 2 Output Status 10 1 PCK3 Programmable Clock 3 Output Status 11 1 PCK4 Programmable Clock 4 Output Status 12 1 PCK5 Programmable Clock 5 Output Status 13 1 PCK6 Programmable Clock 6 Output Status 14 1 USBCLK USB FS Clock Status 5 1 SLPWK_AIPR SleepWalking Activity In Progress Register 0x144 32 read-only n 0x0 0x0 AIP Activity In Progress 0 1 SLPWK_ASR0 SleepWalking Activity Status Register 0 0x120 32 read-only n 0x0 0x0 PID10 Peripheral 10 Activity Status 10 1 PID11 Peripheral 11 Activity Status 11 1 PID12 Peripheral 12 Activity Status 12 1 PID13 Peripheral 13 Activity Status 13 1 PID14 Peripheral 14 Activity Status 14 1 PID15 Peripheral 15 Activity Status 15 1 PID16 Peripheral 16 Activity Status 16 1 PID17 Peripheral 17 Activity Status 17 1 PID18 Peripheral 18 Activity Status 18 1 PID19 Peripheral 19 Activity Status 19 1 PID20 Peripheral 20 Activity Status 20 1 PID21 Peripheral 21 Activity Status 21 1 PID22 Peripheral 22 Activity Status 22 1 PID23 Peripheral 23 Activity Status 23 1 PID24 Peripheral 24 Activity Status 24 1 PID25 Peripheral 25 Activity Status 25 1 PID26 Peripheral 26 Activity Status 26 1 PID27 Peripheral 27 Activity Status 27 1 PID28 Peripheral 28 Activity Status 28 1 PID29 Peripheral 29 Activity Status 29 1 PID30 Peripheral 30 Activity Status 30 1 PID31 Peripheral 31 Activity Status 31 1 PID7 Peripheral 7 Activity Status 7 1 PID8 Peripheral 8 Activity Status 8 1 PID9 Peripheral 9 Activity Status 9 1 SLPWK_ASR1 SleepWalking Activity Status Register 1 0x140 32 read-only n 0x0 0x0 PID32 Peripheral 32 Activity Status 0 1 PID33 Peripheral 33 Activity Status 1 1 PID34 Peripheral 34 Activity Status 2 1 PID35 Peripheral 35 Activity Status 3 1 PID37 Peripheral 37 Activity Status 5 1 PID39 Peripheral 39 Activity Status 7 1 PID40 Peripheral 40 Activity Status 8 1 PID41 Peripheral 41 Activity Status 9 1 PID42 Peripheral 42 Activity Status 10 1 PID43 Peripheral 43 Activity Status 11 1 PID44 Peripheral 44 Activity Status 12 1 PID45 Peripheral 45 Activity Status 13 1 PID46 Peripheral 46 Activity Status 14 1 PID47 Peripheral 47 Activity Status 15 1 PID48 Peripheral 48 Activity Status 16 1 PID49 Peripheral 49 Activity Status 17 1 PID50 Peripheral 50 Activity Status 18 1 PID51 Peripheral 51 Activity Status 19 1 PID52 Peripheral 52 Activity Status 20 1 PID53 Peripheral 53 Activity Status 21 1 PID56 Peripheral 56 Activity Status 24 1 PID57 Peripheral 57 Activity Status 25 1 PID58 Peripheral 58 Activity Status 26 1 PID59 Peripheral 59 Activity Status 27 1 PID60 Peripheral 60 Activity Status 28 1 SLPWK_DR0 SleepWalking Disable Register 0 0x118 32 write-only n 0x0 0x0 PID10 Peripheral 10 SleepWalking Disable 10 1 PID11 Peripheral 11 SleepWalking Disable 11 1 PID12 Peripheral 12 SleepWalking Disable 12 1 PID13 Peripheral 13 SleepWalking Disable 13 1 PID14 Peripheral 14 SleepWalking Disable 14 1 PID15 Peripheral 15 SleepWalking Disable 15 1 PID16 Peripheral 16 SleepWalking Disable 16 1 PID17 Peripheral 17 SleepWalking Disable 17 1 PID18 Peripheral 18 SleepWalking Disable 18 1 PID19 Peripheral 19 SleepWalking Disable 19 1 PID20 Peripheral 20 SleepWalking Disable 20 1 PID21 Peripheral 21 SleepWalking Disable 21 1 PID22 Peripheral 22 SleepWalking Disable 22 1 PID23 Peripheral 23 SleepWalking Disable 23 1 PID24 Peripheral 24 SleepWalking Disable 24 1 PID25 Peripheral 25 SleepWalking Disable 25 1 PID26 Peripheral 26 SleepWalking Disable 26 1 PID27 Peripheral 27 SleepWalking Disable 27 1 PID28 Peripheral 28 SleepWalking Disable 28 1 PID29 Peripheral 29 SleepWalking Disable 29 1 PID30 Peripheral 30 SleepWalking Disable 30 1 PID31 Peripheral 31 SleepWalking Disable 31 1 PID7 Peripheral 7 SleepWalking Disable 7 1 PID8 Peripheral 8 SleepWalking Disable 8 1 PID9 Peripheral 9 SleepWalking Disable 9 1 SLPWK_DR1 SleepWalking Disable Register 1 0x138 32 write-only n 0x0 0x0 PID32 Peripheral 32 SleepWalking Disable 0 1 PID33 Peripheral 33 SleepWalking Disable 1 1 PID34 Peripheral 34 SleepWalking Disable 2 1 PID35 Peripheral 35 SleepWalking Disable 3 1 PID37 Peripheral 37 SleepWalking Disable 5 1 PID39 Peripheral 39 SleepWalking Disable 7 1 PID40 Peripheral 40 SleepWalking Disable 8 1 PID41 Peripheral 41 SleepWalking Disable 9 1 PID42 Peripheral 42 SleepWalking Disable 10 1 PID43 Peripheral 43 SleepWalking Disable 11 1 PID44 Peripheral 44 SleepWalking Disable 12 1 PID45 Peripheral 45 SleepWalking Disable 13 1 PID46 Peripheral 46 SleepWalking Disable 14 1 PID47 Peripheral 47 SleepWalking Disable 15 1 PID48 Peripheral 48 SleepWalking Disable 16 1 PID49 Peripheral 49 SleepWalking Disable 17 1 PID50 Peripheral 50 SleepWalking Disable 18 1 PID51 Peripheral 51 SleepWalking Disable 19 1 PID52 Peripheral 52 SleepWalking Disable 20 1 PID53 Peripheral 53 SleepWalking Disable 21 1 PID56 Peripheral 56 SleepWalking Disable 24 1 PID57 Peripheral 57 SleepWalking Disable 25 1 PID58 Peripheral 58 SleepWalking Disable 26 1 PID59 Peripheral 59 SleepWalking Disable 27 1 PID60 Peripheral 60 SleepWalking Disable 28 1 SLPWK_ER0 SleepWalking Enable Register 0 0x114 32 write-only n 0x0 0x0 PID10 Peripheral 10 SleepWalking Enable 10 1 PID11 Peripheral 11 SleepWalking Enable 11 1 PID12 Peripheral 12 SleepWalking Enable 12 1 PID13 Peripheral 13 SleepWalking Enable 13 1 PID14 Peripheral 14 SleepWalking Enable 14 1 PID15 Peripheral 15 SleepWalking Enable 15 1 PID16 Peripheral 16 SleepWalking Enable 16 1 PID17 Peripheral 17 SleepWalking Enable 17 1 PID18 Peripheral 18 SleepWalking Enable 18 1 PID19 Peripheral 19 SleepWalking Enable 19 1 PID20 Peripheral 20 SleepWalking Enable 20 1 PID21 Peripheral 21 SleepWalking Enable 21 1 PID22 Peripheral 22 SleepWalking Enable 22 1 PID23 Peripheral 23 SleepWalking Enable 23 1 PID24 Peripheral 24 SleepWalking Enable 24 1 PID25 Peripheral 25 SleepWalking Enable 25 1 PID26 Peripheral 26 SleepWalking Enable 26 1 PID27 Peripheral 27 SleepWalking Enable 27 1 PID28 Peripheral 28 SleepWalking Enable 28 1 PID29 Peripheral 29 SleepWalking Enable 29 1 PID30 Peripheral 30 SleepWalking Enable 30 1 PID31 Peripheral 31 SleepWalking Enable 31 1 PID7 Peripheral 7 SleepWalking Enable 7 1 PID8 Peripheral 8 SleepWalking Enable 8 1 PID9 Peripheral 9 SleepWalking Enable 9 1 SLPWK_ER1 SleepWalking Enable Register 1 0x134 32 write-only n 0x0 0x0 PID32 Peripheral 32 SleepWalking Enable 0 1 PID33 Peripheral 33 SleepWalking Enable 1 1 PID34 Peripheral 34 SleepWalking Enable 2 1 PID35 Peripheral 35 SleepWalking Enable 3 1 PID37 Peripheral 37 SleepWalking Enable 5 1 PID39 Peripheral 39 SleepWalking Enable 7 1 PID40 Peripheral 40 SleepWalking Enable 8 1 PID41 Peripheral 41 SleepWalking Enable 9 1 PID42 Peripheral 42 SleepWalking Enable 10 1 PID43 Peripheral 43 SleepWalking Enable 11 1 PID44 Peripheral 44 SleepWalking Enable 12 1 PID45 Peripheral 45 SleepWalking Enable 13 1 PID46 Peripheral 46 SleepWalking Enable 14 1 PID47 Peripheral 47 SleepWalking Enable 15 1 PID48 Peripheral 48 SleepWalking Enable 16 1 PID49 Peripheral 49 SleepWalking Enable 17 1 PID50 Peripheral 50 SleepWalking Enable 18 1 PID51 Peripheral 51 SleepWalking Enable 19 1 PID52 Peripheral 52 SleepWalking Enable 20 1 PID53 Peripheral 53 SleepWalking Enable 21 1 PID56 Peripheral 56 SleepWalking Enable 24 1 PID57 Peripheral 57 SleepWalking Enable 25 1 PID58 Peripheral 58 SleepWalking Enable 26 1 PID59 Peripheral 59 SleepWalking Enable 27 1 PID60 Peripheral 60 SleepWalking Enable 28 1 SLPWK_SR0 SleepWalking Status Register 0 0x11C 32 read-only n 0x0 0x0 PID10 Peripheral 10 SleepWalking Status 10 1 PID11 Peripheral 11 SleepWalking Status 11 1 PID12 Peripheral 12 SleepWalking Status 12 1 PID13 Peripheral 13 SleepWalking Status 13 1 PID14 Peripheral 14 SleepWalking Status 14 1 PID15 Peripheral 15 SleepWalking Status 15 1 PID16 Peripheral 16 SleepWalking Status 16 1 PID17 Peripheral 17 SleepWalking Status 17 1 PID18 Peripheral 18 SleepWalking Status 18 1 PID19 Peripheral 19 SleepWalking Status 19 1 PID20 Peripheral 20 SleepWalking Status 20 1 PID21 Peripheral 21 SleepWalking Status 21 1 PID22 Peripheral 22 SleepWalking Status 22 1 PID23 Peripheral 23 SleepWalking Status 23 1 PID24 Peripheral 24 SleepWalking Status 24 1 PID25 Peripheral 25 SleepWalking Status 25 1 PID26 Peripheral 26 SleepWalking Status 26 1 PID27 Peripheral 27 SleepWalking Status 27 1 PID28 Peripheral 28 SleepWalking Status 28 1 PID29 Peripheral 29 SleepWalking Status 29 1 PID30 Peripheral 30 SleepWalking Status 30 1 PID31 Peripheral 31 SleepWalking Status 31 1 PID7 Peripheral 7 SleepWalking Status 7 1 PID8 Peripheral 8 SleepWalking Status 8 1 PID9 Peripheral 9 SleepWalking Status 9 1 SLPWK_SR1 SleepWalking Status Register 1 0x13C 32 read-only n 0x0 0x0 PID32 Peripheral 32 SleepWalking Status 0 1 PID33 Peripheral 33 SleepWalking Status 1 1 PID34 Peripheral 34 SleepWalking Status 2 1 PID35 Peripheral 35 SleepWalking Status 3 1 PID37 Peripheral 37 SleepWalking Status 5 1 PID39 Peripheral 39 SleepWalking Status 7 1 PID40 Peripheral 40 SleepWalking Status 8 1 PID41 Peripheral 41 SleepWalking Status 9 1 PID42 Peripheral 42 SleepWalking Status 10 1 PID43 Peripheral 43 SleepWalking Status 11 1 PID44 Peripheral 44 SleepWalking Status 12 1 PID45 Peripheral 45 SleepWalking Status 13 1 PID46 Peripheral 46 SleepWalking Status 14 1 PID47 Peripheral 47 SleepWalking Status 15 1 PID48 Peripheral 48 SleepWalking Status 16 1 PID49 Peripheral 49 SleepWalking Status 17 1 PID50 Peripheral 50 SleepWalking Status 18 1 PID51 Peripheral 51 SleepWalking Status 19 1 PID52 Peripheral 52 SleepWalking Status 20 1 PID53 Peripheral 53 SleepWalking Status 21 1 PID56 Peripheral 56 SleepWalking Status 24 1 PID57 Peripheral 57 SleepWalking Status 25 1 PID58 Peripheral 58 SleepWalking Status 26 1 PID59 Peripheral 59 SleepWalking Status 27 1 PID60 Peripheral 60 SleepWalking Status 28 1 SR Status Register 0x68 32 read-only n 0x0 0x0 CFDEV Clock Failure Detector Event 18 1 CFDS Clock Failure Detector Status 19 1 FOS Clock Failure Detector Fault Output Status 20 1 LOCKA PLLA Lock Status 1 1 LOCKU UTMI PLL Lock Status 6 1 MCKRDY Master Clock Status 3 1 MOSCRCS Main RC Oscillator Status 17 1 MOSCSELS Main Clock Source Oscillator Selection Status 16 1 MOSCXTS Main Crystal Oscillator Status 0 1 OSCSELS Slow Clock Source Oscillator Selection 7 1 PCKRDY0 Programmable Clock Ready 0 Status 8 1 PCKRDY1 Programmable Clock Ready 1 Status 9 1 PCKRDY2 Programmable Clock Ready 2 Status 10 1 PCKRDY3 Programmable Clock Ready 3 Status 11 1 PCKRDY4 Programmable Clock Ready 4 Status 12 1 PCKRDY5 Programmable Clock Ready 5 Status 13 1 PCKRDY6 Programmable Clock Ready 6 Status 14 1 XT32KERR Slow Crystal Oscillator Error 21 1 USB USB Clock Register 0x38 32 read-write n 0x0 0x0 USBDIV Divider for USB_48M 8 4 USBS USB Input Clock Selection 0 1 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5262659 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 PWM0 Pulse Width Modulation Controller 0 PWM 0x0 0x0 0x4000 registers n PWM0 31 CCNT0 PWM Channel Counter Register (ch_num = 0) 0x214 32 read-only n 0x0 CNT Channel Counter Register 0 24 read-only CCNT1 PWM Channel Counter Register (ch_num = 1) 0x234 32 read-only n 0x0 CNT Channel Counter Register 0 24 read-only CCNT2 PWM Channel Counter Register (ch_num = 2) 0x254 32 read-only n 0x0 CNT Channel Counter Register 0 24 read-only CCNT3 PWM Channel Counter Register (ch_num = 3) 0x274 32 read-only n 0x0 CNT Channel Counter Register 0 24 read-only CDTY0 PWM Channel Duty Cycle Register (ch_num = 0) 0x204 32 read-write n 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY1 PWM Channel Duty Cycle Register (ch_num = 1) 0x224 32 read-write n 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY2 PWM Channel Duty Cycle Register (ch_num = 2) 0x244 32 read-write n 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY3 PWM Channel Duty Cycle Register (ch_num = 3) 0x264 32 read-write n 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD0 PWM Channel Duty Cycle Update Register (ch_num = 0) 0x208 32 write-only n CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD1 PWM Channel Duty Cycle Update Register (ch_num = 1) 0x228 32 write-only n CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD2 PWM Channel Duty Cycle Update Register (ch_num = 2) 0x248 32 write-only n CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD3 PWM Channel Duty Cycle Update Register (ch_num = 3) 0x268 32 write-only n CDTYUPD Channel Duty-Cycle Update 0 24 write-only CLK PWM Clock Register 0x0 32 read-write n 0x0 DIVA CLKA Divide Factor 0 8 read-write CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 read-write CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 read-write CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PREB CLKB Source Clock Selection 24 4 read-write CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA CMPM0 PWM Comparison 0 Mode Register 0x138 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM1 PWM Comparison 1 Mode Register 0x148 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM2 PWM Comparison 2 Mode Register 0x158 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM3 PWM Comparison 3 Mode Register 0x168 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM4 PWM Comparison 4 Mode Register 0x178 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM5 PWM Comparison 5 Mode Register 0x188 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM6 PWM Comparison 6 Mode Register 0x198 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM7 PWM Comparison 7 Mode Register 0x1A8 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD0 PWM Comparison 0 Mode Update Register 0x13C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD1 PWM Comparison 1 Mode Update Register 0x14C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD2 PWM Comparison 2 Mode Update Register 0x15C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD3 PWM Comparison 3 Mode Update Register 0x16C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD4 PWM Comparison 4 Mode Update Register 0x17C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD5 PWM Comparison 5 Mode Update Register 0x18C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD6 PWM Comparison 6 Mode Update Register 0x19C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD7 PWM Comparison 7 Mode Update Register 0x1AC 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV0 PWM Comparison 0 Value Register 0x130 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV1 PWM Comparison 1 Value Register 0x140 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV2 PWM Comparison 2 Value Register 0x150 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV3 PWM Comparison 3 Value Register 0x160 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV4 PWM Comparison 4 Value Register 0x170 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV5 PWM Comparison 5 Value Register 0x180 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV6 PWM Comparison 6 Value Register 0x190 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV7 PWM Comparison 7 Value Register 0x1A0 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD0 PWM Comparison 0 Value Update Register 0x134 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD1 PWM Comparison 1 Value Update Register 0x144 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD2 PWM Comparison 2 Value Update Register 0x154 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD3 PWM Comparison 3 Value Update Register 0x164 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD4 PWM Comparison 4 Value Update Register 0x174 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD5 PWM Comparison 5 Value Update Register 0x184 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD6 PWM Comparison 6 Value Update Register 0x194 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD7 PWM Comparison 7 Value Update Register 0x1A4 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMR0 PWM Channel Mode Register (ch_num = 0) 0x200 32 read-write n 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write PPM Push-Pull Mode 19 1 read-write TCTS Timer Counter Trigger Selection 13 1 read-write UPDS Update Selection 11 1 read-write CMR1 PWM Channel Mode Register (ch_num = 1) 0x220 32 read-write n 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write PPM Push-Pull Mode 19 1 read-write TCTS Timer Counter Trigger Selection 13 1 read-write UPDS Update Selection 11 1 read-write CMR2 PWM Channel Mode Register (ch_num = 2) 0x240 32 read-write n 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write PPM Push-Pull Mode 19 1 read-write TCTS Timer Counter Trigger Selection 13 1 read-write UPDS Update Selection 11 1 read-write CMR3 PWM Channel Mode Register (ch_num = 3) 0x260 32 read-write n 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write PPM Push-Pull Mode 19 1 read-write TCTS Timer Counter Trigger Selection 13 1 read-write UPDS Update Selection 11 1 read-write CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CPRD0 PWM Channel Period Register (ch_num = 0) 0x20C 32 read-write n 0x0 CPRD Channel Period 0 24 read-write CPRD1 PWM Channel Period Register (ch_num = 1) 0x22C 32 read-write n 0x0 CPRD Channel Period 0 24 read-write CPRD2 PWM Channel Period Register (ch_num = 2) 0x24C 32 read-write n 0x0 CPRD Channel Period 0 24 read-write CPRD3 PWM Channel Period Register (ch_num = 3) 0x26C 32 read-write n 0x0 CPRD Channel Period 0 24 read-write CPRDUPD0 PWM Channel Period Update Register (ch_num = 0) 0x210 32 write-only n CPRDUPD Channel Period Update 0 24 write-only CPRDUPD1 PWM Channel Period Update Register (ch_num = 1) 0x230 32 write-only n CPRDUPD Channel Period Update 0 24 write-only CPRDUPD2 PWM Channel Period Update Register (ch_num = 2) 0x250 32 write-only n CPRDUPD Channel Period Update 0 24 write-only CPRDUPD3 PWM Channel Period Update Register (ch_num = 3) 0x270 32 write-only n CPRDUPD Channel Period Update 0 24 write-only DIS PWM Disable Register 0x8 32 write-only n CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only DMAR PWM DMA Register 0x24 32 write-only n DMADUTY Duty-Cycle Holding Register for DMA Access 0 24 write-only DT0 PWM Channel Dead Time Register (ch_num = 0) 0x218 32 read-write n 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT1 PWM Channel Dead Time Register (ch_num = 1) 0x238 32 read-write n 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT2 PWM Channel Dead Time Register (ch_num = 2) 0x258 32 read-write n 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT3 PWM Channel Dead Time Register (ch_num = 3) 0x278 32 read-write n 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD0 PWM Channel Dead Time Update Register (ch_num = 0) 0x21C 32 write-only n DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD1 PWM Channel Dead Time Update Register (ch_num = 1) 0x23C 32 write-only n DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD2 PWM Channel Dead Time Update Register (ch_num = 2) 0x25C 32 write-only n DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD3 PWM Channel Dead Time Update Register (ch_num = 3) 0x27C 32 write-only n DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only ELMR0 PWM Event Line 0 Mode Register 0x7C 32 read-write n CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ELMR1 PWM Event Line 0 Mode Register 0x80 32 read-write n CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ENA PWM Enable Register 0x4 32 write-only n CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only ETRG1 PWM External Trigger Register (trg_num = 1) 0x42C 32 read-write n 0x0 MAXCNT Maximum Counter value 0 24 read-write RFEN Recoverable Fault Enable 31 1 read-write TRGEDGE Edge Selection 28 1 read-write FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 read-write TRGMODE External Trigger Mode 24 2 read-write OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 read-write ETRG2 PWM External Trigger Register (trg_num = 2) 0x44C 32 read-write n 0x0 MAXCNT Maximum Counter value 0 24 read-write RFEN Recoverable Fault Enable 31 1 read-write TRGEDGE Edge Selection 28 1 read-write FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 read-write TRGMODE External Trigger Mode 24 2 read-write OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 read-write FCR PWM Fault Clear Register 0x64 32 write-only n FCLR Fault Clear 0 8 write-only FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 FFIL Fault Filtering 16 8 read-write FMOD Fault Activation Mode 8 8 read-write FPOL Fault Polarity 0 8 read-write FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 FPE0 Fault Protection Enable for channel 0 0 8 read-write FPE1 Fault Protection Enable for channel 1 8 8 read-write FPE2 Fault Protection Enable for channel 2 16 8 read-write FPE3 Fault Protection Enable for channel 3 24 8 read-write FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 read-write FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 read-write FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 read-write FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 read-write FPVL0 Fault Protection Value for PWML output on channel 0 16 1 read-write FPVL1 Fault Protection Value for PWML output on channel 1 17 1 read-write FPVL2 Fault Protection Value for PWML output on channel 2 18 1 read-write FPVL3 Fault Protection Value for PWML output on channel 3 19 1 read-write FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 read-write FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 read-write FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 read-write FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 read-write FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 read-write FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 read-write FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 read-write FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 read-write FSR PWM Fault Status Register 0x60 32 read-only n 0x0 FIV Fault Input Value 0 8 read-only FS Fault Status 8 8 read-only IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 write-only IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n CMPM0 Comparison 0 Match Interrupt Disable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Disable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Disable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Disable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Disable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Disable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Disable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Disable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Disable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Disable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Disable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Disable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Disable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Disable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Disable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Disable 23 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 write-only IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 write-only IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n CMPM0 Comparison 0 Match Interrupt Enable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Enable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Enable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Enable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Enable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Enable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Enable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Enable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Enable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Enable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Enable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Enable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Enable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Enable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Enable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Enable 23 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 write-only IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 read-only CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 read-only CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 read-only CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 read-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 read-only IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 read-only CMPM1 Comparison 1 Match Interrupt Mask 9 1 read-only CMPM2 Comparison 2 Match Interrupt Mask 10 1 read-only CMPM3 Comparison 3 Match Interrupt Mask 11 1 read-only CMPM4 Comparison 4 Match Interrupt Mask 12 1 read-only CMPM5 Comparison 5 Match Interrupt Mask 13 1 read-only CMPM6 Comparison 6 Match Interrupt Mask 14 1 read-only CMPM7 Comparison 7 Match Interrupt Mask 15 1 read-only CMPU0 Comparison 0 Update Interrupt Mask 16 1 read-only CMPU1 Comparison 1 Update Interrupt Mask 17 1 read-only CMPU2 Comparison 2 Update Interrupt Mask 18 1 read-only CMPU3 Comparison 3 Update Interrupt Mask 19 1 read-only CMPU4 Comparison 4 Update Interrupt Mask 20 1 read-only CMPU5 Comparison 5 Update Interrupt Mask 21 1 read-only CMPU6 Comparison 6 Update Interrupt Mask 22 1 read-only CMPU7 Comparison 7 Update Interrupt Mask 23 1 read-only UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 read-only WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 read-only ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 CHID0 Counter Event on Channel 0 0 1 read-only CHID1 Counter Event on Channel 1 1 1 read-only CHID2 Counter Event on Channel 2 2 1 read-only CHID3 Counter Event on Channel 3 3 1 read-only FCHID0 Fault Protection Trigger on Channel 0 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 19 1 read-only ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 CMPM0 Comparison 0 Match 8 1 read-only CMPM1 Comparison 1 Match 9 1 read-only CMPM2 Comparison 2 Match 10 1 read-only CMPM3 Comparison 3 Match 11 1 read-only CMPM4 Comparison 4 Match 12 1 read-only CMPM5 Comparison 5 Match 13 1 read-only CMPM6 Comparison 6 Match 14 1 read-only CMPM7 Comparison 7 Match 15 1 read-only CMPU0 Comparison 0 Update 16 1 read-only CMPU1 Comparison 1 Update 17 1 read-only CMPU2 Comparison 2 Update 18 1 read-only CMPU3 Comparison 3 Update 19 1 read-only CMPU4 Comparison 4 Update 20 1 read-only CMPU5 Comparison 5 Update 21 1 read-only CMPU6 Comparison 6 Update 22 1 read-only CMPU7 Comparison 7 Update 23 1 read-only UNRE Synchronous Channels Update Underrun Error 3 1 read-only WRDY Write Ready for Synchronous Channels Update 0 1 read-only LEBR1 PWM Leading-Edge Blanking Register (trg_num = 1) 0x430 32 read-write n 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 read-write PWMHFEN PWMH Falling Edge Enable 18 1 read-write PWMHREN PWMH Rising Edge Enable 19 1 read-write PWMLFEN PWML Falling Edge Enable 16 1 read-write PWMLREN PWML Rising Edge Enable 17 1 read-write LEBR2 PWM Leading-Edge Blanking Register (trg_num = 2) 0x450 32 read-write n 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 read-write PWMHFEN PWMH Falling Edge Enable 18 1 read-write PWMHREN PWMH Rising Edge Enable 19 1 read-write PWMLFEN PWML Falling Edge Enable 16 1 read-write PWMLREN PWML Rising Edge Enable 17 1 read-write OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 read-write OOVH1 Output Override Value for PWMH output of the channel 1 1 1 read-write OOVH2 Output Override Value for PWMH output of the channel 2 2 1 read-write OOVH3 Output Override Value for PWMH output of the channel 3 3 1 read-write OOVL0 Output Override Value for PWML output of the channel 0 16 1 read-write OOVL1 Output Override Value for PWML output of the channel 1 17 1 read-write OOVL2 Output Override Value for PWML output of the channel 2 18 1 read-write OOVL3 Output Override Value for PWML output of the channel 3 19 1 read-write OS PWM Output Selection Register 0x48 32 read-write n 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 read-write OSH1 Output Selection for PWMH output of the channel 1 1 1 read-write OSH2 Output Selection for PWMH output of the channel 2 2 1 read-write OSH3 Output Selection for PWMH output of the channel 3 3 1 read-write OSL0 Output Selection for PWML output of the channel 0 16 1 read-write OSL1 Output Selection for PWML output of the channel 1 17 1 read-write OSL2 Output Selection for PWML output of the channel 2 18 1 read-write OSL3 Output Selection for PWML output of the channel 3 19 1 read-write OSC PWM Output Selection Clear Register 0x50 32 write-only n OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSS PWM Output Selection Set Register 0x4C 32 write-only n OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSL3 Output Selection Set for PWML output of the channel 3 19 1 write-only OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 write-only PWM_PWM_CH_NUM[0]-PWM_CCNT PWM Channel Counter Register (ch_num = 0) 0x214 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_PWM_CH_NUM[0]-PWM_CDTY PWM Channel Duty Cycle Register (ch_num = 0) 0x204 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_PWM_CH_NUM[0]-PWM_CDTYUPD PWM Channel Duty Cycle Update Register (ch_num = 0) 0x208 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_PWM_CH_NUM[0]-PWM_CMR PWM Channel Mode Register (ch_num = 0) 0x200 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CES Counter Event Selection 10 1 CPOL Channel Polarity 9 1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0 MCK_DIV_2 Peripheral clock/2 1 MCK_DIV_1024 Peripheral clock/1024 10 CLKA Clock A 11 CLKB Clock B 12 MCK_DIV_4 Peripheral clock/4 2 MCK_DIV_8 Peripheral clock/8 3 MCK_DIV_16 Peripheral clock/16 4 MCK_DIV_32 Peripheral clock/32 5 MCK_DIV_64 Peripheral clock/64 6 MCK_DIV_128 Peripheral clock/128 7 MCK_DIV_256 Peripheral clock/256 8 MCK_DIV_512 Peripheral clock/512 9 DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 PWM_PWM_CH_NUM[0]-PWM_CPRD PWM Channel Period Register (ch_num = 0) 0x20C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_PWM_CH_NUM[0]-PWM_CPRDUPD PWM Channel Period Update Register (ch_num = 0) 0x210 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_PWM_CH_NUM[0]-PWM_DT PWM Channel Dead Time Register (ch_num = 0) 0x218 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_PWM_CH_NUM[0]-PWM_DTUPD PWM Channel Dead Time Update Register (ch_num = 0) 0x21C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT PWM Channel Counter Register (ch_num = 0) 0x434 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY PWM Channel Duty Cycle Register (ch_num = 0) 0x424 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD PWM Channel Duty Cycle Update Register (ch_num = 0) 0x428 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR PWM Channel Mode Register (ch_num = 0) 0x420 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CES Counter Event Selection 10 1 CPOL Channel Polarity 9 1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0 MCK_DIV_2 Peripheral clock/2 1 MCK_DIV_1024 Peripheral clock/1024 10 CLKA Clock A 11 CLKB Clock B 12 MCK_DIV_4 Peripheral clock/4 2 MCK_DIV_8 Peripheral clock/8 3 MCK_DIV_16 Peripheral clock/16 4 MCK_DIV_32 Peripheral clock/32 5 MCK_DIV_64 Peripheral clock/64 6 MCK_DIV_128 Peripheral clock/128 7 MCK_DIV_256 Peripheral clock/256 8 MCK_DIV_512 Peripheral clock/512 9 DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD PWM Channel Period Register (ch_num = 0) 0x42C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD PWM Channel Period Update Register (ch_num = 0) 0x430 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT PWM Channel Dead Time Register (ch_num = 0) 0x438 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD PWM Channel Dead Time Update Register (ch_num = 0) 0x43C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT PWM Channel Counter Register (ch_num = 0) 0x674 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY PWM Channel Duty Cycle Register (ch_num = 0) 0x664 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD PWM Channel Duty Cycle Update Register (ch_num = 0) 0x668 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR PWM Channel Mode Register (ch_num = 0) 0x660 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CES Counter Event Selection 10 1 CPOL Channel Polarity 9 1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0 MCK_DIV_2 Peripheral clock/2 1 MCK_DIV_1024 Peripheral clock/1024 10 CLKA Clock A 11 CLKB Clock B 12 MCK_DIV_4 Peripheral clock/4 2 MCK_DIV_8 Peripheral clock/8 3 MCK_DIV_16 Peripheral clock/16 4 MCK_DIV_32 Peripheral clock/32 5 MCK_DIV_64 Peripheral clock/64 6 MCK_DIV_128 Peripheral clock/128 7 MCK_DIV_256 Peripheral clock/256 8 MCK_DIV_512 Peripheral clock/512 9 DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD PWM Channel Period Register (ch_num = 0) 0x66C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD PWM Channel Period Update Register (ch_num = 0) 0x670 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT PWM Channel Dead Time Register (ch_num = 0) 0x678 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD PWM Channel Dead Time Update Register (ch_num = 0) 0x67C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT PWM Channel Counter Register (ch_num = 0) 0x8D4 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY PWM Channel Duty Cycle Register (ch_num = 0) 0x8C4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD PWM Channel Duty Cycle Update Register (ch_num = 0) 0x8C8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR PWM Channel Mode Register (ch_num = 0) 0x8C0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CES Counter Event Selection 10 1 CPOL Channel Polarity 9 1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0 MCK_DIV_2 Peripheral clock/2 1 MCK_DIV_1024 Peripheral clock/1024 10 CLKA Clock A 11 CLKB Clock B 12 MCK_DIV_4 Peripheral clock/4 2 MCK_DIV_8 Peripheral clock/8 3 MCK_DIV_16 Peripheral clock/16 4 MCK_DIV_32 Peripheral clock/32 5 MCK_DIV_64 Peripheral clock/64 6 MCK_DIV_128 Peripheral clock/128 7 MCK_DIV_256 Peripheral clock/256 8 MCK_DIV_512 Peripheral clock/512 9 DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD PWM Channel Period Register (ch_num = 0) 0x8CC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD PWM Channel Period Update Register (ch_num = 0) 0x8D0 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT PWM Channel Dead Time Register (ch_num = 0) 0x8D8 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD PWM Channel Dead Time Update Register (ch_num = 0) 0x8DC 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_PWM_CLK PWM Clock Register 0x0 32 read-write n 0x0 0x0 DIVA CLKA Divide Factor 0 8 DIVASelect CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 DIVBSelect CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 PREASelect CLK Peripheral clock 0 CLK_DIV2 Peripheral clock/2 1 CLK_DIV1024 Peripheral clock/1024 10 CLK_DIV4 Peripheral clock/4 2 CLK_DIV8 Peripheral clock/8 3 CLK_DIV16 Peripheral clock/16 4 CLK_DIV32 Peripheral clock/32 5 CLK_DIV64 Peripheral clock/64 6 CLK_DIV128 Peripheral clock/128 7 CLK_DIV256 Peripheral clock/256 8 CLK_DIV512 Peripheral clock/512 9 PREB CLKB Source Clock Selection 24 4 PREBSelect CLK Peripheral clock 0 CLK_DIV2 Peripheral clock/2 1 CLK_DIV1024 Peripheral clock/1024 10 CLK_DIV4 Peripheral clock/4 2 CLK_DIV8 Peripheral clock/8 3 CLK_DIV16 Peripheral clock/16 4 CLK_DIV32 Peripheral clock/32 5 CLK_DIV64 Peripheral clock/64 6 CLK_DIV128 Peripheral clock/128 7 CLK_DIV256 Peripheral clock/256 8 CLK_DIV512 Peripheral clock/512 9 PWM_PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x138 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x13C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x130 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x134 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x278 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x27C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x270 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x274 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x3C8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x3CC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x3C0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x3C4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x528 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x52C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x520 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x524 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x698 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x69C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x690 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x694 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x818 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x81C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x810 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x814 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x9A8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x9AC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x9A0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x9A4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0xB48 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0xB4C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0xB40 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0xB44 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_PWM_CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_PWM_CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_PWM_CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_PWM_DIS PWM Disable Register 0x8 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_PWM_DMAR PWM DMA Register 0x24 32 write-only n 0x0 0x0 DMADUTY Duty-Cycle Holding Register for DMA Access 0 24 PWM_PWM_ELMR[0] PWM Event Line 0 Mode Register 0 0xF8 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 PWM_PWM_ELMR[1] PWM Event Line 0 Mode Register 0 0x178 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 PWM_PWM_ENA PWM Enable Register 0x4 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_PWM_ETRG1 PWM External Trigger Register (trg_num = 1) 0x42C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0 MODE1 External PWM Reset Mode 1 MODE2 External PWM Start Mode 2 MODE3 Cycle-by-cycle Duty Mode 3 TRGSRC Trigger Source 30 1 PWM_PWM_ETRG2 PWM External Trigger Register (trg_num = 2) 0x44C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0 MODE1 External PWM Reset Mode 1 MODE2 External PWM Start Mode 2 MODE3 Cycle-by-cycle Duty Mode 3 TRGSRC Trigger Source 30 1 PWM_PWM_FCR PWM Fault Clear Register 0x64 32 write-only n 0x0 0x0 FCLR Fault Clear 0 8 PWM_PWM_FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 0x0 FFIL Fault Filtering 16 8 FMOD Fault Activation Mode 8 8 FPOL Fault Polarity 0 8 PWM_PWM_FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 0x0 FPE0 Fault Protection Enable for channel 0 0 8 FPE1 Fault Protection Enable for channel 1 8 8 FPE2 Fault Protection Enable for channel 2 16 8 FPE3 Fault Protection Enable for channel 3 24 8 PWM_PWM_FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 FPVL0 Fault Protection Value for PWML output on channel 0 16 1 FPVL1 Fault Protection Value for PWML output on channel 1 17 1 FPVL2 Fault Protection Value for PWML output on channel 2 18 1 FPVL3 Fault Protection Value for PWML output on channel 3 19 1 PWM_PWM_FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 PWM_PWM_FSR PWM Fault Status Register 0x60 32 read-only n 0x0 0x0 FIV Fault Input Value 0 8 FS Fault Status 8 8 PWM_PWM_IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 PWM_PWM_IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Disable 8 1 CMPM1 Comparison 1 Match Interrupt Disable 9 1 CMPM2 Comparison 2 Match Interrupt Disable 10 1 CMPM3 Comparison 3 Match Interrupt Disable 11 1 CMPM4 Comparison 4 Match Interrupt Disable 12 1 CMPM5 Comparison 5 Match Interrupt Disable 13 1 CMPM6 Comparison 6 Match Interrupt Disable 14 1 CMPM7 Comparison 7 Match Interrupt Disable 15 1 CMPU0 Comparison 0 Update Interrupt Disable 16 1 CMPU1 Comparison 1 Update Interrupt Disable 17 1 CMPU2 Comparison 2 Update Interrupt Disable 18 1 CMPU3 Comparison 3 Update Interrupt Disable 19 1 CMPU4 Comparison 4 Update Interrupt Disable 20 1 CMPU5 Comparison 5 Update Interrupt Disable 21 1 CMPU6 Comparison 6 Update Interrupt Disable 22 1 CMPU7 Comparison 7 Update Interrupt Disable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 PWM_PWM_IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 PWM_PWM_IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Enable 8 1 CMPM1 Comparison 1 Match Interrupt Enable 9 1 CMPM2 Comparison 2 Match Interrupt Enable 10 1 CMPM3 Comparison 3 Match Interrupt Enable 11 1 CMPM4 Comparison 4 Match Interrupt Enable 12 1 CMPM5 Comparison 5 Match Interrupt Enable 13 1 CMPM6 Comparison 6 Match Interrupt Enable 14 1 CMPM7 Comparison 7 Match Interrupt Enable 15 1 CMPU0 Comparison 0 Update Interrupt Enable 16 1 CMPU1 Comparison 1 Update Interrupt Enable 17 1 CMPU2 Comparison 2 Update Interrupt Enable 18 1 CMPU3 Comparison 3 Update Interrupt Enable 19 1 CMPU4 Comparison 4 Update Interrupt Enable 20 1 CMPU5 Comparison 5 Update Interrupt Enable 21 1 CMPU6 Comparison 6 Update Interrupt Enable 22 1 CMPU7 Comparison 7 Update Interrupt Enable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 PWM_PWM_IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 PWM_PWM_IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 CMPM1 Comparison 1 Match Interrupt Mask 9 1 CMPM2 Comparison 2 Match Interrupt Mask 10 1 CMPM3 Comparison 3 Match Interrupt Mask 11 1 CMPM4 Comparison 4 Match Interrupt Mask 12 1 CMPM5 Comparison 5 Match Interrupt Mask 13 1 CMPM6 Comparison 6 Match Interrupt Mask 14 1 CMPM7 Comparison 7 Match Interrupt Mask 15 1 CMPU0 Comparison 0 Update Interrupt Mask 16 1 CMPU1 Comparison 1 Update Interrupt Mask 17 1 CMPU2 Comparison 2 Update Interrupt Mask 18 1 CMPU3 Comparison 3 Update Interrupt Mask 19 1 CMPU4 Comparison 4 Update Interrupt Mask 20 1 CMPU5 Comparison 5 Update Interrupt Mask 21 1 CMPU6 Comparison 6 Update Interrupt Mask 22 1 CMPU7 Comparison 7 Update Interrupt Mask 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 PWM_PWM_ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 0 1 CHID1 Counter Event on Channel 1 1 1 CHID2 Counter Event on Channel 2 2 1 CHID3 Counter Event on Channel 3 3 1 FCHID0 Fault Protection Trigger on Channel 0 16 1 FCHID1 Fault Protection Trigger on Channel 1 17 1 FCHID2 Fault Protection Trigger on Channel 2 18 1 FCHID3 Fault Protection Trigger on Channel 3 19 1 PWM_PWM_ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match 8 1 CMPM1 Comparison 1 Match 9 1 CMPM2 Comparison 2 Match 10 1 CMPM3 Comparison 3 Match 11 1 CMPM4 Comparison 4 Match 12 1 CMPM5 Comparison 5 Match 13 1 CMPM6 Comparison 6 Match 14 1 CMPM7 Comparison 7 Match 15 1 CMPU0 Comparison 0 Update 16 1 CMPU1 Comparison 1 Update 17 1 CMPU2 Comparison 2 Update 18 1 CMPU3 Comparison 3 Update 19 1 CMPU4 Comparison 4 Update 20 1 CMPU5 Comparison 5 Update 21 1 CMPU6 Comparison 6 Update 22 1 CMPU7 Comparison 7 Update 23 1 UNRE Synchronous Channels Update Underrun Error 3 1 WRDY Write Ready for Synchronous Channels Update 0 1 PWM_PWM_LEBR1 PWM Leading-Edge Blanking Register (trg_num = 1) 0x430 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 PWM_PWM_LEBR2 PWM Leading-Edge Blanking Register (trg_num = 2) 0x450 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 PWM_PWM_OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 OOVH1 Output Override Value for PWMH output of the channel 1 1 1 OOVH2 Output Override Value for PWMH output of the channel 2 2 1 OOVH3 Output Override Value for PWMH output of the channel 3 3 1 OOVL0 Output Override Value for PWML output of the channel 0 16 1 OOVL1 Output Override Value for PWML output of the channel 1 17 1 OOVL2 Output Override Value for PWML output of the channel 2 18 1 OOVL3 Output Override Value for PWML output of the channel 3 19 1 PWM_PWM_OS PWM Output Selection Register 0x48 32 read-write n 0x0 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 OSH1 Output Selection for PWMH output of the channel 1 1 1 OSH2 Output Selection for PWMH output of the channel 2 2 1 OSH3 Output Selection for PWMH output of the channel 3 3 1 OSL0 Output Selection for PWML output of the channel 0 16 1 OSL1 Output Selection for PWML output of the channel 1 17 1 OSL2 Output Selection for PWML output of the channel 2 18 1 OSL3 Output Selection for PWML output of the channel 3 19 1 PWM_PWM_OSC PWM Output Selection Clear Register 0x50 32 write-only n 0x0 0x0 OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 PWM_PWM_OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n 0x0 0x0 OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 PWM_PWM_OSS PWM Output Selection Set Register 0x4C 32 write-only n 0x0 0x0 OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSL0 Output Selection Set for PWML output of the channel 0 16 1 OSSL1 Output Selection Set for PWML output of the channel 1 17 1 OSSL2 Output Selection Set for PWML output of the channel 2 18 1 OSSL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_PWM_OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n 0x0 0x0 OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_PWM_SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 0x0 PTRCS DMA Controller Transfer Request Comparison Selection 21 3 PTRM DMA Controller Transfer Request Mode 20 1 SYNC0 Synchronous Channel 0 0 1 SYNC1 Synchronous Channel 1 1 1 SYNC2 Synchronous Channel 2 2 1 SYNC3 Synchronous Channel 3 3 1 UPDM Synchronous Channels Update Mode 16 2 UPDMSelect MODE0 Manual write of double buffer registers and manual update of synchronous channels 0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 2 PWM_PWM_SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 PWM_PWM_SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 0x0 UPR Update Period 0 4 UPRCNT Update Period Counter 4 4 PWM_PWM_SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n 0x0 0x0 UPRUPD Update Period Update 0 4 PWM_PWM_SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 0x0 DOWN0 DOWN Count 16 1 DOWN1 DOWN Count 17 1 GCEN0 Gray Count ENable 0 1 GCEN1 Gray Count ENable 1 1 PWM_PWM_SR PWM Status Register 0xC 32 read-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_PWM_SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 0x0 SPRD Spread Spectrum Limit Value 0 24 SPRDM Spread Spectrum Counter Mode 24 1 PWM_PWM_SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n 0x0 0x0 SPRDUP Spread Spectrum Limit Value Update 0 24 PWM_PWM_WPCR PWM Write Protection Control Register 0xE4 32 write-only n 0x0 0x0 WPCMD Write Protection Command 0 2 WPCMDSelect DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 2 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 5265229 WPRG0 Write Protection Register Group 0 2 1 WPRG1 Write Protection Register Group 1 3 1 WPRG2 Write Protection Register Group 2 4 1 WPRG3 Write Protection Register Group 3 5 1 WPRG4 Write Protection Register Group 4 6 1 WPRG5 Write Protection Register Group 5 7 1 PWM_PWM_WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPHWS0 Write Protect HW Status 8 1 WPHWS1 Write Protect HW Status 9 1 WPHWS2 Write Protect HW Status 10 1 WPHWS3 Write Protect HW Status 11 1 WPHWS4 Write Protect HW Status 12 1 WPHWS5 Write Protect HW Status 13 1 WPSWS0 Write Protect SW Status 0 1 WPSWS1 Write Protect SW Status 1 1 WPSWS2 Write Protect SW Status 2 1 WPSWS3 Write Protect SW Status 3 1 WPSWS4 Write Protect SW Status 4 1 WPSWS5 Write Protect SW Status 5 1 WPVS Write Protect Violation Status 7 1 WPVSRC Write Protect Violation Source 16 16 SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 PTRCS DMA Controller Transfer Request Comparison Selection 21 3 read-write PTRM DMA Controller Transfer Request Mode 20 1 read-write SYNC0 Synchronous Channel 0 0 1 read-write SYNC1 Synchronous Channel 1 1 1 read-write SYNC2 Synchronous Channel 2 2 1 read-write SYNC3 Synchronous Channel 3 3 1 read-write UPDM Synchronous Channels Update Mode 16 2 read-write MODE0 Manual write of double buffer registers and manual update of synchronous channels 0x0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 0x1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 0x2 SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 read-write SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 UPR Update Period 0 4 read-write UPRCNT Update Period Counter 4 4 read-write SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n UPRUPD Update Period Update 0 4 write-only SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 DOWN0 DOWN Count 16 1 read-write DOWN1 DOWN Count 17 1 read-write GCEN0 Gray Count ENable 0 1 read-write GCEN1 Gray Count ENable 1 1 read-write SR PWM Status Register 0xC 32 read-only n 0x0 CHID0 Channel ID 0 1 read-only CHID1 Channel ID 1 1 read-only CHID2 Channel ID 2 1 read-only CHID3 Channel ID 3 1 read-only SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 SPRD Spread Spectrum Limit Value 0 24 read-write SPRDM Spread Spectrum Counter Mode 24 1 read-write SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n SPRDUP Spread Spectrum Limit Value Update 0 24 write-only WPCR PWM Write Protection Control Register 0xE4 32 write-only n WPCMD Write Protection Command 0 2 write-only DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 0x2 WPKEY Write Protection Key 8 24 write-only PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 0x50574D WPRG0 Write Protection Register Group 0 2 1 write-only WPRG1 Write Protection Register Group 1 3 1 write-only WPRG2 Write Protection Register Group 2 4 1 write-only WPRG3 Write Protection Register Group 3 5 1 write-only WPRG4 Write Protection Register Group 4 6 1 write-only WPRG5 Write Protection Register Group 5 7 1 write-only WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 WPHWS0 Write Protect HW Status 8 1 read-only WPHWS1 Write Protect HW Status 9 1 read-only WPHWS2 Write Protect HW Status 10 1 read-only WPHWS3 Write Protect HW Status 11 1 read-only WPHWS4 Write Protect HW Status 12 1 read-only WPHWS5 Write Protect HW Status 13 1 read-only WPSWS0 Write Protect SW Status 0 1 read-only WPSWS1 Write Protect SW Status 1 1 read-only WPSWS2 Write Protect SW Status 2 1 read-only WPSWS3 Write Protect SW Status 3 1 read-only WPSWS4 Write Protect SW Status 4 1 read-only WPSWS5 Write Protect SW Status 5 1 read-only WPVS Write Protect Violation Status 7 1 read-only WPVSRC Write Protect Violation Source 16 16 read-only PWM1 Pulse Width Modulation Controller 1 PWM 0x0 0x0 0x4000 registers n PWM1 60 CCNT0 PWM Channel Counter Register (ch_num = 0) 0x214 32 read-only n 0x0 CNT Channel Counter Register 0 24 read-only CCNT1 PWM Channel Counter Register (ch_num = 1) 0x234 32 read-only n 0x0 CNT Channel Counter Register 0 24 read-only CCNT2 PWM Channel Counter Register (ch_num = 2) 0x254 32 read-only n 0x0 CNT Channel Counter Register 0 24 read-only CCNT3 PWM Channel Counter Register (ch_num = 3) 0x274 32 read-only n 0x0 CNT Channel Counter Register 0 24 read-only CDTY0 PWM Channel Duty Cycle Register (ch_num = 0) 0x204 32 read-write n 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY1 PWM Channel Duty Cycle Register (ch_num = 1) 0x224 32 read-write n 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY2 PWM Channel Duty Cycle Register (ch_num = 2) 0x244 32 read-write n 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTY3 PWM Channel Duty Cycle Register (ch_num = 3) 0x264 32 read-write n 0x0 CDTY Channel Duty-Cycle 0 24 read-write CDTYUPD0 PWM Channel Duty Cycle Update Register (ch_num = 0) 0x208 32 write-only n CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD1 PWM Channel Duty Cycle Update Register (ch_num = 1) 0x228 32 write-only n CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD2 PWM Channel Duty Cycle Update Register (ch_num = 2) 0x248 32 write-only n CDTYUPD Channel Duty-Cycle Update 0 24 write-only CDTYUPD3 PWM Channel Duty Cycle Update Register (ch_num = 3) 0x268 32 write-only n CDTYUPD Channel Duty-Cycle Update 0 24 write-only CLK PWM Clock Register 0x0 32 read-write n 0x0 DIVA CLKA Divide Factor 0 8 read-write CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 read-write CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 read-write CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA PREB CLKB Source Clock Selection 24 4 read-write CLK Peripheral clock 0x0 CLK_DIV2 Peripheral clock/2 0x1 CLK_DIV4 Peripheral clock/4 0x2 CLK_DIV8 Peripheral clock/8 0x3 CLK_DIV16 Peripheral clock/16 0x4 CLK_DIV32 Peripheral clock/32 0x5 CLK_DIV64 Peripheral clock/64 0x6 CLK_DIV128 Peripheral clock/128 0x7 CLK_DIV256 Peripheral clock/256 0x8 CLK_DIV512 Peripheral clock/512 0x9 CLK_DIV1024 Peripheral clock/1024 0xA CMPM0 PWM Comparison 0 Mode Register 0x138 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM1 PWM Comparison 1 Mode Register 0x148 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM2 PWM Comparison 2 Mode Register 0x158 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM3 PWM Comparison 3 Mode Register 0x168 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM4 PWM Comparison 4 Mode Register 0x178 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM5 PWM Comparison 5 Mode Register 0x188 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM6 PWM Comparison 6 Mode Register 0x198 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPM7 PWM Comparison 7 Mode Register 0x1A8 32 read-write n 0x0 CEN Comparison x Enable 0 1 read-write CPR Comparison x Period 8 4 read-write CPRCNT Comparison x Period Counter 12 4 read-write CTR Comparison x Trigger 4 4 read-write CUPR Comparison x Update Period 16 4 read-write CUPRCNT Comparison x Update Period Counter 20 4 read-write CMPMUPD0 PWM Comparison 0 Mode Update Register 0x13C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD1 PWM Comparison 1 Mode Update Register 0x14C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD2 PWM Comparison 2 Mode Update Register 0x15C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD3 PWM Comparison 3 Mode Update Register 0x16C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD4 PWM Comparison 4 Mode Update Register 0x17C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD5 PWM Comparison 5 Mode Update Register 0x18C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD6 PWM Comparison 6 Mode Update Register 0x19C 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPMUPD7 PWM Comparison 7 Mode Update Register 0x1AC 32 write-only n CENUPD Comparison x Enable Update 0 1 write-only CPRUPD Comparison x Period Update 8 4 write-only CTRUPD Comparison x Trigger Update 4 4 write-only CUPRUPD Comparison x Update Period Update 16 4 write-only CMPV0 PWM Comparison 0 Value Register 0x130 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV1 PWM Comparison 1 Value Register 0x140 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV2 PWM Comparison 2 Value Register 0x150 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV3 PWM Comparison 3 Value Register 0x160 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV4 PWM Comparison 4 Value Register 0x170 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV5 PWM Comparison 5 Value Register 0x180 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV6 PWM Comparison 6 Value Register 0x190 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPV7 PWM Comparison 7 Value Register 0x1A0 32 read-write n 0x0 CV Comparison x Value 0 24 read-write CVM Comparison x Value Mode 24 1 read-write CMPVUPD0 PWM Comparison 0 Value Update Register 0x134 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD1 PWM Comparison 1 Value Update Register 0x144 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD2 PWM Comparison 2 Value Update Register 0x154 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD3 PWM Comparison 3 Value Update Register 0x164 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD4 PWM Comparison 4 Value Update Register 0x174 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD5 PWM Comparison 5 Value Update Register 0x184 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD6 PWM Comparison 6 Value Update Register 0x194 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMPVUPD7 PWM Comparison 7 Value Update Register 0x1A4 32 write-only n CVMUPD Comparison x Value Mode Update 24 1 write-only CVUPD Comparison x Value Update 0 24 write-only CMR0 PWM Channel Mode Register (ch_num = 0) 0x200 32 read-write n 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write PPM Push-Pull Mode 19 1 read-write TCTS Timer Counter Trigger Selection 13 1 read-write UPDS Update Selection 11 1 read-write CMR1 PWM Channel Mode Register (ch_num = 1) 0x220 32 read-write n 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write PPM Push-Pull Mode 19 1 read-write TCTS Timer Counter Trigger Selection 13 1 read-write UPDS Update Selection 11 1 read-write CMR2 PWM Channel Mode Register (ch_num = 2) 0x240 32 read-write n 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write PPM Push-Pull Mode 19 1 read-write TCTS Timer Counter Trigger Selection 13 1 read-write UPDS Update Selection 11 1 read-write CMR3 PWM Channel Mode Register (ch_num = 3) 0x260 32 read-write n 0x0 CALG Channel Alignment 8 1 read-write CES Counter Event Selection 10 1 read-write CPOL Channel Polarity 9 1 read-write CPRE Channel Pre-scaler 0 4 read-write MCK Peripheral clock 0x0 MCK_DIV_2 Peripheral clock/2 0x1 MCK_DIV_4 Peripheral clock/4 0x2 MCK_DIV_8 Peripheral clock/8 0x3 MCK_DIV_16 Peripheral clock/16 0x4 MCK_DIV_32 Peripheral clock/32 0x5 MCK_DIV_64 Peripheral clock/64 0x6 MCK_DIV_128 Peripheral clock/128 0x7 MCK_DIV_256 Peripheral clock/256 0x8 MCK_DIV_512 Peripheral clock/512 0x9 MCK_DIV_1024 Peripheral clock/1024 0xA CLKA Clock A 0xB CLKB Clock B 0xC DPOLI Disabled Polarity Inverted 12 1 read-write DTE Dead-Time Generator Enable 16 1 read-write DTHI Dead-Time PWMHx Output Inverted 17 1 read-write DTLI Dead-Time PWMLx Output Inverted 18 1 read-write PPM Push-Pull Mode 19 1 read-write TCTS Timer Counter Trigger Selection 13 1 read-write UPDS Update Selection 11 1 read-write CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n CPOLINVUP Channel Polarity Inversion Update 13 1 write-only CPOLUP Channel Polarity Update 9 1 write-only CPRD0 PWM Channel Period Register (ch_num = 0) 0x20C 32 read-write n 0x0 CPRD Channel Period 0 24 read-write CPRD1 PWM Channel Period Register (ch_num = 1) 0x22C 32 read-write n 0x0 CPRD Channel Period 0 24 read-write CPRD2 PWM Channel Period Register (ch_num = 2) 0x24C 32 read-write n 0x0 CPRD Channel Period 0 24 read-write CPRD3 PWM Channel Period Register (ch_num = 3) 0x26C 32 read-write n 0x0 CPRD Channel Period 0 24 read-write CPRDUPD0 PWM Channel Period Update Register (ch_num = 0) 0x210 32 write-only n CPRDUPD Channel Period Update 0 24 write-only CPRDUPD1 PWM Channel Period Update Register (ch_num = 1) 0x230 32 write-only n CPRDUPD Channel Period Update 0 24 write-only CPRDUPD2 PWM Channel Period Update Register (ch_num = 2) 0x250 32 write-only n CPRDUPD Channel Period Update 0 24 write-only CPRDUPD3 PWM Channel Period Update Register (ch_num = 3) 0x270 32 write-only n CPRDUPD Channel Period Update 0 24 write-only DIS PWM Disable Register 0x8 32 write-only n CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only DMAR PWM DMA Register 0x24 32 write-only n DMADUTY Duty-Cycle Holding Register for DMA Access 0 24 write-only DT0 PWM Channel Dead Time Register (ch_num = 0) 0x218 32 read-write n 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT1 PWM Channel Dead Time Register (ch_num = 1) 0x238 32 read-write n 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT2 PWM Channel Dead Time Register (ch_num = 2) 0x258 32 read-write n 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DT3 PWM Channel Dead Time Register (ch_num = 3) 0x278 32 read-write n 0x0 DTH Dead-Time Value for PWMHx Output 0 16 read-write DTL Dead-Time Value for PWMLx Output 16 16 read-write DTUPD0 PWM Channel Dead Time Update Register (ch_num = 0) 0x21C 32 write-only n DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD1 PWM Channel Dead Time Update Register (ch_num = 1) 0x23C 32 write-only n DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD2 PWM Channel Dead Time Update Register (ch_num = 2) 0x25C 32 write-only n DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only DTUPD3 PWM Channel Dead Time Update Register (ch_num = 3) 0x27C 32 write-only n DTHUPD Dead-Time Value Update for PWMHx Output 0 16 write-only DTLUPD Dead-Time Value Update for PWMLx Output 16 16 write-only ELMR0 PWM Event Line 0 Mode Register 0x7C 32 read-write n CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ELMR1 PWM Event Line 0 Mode Register 0x80 32 read-write n CSEL0 Comparison 0 Selection 0 1 read-write CSEL1 Comparison 1 Selection 1 1 read-write CSEL2 Comparison 2 Selection 2 1 read-write CSEL3 Comparison 3 Selection 3 1 read-write CSEL4 Comparison 4 Selection 4 1 read-write CSEL5 Comparison 5 Selection 5 1 read-write CSEL6 Comparison 6 Selection 6 1 read-write CSEL7 Comparison 7 Selection 7 1 read-write ENA PWM Enable Register 0x4 32 write-only n CHID0 Channel ID 0 1 write-only CHID1 Channel ID 1 1 write-only CHID2 Channel ID 2 1 write-only CHID3 Channel ID 3 1 write-only ETRG1 PWM External Trigger Register (trg_num = 1) 0x42C 32 read-write n 0x0 MAXCNT Maximum Counter value 0 24 read-write RFEN Recoverable Fault Enable 31 1 read-write TRGEDGE Edge Selection 28 1 read-write FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 read-write TRGMODE External Trigger Mode 24 2 read-write OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 read-write ETRG2 PWM External Trigger Register (trg_num = 2) 0x44C 32 read-write n 0x0 MAXCNT Maximum Counter value 0 24 read-write RFEN Recoverable Fault Enable 31 1 read-write TRGEDGE Edge Selection 28 1 read-write FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 read-write TRGMODE External Trigger Mode 24 2 read-write OFF External trigger is not enabled. 0x0 MODE1 External PWM Reset Mode 0x1 MODE2 External PWM Start Mode 0x2 MODE3 Cycle-by-cycle Duty Mode 0x3 TRGSRC Trigger Source 30 1 read-write FCR PWM Fault Clear Register 0x64 32 write-only n FCLR Fault Clear 0 8 write-only FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 FFIL Fault Filtering 16 8 read-write FMOD Fault Activation Mode 8 8 read-write FPOL Fault Polarity 0 8 read-write FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 FPE0 Fault Protection Enable for channel 0 0 8 read-write FPE1 Fault Protection Enable for channel 1 8 8 read-write FPE2 Fault Protection Enable for channel 2 16 8 read-write FPE3 Fault Protection Enable for channel 3 24 8 read-write FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 read-write FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 read-write FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 read-write FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 read-write FPVL0 Fault Protection Value for PWML output on channel 0 16 1 read-write FPVL1 Fault Protection Value for PWML output on channel 1 17 1 read-write FPVL2 Fault Protection Value for PWML output on channel 2 18 1 read-write FPVL3 Fault Protection Value for PWML output on channel 3 19 1 read-write FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 read-write FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 read-write FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 read-write FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 read-write FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 read-write FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 read-write FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 read-write FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 read-write FSR PWM Fault Status Register 0x60 32 read-only n 0x0 FIV Fault Input Value 0 8 read-only FS Fault Status 8 8 read-only IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 write-only IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n CMPM0 Comparison 0 Match Interrupt Disable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Disable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Disable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Disable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Disable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Disable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Disable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Disable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Disable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Disable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Disable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Disable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Disable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Disable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Disable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Disable 23 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 write-only IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 write-only CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 write-only CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 write-only CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 write-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 write-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 write-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 write-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 write-only IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n CMPM0 Comparison 0 Match Interrupt Enable 8 1 write-only CMPM1 Comparison 1 Match Interrupt Enable 9 1 write-only CMPM2 Comparison 2 Match Interrupt Enable 10 1 write-only CMPM3 Comparison 3 Match Interrupt Enable 11 1 write-only CMPM4 Comparison 4 Match Interrupt Enable 12 1 write-only CMPM5 Comparison 5 Match Interrupt Enable 13 1 write-only CMPM6 Comparison 6 Match Interrupt Enable 14 1 write-only CMPM7 Comparison 7 Match Interrupt Enable 15 1 write-only CMPU0 Comparison 0 Update Interrupt Enable 16 1 write-only CMPU1 Comparison 1 Update Interrupt Enable 17 1 write-only CMPU2 Comparison 2 Update Interrupt Enable 18 1 write-only CMPU3 Comparison 3 Update Interrupt Enable 19 1 write-only CMPU4 Comparison 4 Update Interrupt Enable 20 1 write-only CMPU5 Comparison 5 Update Interrupt Enable 21 1 write-only CMPU6 Comparison 6 Update Interrupt Enable 22 1 write-only CMPU7 Comparison 7 Update Interrupt Enable 23 1 write-only UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 write-only WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 write-only IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 read-only CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 read-only CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 read-only CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 read-only FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 read-only IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 read-only CMPM1 Comparison 1 Match Interrupt Mask 9 1 read-only CMPM2 Comparison 2 Match Interrupt Mask 10 1 read-only CMPM3 Comparison 3 Match Interrupt Mask 11 1 read-only CMPM4 Comparison 4 Match Interrupt Mask 12 1 read-only CMPM5 Comparison 5 Match Interrupt Mask 13 1 read-only CMPM6 Comparison 6 Match Interrupt Mask 14 1 read-only CMPM7 Comparison 7 Match Interrupt Mask 15 1 read-only CMPU0 Comparison 0 Update Interrupt Mask 16 1 read-only CMPU1 Comparison 1 Update Interrupt Mask 17 1 read-only CMPU2 Comparison 2 Update Interrupt Mask 18 1 read-only CMPU3 Comparison 3 Update Interrupt Mask 19 1 read-only CMPU4 Comparison 4 Update Interrupt Mask 20 1 read-only CMPU5 Comparison 5 Update Interrupt Mask 21 1 read-only CMPU6 Comparison 6 Update Interrupt Mask 22 1 read-only CMPU7 Comparison 7 Update Interrupt Mask 23 1 read-only UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 read-only WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 read-only ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 CHID0 Counter Event on Channel 0 0 1 read-only CHID1 Counter Event on Channel 1 1 1 read-only CHID2 Counter Event on Channel 2 2 1 read-only CHID3 Counter Event on Channel 3 3 1 read-only FCHID0 Fault Protection Trigger on Channel 0 16 1 read-only FCHID1 Fault Protection Trigger on Channel 1 17 1 read-only FCHID2 Fault Protection Trigger on Channel 2 18 1 read-only FCHID3 Fault Protection Trigger on Channel 3 19 1 read-only ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 CMPM0 Comparison 0 Match 8 1 read-only CMPM1 Comparison 1 Match 9 1 read-only CMPM2 Comparison 2 Match 10 1 read-only CMPM3 Comparison 3 Match 11 1 read-only CMPM4 Comparison 4 Match 12 1 read-only CMPM5 Comparison 5 Match 13 1 read-only CMPM6 Comparison 6 Match 14 1 read-only CMPM7 Comparison 7 Match 15 1 read-only CMPU0 Comparison 0 Update 16 1 read-only CMPU1 Comparison 1 Update 17 1 read-only CMPU2 Comparison 2 Update 18 1 read-only CMPU3 Comparison 3 Update 19 1 read-only CMPU4 Comparison 4 Update 20 1 read-only CMPU5 Comparison 5 Update 21 1 read-only CMPU6 Comparison 6 Update 22 1 read-only CMPU7 Comparison 7 Update 23 1 read-only UNRE Synchronous Channels Update Underrun Error 3 1 read-only WRDY Write Ready for Synchronous Channels Update 0 1 read-only LEBR1 PWM Leading-Edge Blanking Register (trg_num = 1) 0x430 32 read-write n 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 read-write PWMHFEN PWMH Falling Edge Enable 18 1 read-write PWMHREN PWMH Rising Edge Enable 19 1 read-write PWMLFEN PWML Falling Edge Enable 16 1 read-write PWMLREN PWML Rising Edge Enable 17 1 read-write LEBR2 PWM Leading-Edge Blanking Register (trg_num = 2) 0x450 32 read-write n 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 read-write PWMHFEN PWMH Falling Edge Enable 18 1 read-write PWMHREN PWMH Rising Edge Enable 19 1 read-write PWMLFEN PWML Falling Edge Enable 16 1 read-write PWMLREN PWML Rising Edge Enable 17 1 read-write OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 read-write OOVH1 Output Override Value for PWMH output of the channel 1 1 1 read-write OOVH2 Output Override Value for PWMH output of the channel 2 2 1 read-write OOVH3 Output Override Value for PWMH output of the channel 3 3 1 read-write OOVL0 Output Override Value for PWML output of the channel 0 16 1 read-write OOVL1 Output Override Value for PWML output of the channel 1 17 1 read-write OOVL2 Output Override Value for PWML output of the channel 2 18 1 read-write OOVL3 Output Override Value for PWML output of the channel 3 19 1 read-write OS PWM Output Selection Register 0x48 32 read-write n 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 read-write OSH1 Output Selection for PWMH output of the channel 1 1 1 read-write OSH2 Output Selection for PWMH output of the channel 2 2 1 read-write OSH3 Output Selection for PWMH output of the channel 3 3 1 read-write OSL0 Output Selection for PWML output of the channel 0 16 1 read-write OSL1 Output Selection for PWML output of the channel 1 17 1 read-write OSL2 Output Selection for PWML output of the channel 2 18 1 read-write OSL3 Output Selection for PWML output of the channel 3 19 1 read-write OSC PWM Output Selection Clear Register 0x50 32 write-only n OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 write-only OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 write-only OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 write-only OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 write-only OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 write-only OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 write-only OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 write-only OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 write-only OSS PWM Output Selection Set Register 0x4C 32 write-only n OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSL3 Output Selection Set for PWML output of the channel 3 19 1 write-only OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 write-only OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 write-only OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 write-only OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 write-only OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 write-only OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 write-only OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 write-only OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 write-only PWM_PWM_CH_NUM[0]-PWM_CCNT PWM Channel Counter Register (ch_num = 0) 0x214 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_PWM_CH_NUM[0]-PWM_CDTY PWM Channel Duty Cycle Register (ch_num = 0) 0x204 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_PWM_CH_NUM[0]-PWM_CDTYUPD PWM Channel Duty Cycle Update Register (ch_num = 0) 0x208 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_PWM_CH_NUM[0]-PWM_CMR PWM Channel Mode Register (ch_num = 0) 0x200 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CES Counter Event Selection 10 1 CPOL Channel Polarity 9 1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0 MCK_DIV_2 Peripheral clock/2 1 MCK_DIV_1024 Peripheral clock/1024 10 CLKA Clock A 11 CLKB Clock B 12 MCK_DIV_4 Peripheral clock/4 2 MCK_DIV_8 Peripheral clock/8 3 MCK_DIV_16 Peripheral clock/16 4 MCK_DIV_32 Peripheral clock/32 5 MCK_DIV_64 Peripheral clock/64 6 MCK_DIV_128 Peripheral clock/128 7 MCK_DIV_256 Peripheral clock/256 8 MCK_DIV_512 Peripheral clock/512 9 DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 PWM_PWM_CH_NUM[0]-PWM_CPRD PWM Channel Period Register (ch_num = 0) 0x20C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_PWM_CH_NUM[0]-PWM_CPRDUPD PWM Channel Period Update Register (ch_num = 0) 0x210 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_PWM_CH_NUM[0]-PWM_DT PWM Channel Dead Time Register (ch_num = 0) 0x218 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_PWM_CH_NUM[0]-PWM_DTUPD PWM Channel Dead Time Update Register (ch_num = 0) 0x21C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT PWM Channel Counter Register (ch_num = 0) 0x434 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY PWM Channel Duty Cycle Register (ch_num = 0) 0x424 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD PWM Channel Duty Cycle Update Register (ch_num = 0) 0x428 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR PWM Channel Mode Register (ch_num = 0) 0x420 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CES Counter Event Selection 10 1 CPOL Channel Polarity 9 1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0 MCK_DIV_2 Peripheral clock/2 1 MCK_DIV_1024 Peripheral clock/1024 10 CLKA Clock A 11 CLKB Clock B 12 MCK_DIV_4 Peripheral clock/4 2 MCK_DIV_8 Peripheral clock/8 3 MCK_DIV_16 Peripheral clock/16 4 MCK_DIV_32 Peripheral clock/32 5 MCK_DIV_64 Peripheral clock/64 6 MCK_DIV_128 Peripheral clock/128 7 MCK_DIV_256 Peripheral clock/256 8 MCK_DIV_512 Peripheral clock/512 9 DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD PWM Channel Period Register (ch_num = 0) 0x42C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD PWM Channel Period Update Register (ch_num = 0) 0x430 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT PWM Channel Dead Time Register (ch_num = 0) 0x438 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD PWM Channel Dead Time Update Register (ch_num = 0) 0x43C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT PWM Channel Counter Register (ch_num = 0) 0x674 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY PWM Channel Duty Cycle Register (ch_num = 0) 0x664 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD PWM Channel Duty Cycle Update Register (ch_num = 0) 0x668 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR PWM Channel Mode Register (ch_num = 0) 0x660 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CES Counter Event Selection 10 1 CPOL Channel Polarity 9 1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0 MCK_DIV_2 Peripheral clock/2 1 MCK_DIV_1024 Peripheral clock/1024 10 CLKA Clock A 11 CLKB Clock B 12 MCK_DIV_4 Peripheral clock/4 2 MCK_DIV_8 Peripheral clock/8 3 MCK_DIV_16 Peripheral clock/16 4 MCK_DIV_32 Peripheral clock/32 5 MCK_DIV_64 Peripheral clock/64 6 MCK_DIV_128 Peripheral clock/128 7 MCK_DIV_256 Peripheral clock/256 8 MCK_DIV_512 Peripheral clock/512 9 DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD PWM Channel Period Register (ch_num = 0) 0x66C 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD PWM Channel Period Update Register (ch_num = 0) 0x670 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT PWM Channel Dead Time Register (ch_num = 0) 0x678 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD PWM Channel Dead Time Update Register (ch_num = 0) 0x67C 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CCNT PWM Channel Counter Register (ch_num = 0) 0x8D4 32 read-only n 0x0 0x0 CNT Channel Counter Register 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTY PWM Channel Duty Cycle Register (ch_num = 0) 0x8C4 32 read-write n 0x0 0x0 CDTY Channel Duty-Cycle 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CDTYUPD PWM Channel Duty Cycle Update Register (ch_num = 0) 0x8C8 32 write-only n 0x0 0x0 CDTYUPD Channel Duty-Cycle Update 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CMR PWM Channel Mode Register (ch_num = 0) 0x8C0 32 read-write n 0x0 0x0 CALG Channel Alignment 8 1 CES Counter Event Selection 10 1 CPOL Channel Polarity 9 1 CPRE Channel Pre-scaler 0 4 CPRESelect MCK Peripheral clock 0 MCK_DIV_2 Peripheral clock/2 1 MCK_DIV_1024 Peripheral clock/1024 10 CLKA Clock A 11 CLKB Clock B 12 MCK_DIV_4 Peripheral clock/4 2 MCK_DIV_8 Peripheral clock/8 3 MCK_DIV_16 Peripheral clock/16 4 MCK_DIV_32 Peripheral clock/32 5 MCK_DIV_64 Peripheral clock/64 6 MCK_DIV_128 Peripheral clock/128 7 MCK_DIV_256 Peripheral clock/256 8 MCK_DIV_512 Peripheral clock/512 9 DPOLI Disabled Polarity Inverted 12 1 DTE Dead-Time Generator Enable 16 1 DTHI Dead-Time PWMHx Output Inverted 17 1 DTLI Dead-Time PWMLx Output Inverted 18 1 PPM Push-Pull Mode 19 1 TCTS Timer Counter Trigger Selection 13 1 UPDS Update Selection 11 1 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRD PWM Channel Period Register (ch_num = 0) 0x8CC 32 read-write n 0x0 0x0 CPRD Channel Period 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_CPRDUPD PWM Channel Period Update Register (ch_num = 0) 0x8D0 32 write-only n 0x0 0x0 CPRDUPD Channel Period Update 0 24 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DT PWM Channel Dead Time Register (ch_num = 0) 0x8D8 32 read-write n 0x0 0x0 DTH Dead-Time Value for PWMHx Output 0 16 DTL Dead-Time Value for PWMLx Output 16 16 PWM_PWM_CH_NUM[3]-PWM_CH_NUM[2]-PWM_CH_NUM[1]-PWM_CH_NUM[0]-PWM_DTUPD PWM Channel Dead Time Update Register (ch_num = 0) 0x8DC 32 write-only n 0x0 0x0 DTHUPD Dead-Time Value Update for PWMHx Output 0 16 DTLUPD Dead-Time Value Update for PWMLx Output 16 16 PWM_PWM_CLK PWM Clock Register 0x0 32 read-write n 0x0 0x0 DIVA CLKA Divide Factor 0 8 DIVASelect CLKA_POFF CLKA clock is turned off 0 PREA CLKA clock is clock selected by PREA 1 DIVB CLKB Divide Factor 16 8 DIVBSelect CLKB_POFF CLKB clock is turned off 0 PREB CLKB clock is clock selected by PREB 1 PREA CLKA Source Clock Selection 8 4 PREASelect CLK Peripheral clock 0 CLK_DIV2 Peripheral clock/2 1 CLK_DIV1024 Peripheral clock/1024 10 CLK_DIV4 Peripheral clock/4 2 CLK_DIV8 Peripheral clock/8 3 CLK_DIV16 Peripheral clock/16 4 CLK_DIV32 Peripheral clock/32 5 CLK_DIV64 Peripheral clock/64 6 CLK_DIV128 Peripheral clock/128 7 CLK_DIV256 Peripheral clock/256 8 CLK_DIV512 Peripheral clock/512 9 PREB CLKB Source Clock Selection 24 4 PREBSelect CLK Peripheral clock 0 CLK_DIV2 Peripheral clock/2 1 CLK_DIV1024 Peripheral clock/1024 10 CLK_DIV4 Peripheral clock/4 2 CLK_DIV8 Peripheral clock/8 3 CLK_DIV16 Peripheral clock/16 4 CLK_DIV32 Peripheral clock/32 5 CLK_DIV64 Peripheral clock/64 6 CLK_DIV128 Peripheral clock/128 7 CLK_DIV256 Peripheral clock/256 8 CLK_DIV512 Peripheral clock/512 9 PWM_PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x138 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x13C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x130 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x134 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x278 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x27C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x270 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x274 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x3C8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x3CC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x3C0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x3C4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x528 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x52C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x520 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x524 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x698 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x69C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x690 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x694 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x818 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x81C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x810 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x814 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0x9A8 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0x9AC 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0x9A0 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0x9A4 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPM PWM Comparison 0 Mode Register 0xB48 32 read-write n 0x0 0x0 CEN Comparison x Enable 0 1 CPR Comparison x Period 8 4 CPRCNT Comparison x Period Counter 12 4 CTR Comparison x Trigger 4 4 CUPR Comparison x Update Period 16 4 CUPRCNT Comparison x Update Period Counter 20 4 PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPMUPD PWM Comparison 0 Mode Update Register 0xB4C 32 write-only n 0x0 0x0 CENUPD Comparison x Enable Update 0 1 CPRUPD Comparison x Period Update 8 4 CTRUPD Comparison x Trigger Update 4 4 CUPRUPD Comparison x Update Period Update 16 4 PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPV PWM Comparison 0 Value Register 0xB40 32 read-write n 0x0 0x0 CV Comparison x Value 0 24 CVM Comparison x Value Mode 24 1 PWM_PWM_CMP[7]-PWM_CMP[6]-PWM_CMP[5]-PWM_CMP[4]-PWM_CMP[3]-PWM_CMP[2]-PWM_CMP[1]-PWM_CMP[0]-PWM_CMPVUPD PWM Comparison 0 Value Update Register 0xB44 32 write-only n 0x0 0x0 CVMUPD Comparison x Value Mode Update 24 1 CVUPD Comparison x Value Update 0 24 PWM_PWM_CMUPD0 PWM Channel Mode Update Register (ch_num = 0) 0x400 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_PWM_CMUPD1 PWM Channel Mode Update Register (ch_num = 1) 0x420 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_PWM_CMUPD2 PWM Channel Mode Update Register (ch_num = 2) 0x440 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_PWM_CMUPD3 PWM Channel Mode Update Register (ch_num = 3) 0x460 32 write-only n 0x0 0x0 CPOLINVUP Channel Polarity Inversion Update 13 1 CPOLUP Channel Polarity Update 9 1 PWM_PWM_DIS PWM Disable Register 0x8 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_PWM_DMAR PWM DMA Register 0x24 32 write-only n 0x0 0x0 DMADUTY Duty-Cycle Holding Register for DMA Access 0 24 PWM_PWM_ELMR[0] PWM Event Line 0 Mode Register 0 0xF8 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 PWM_PWM_ELMR[1] PWM Event Line 0 Mode Register 0 0x178 32 read-write n 0x0 0x0 CSEL0 Comparison 0 Selection 0 1 CSEL1 Comparison 1 Selection 1 1 CSEL2 Comparison 2 Selection 2 1 CSEL3 Comparison 3 Selection 3 1 CSEL4 Comparison 4 Selection 4 1 CSEL5 Comparison 5 Selection 5 1 CSEL6 Comparison 6 Selection 6 1 CSEL7 Comparison 7 Selection 7 1 PWM_PWM_ENA PWM Enable Register 0x4 32 write-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_PWM_ETRG1 PWM External Trigger Register (trg_num = 1) 0x42C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0 MODE1 External PWM Reset Mode 1 MODE2 External PWM Start Mode 2 MODE3 Cycle-by-cycle Duty Mode 3 TRGSRC Trigger Source 30 1 PWM_PWM_ETRG2 PWM External Trigger Register (trg_num = 2) 0x44C 32 read-write n 0x0 0x0 MAXCNT Maximum Counter value 0 24 RFEN Recoverable Fault Enable 31 1 TRGEDGE Edge Selection 28 1 TRGEDGESelect FALLING_ZERO TRGMODE = 1: TRGINx event detection on falling edge.TRGMODE = 2, 3: TRGINx active level is 0 0 RISING_ONE TRGMODE = 1: TRGINx event detection on rising edge.TRGMODE = 2, 3: TRGINx active level is 1 1 TRGFILT Filtered input 29 1 TRGMODE External Trigger Mode 24 2 TRGMODESelect OFF External trigger is not enabled. 0 MODE1 External PWM Reset Mode 1 MODE2 External PWM Start Mode 2 MODE3 Cycle-by-cycle Duty Mode 3 TRGSRC Trigger Source 30 1 PWM_PWM_FCR PWM Fault Clear Register 0x64 32 write-only n 0x0 0x0 FCLR Fault Clear 0 8 PWM_PWM_FMR PWM Fault Mode Register 0x5C 32 read-write n 0x0 0x0 FFIL Fault Filtering 16 8 FMOD Fault Activation Mode 8 8 FPOL Fault Polarity 0 8 PWM_PWM_FPE PWM Fault Protection Enable Register 0x6C 32 read-write n 0x0 0x0 FPE0 Fault Protection Enable for channel 0 0 8 FPE1 Fault Protection Enable for channel 1 8 8 FPE2 Fault Protection Enable for channel 2 16 8 FPE3 Fault Protection Enable for channel 3 24 8 PWM_PWM_FPV1 PWM Fault Protection Value Register 1 0x68 32 read-write n 0x0 0x0 FPVH0 Fault Protection Value for PWMH output on channel 0 0 1 FPVH1 Fault Protection Value for PWMH output on channel 1 1 1 FPVH2 Fault Protection Value for PWMH output on channel 2 2 1 FPVH3 Fault Protection Value for PWMH output on channel 3 3 1 FPVL0 Fault Protection Value for PWML output on channel 0 16 1 FPVL1 Fault Protection Value for PWML output on channel 1 17 1 FPVL2 Fault Protection Value for PWML output on channel 2 18 1 FPVL3 Fault Protection Value for PWML output on channel 3 19 1 PWM_PWM_FPV2 PWM Fault Protection Value 2 Register 0xC0 32 read-write n 0x0 0x0 FPZH0 Fault Protection to Hi-Z for PWMH output on channel 0 0 1 FPZH1 Fault Protection to Hi-Z for PWMH output on channel 1 1 1 FPZH2 Fault Protection to Hi-Z for PWMH output on channel 2 2 1 FPZH3 Fault Protection to Hi-Z for PWMH output on channel 3 3 1 FPZL0 Fault Protection to Hi-Z for PWML output on channel 0 16 1 FPZL1 Fault Protection to Hi-Z for PWML output on channel 1 17 1 FPZL2 Fault Protection to Hi-Z for PWML output on channel 2 18 1 FPZL3 Fault Protection to Hi-Z for PWML output on channel 3 19 1 PWM_PWM_FSR PWM Fault Status Register 0x60 32 read-only n 0x0 0x0 FIV Fault Input Value 0 8 FS Fault Status 8 8 PWM_PWM_IDR1 PWM Interrupt Disable Register 1 0x14 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Disable 0 1 CHID1 Counter Event on Channel 1 Interrupt Disable 1 1 CHID2 Counter Event on Channel 2 Interrupt Disable 2 1 CHID3 Counter Event on Channel 3 Interrupt Disable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Disable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Disable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Disable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Disable 19 1 PWM_PWM_IDR2 PWM Interrupt Disable Register 2 0x38 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Disable 8 1 CMPM1 Comparison 1 Match Interrupt Disable 9 1 CMPM2 Comparison 2 Match Interrupt Disable 10 1 CMPM3 Comparison 3 Match Interrupt Disable 11 1 CMPM4 Comparison 4 Match Interrupt Disable 12 1 CMPM5 Comparison 5 Match Interrupt Disable 13 1 CMPM6 Comparison 6 Match Interrupt Disable 14 1 CMPM7 Comparison 7 Match Interrupt Disable 15 1 CMPU0 Comparison 0 Update Interrupt Disable 16 1 CMPU1 Comparison 1 Update Interrupt Disable 17 1 CMPU2 Comparison 2 Update Interrupt Disable 18 1 CMPU3 Comparison 3 Update Interrupt Disable 19 1 CMPU4 Comparison 4 Update Interrupt Disable 20 1 CMPU5 Comparison 5 Update Interrupt Disable 21 1 CMPU6 Comparison 6 Update Interrupt Disable 22 1 CMPU7 Comparison 7 Update Interrupt Disable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Disable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Disable 0 1 PWM_PWM_IER1 PWM Interrupt Enable Register 1 0x10 32 write-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Enable 0 1 CHID1 Counter Event on Channel 1 Interrupt Enable 1 1 CHID2 Counter Event on Channel 2 Interrupt Enable 2 1 CHID3 Counter Event on Channel 3 Interrupt Enable 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Enable 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Enable 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Enable 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Enable 19 1 PWM_PWM_IER2 PWM Interrupt Enable Register 2 0x34 32 write-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Enable 8 1 CMPM1 Comparison 1 Match Interrupt Enable 9 1 CMPM2 Comparison 2 Match Interrupt Enable 10 1 CMPM3 Comparison 3 Match Interrupt Enable 11 1 CMPM4 Comparison 4 Match Interrupt Enable 12 1 CMPM5 Comparison 5 Match Interrupt Enable 13 1 CMPM6 Comparison 6 Match Interrupt Enable 14 1 CMPM7 Comparison 7 Match Interrupt Enable 15 1 CMPU0 Comparison 0 Update Interrupt Enable 16 1 CMPU1 Comparison 1 Update Interrupt Enable 17 1 CMPU2 Comparison 2 Update Interrupt Enable 18 1 CMPU3 Comparison 3 Update Interrupt Enable 19 1 CMPU4 Comparison 4 Update Interrupt Enable 20 1 CMPU5 Comparison 5 Update Interrupt Enable 21 1 CMPU6 Comparison 6 Update Interrupt Enable 22 1 CMPU7 Comparison 7 Update Interrupt Enable 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Enable 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Enable 0 1 PWM_PWM_IMR1 PWM Interrupt Mask Register 1 0x18 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 Interrupt Mask 0 1 CHID1 Counter Event on Channel 1 Interrupt Mask 1 1 CHID2 Counter Event on Channel 2 Interrupt Mask 2 1 CHID3 Counter Event on Channel 3 Interrupt Mask 3 1 FCHID0 Fault Protection Trigger on Channel 0 Interrupt Mask 16 1 FCHID1 Fault Protection Trigger on Channel 1 Interrupt Mask 17 1 FCHID2 Fault Protection Trigger on Channel 2 Interrupt Mask 18 1 FCHID3 Fault Protection Trigger on Channel 3 Interrupt Mask 19 1 PWM_PWM_IMR2 PWM Interrupt Mask Register 2 0x3C 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match Interrupt Mask 8 1 CMPM1 Comparison 1 Match Interrupt Mask 9 1 CMPM2 Comparison 2 Match Interrupt Mask 10 1 CMPM3 Comparison 3 Match Interrupt Mask 11 1 CMPM4 Comparison 4 Match Interrupt Mask 12 1 CMPM5 Comparison 5 Match Interrupt Mask 13 1 CMPM6 Comparison 6 Match Interrupt Mask 14 1 CMPM7 Comparison 7 Match Interrupt Mask 15 1 CMPU0 Comparison 0 Update Interrupt Mask 16 1 CMPU1 Comparison 1 Update Interrupt Mask 17 1 CMPU2 Comparison 2 Update Interrupt Mask 18 1 CMPU3 Comparison 3 Update Interrupt Mask 19 1 CMPU4 Comparison 4 Update Interrupt Mask 20 1 CMPU5 Comparison 5 Update Interrupt Mask 21 1 CMPU6 Comparison 6 Update Interrupt Mask 22 1 CMPU7 Comparison 7 Update Interrupt Mask 23 1 UNRE Synchronous Channels Update Underrun Error Interrupt Mask 3 1 WRDY Write Ready for Synchronous Channels Update Interrupt Mask 0 1 PWM_PWM_ISR1 PWM Interrupt Status Register 1 0x1C 32 read-only n 0x0 0x0 CHID0 Counter Event on Channel 0 0 1 CHID1 Counter Event on Channel 1 1 1 CHID2 Counter Event on Channel 2 2 1 CHID3 Counter Event on Channel 3 3 1 FCHID0 Fault Protection Trigger on Channel 0 16 1 FCHID1 Fault Protection Trigger on Channel 1 17 1 FCHID2 Fault Protection Trigger on Channel 2 18 1 FCHID3 Fault Protection Trigger on Channel 3 19 1 PWM_PWM_ISR2 PWM Interrupt Status Register 2 0x40 32 read-only n 0x0 0x0 CMPM0 Comparison 0 Match 8 1 CMPM1 Comparison 1 Match 9 1 CMPM2 Comparison 2 Match 10 1 CMPM3 Comparison 3 Match 11 1 CMPM4 Comparison 4 Match 12 1 CMPM5 Comparison 5 Match 13 1 CMPM6 Comparison 6 Match 14 1 CMPM7 Comparison 7 Match 15 1 CMPU0 Comparison 0 Update 16 1 CMPU1 Comparison 1 Update 17 1 CMPU2 Comparison 2 Update 18 1 CMPU3 Comparison 3 Update 19 1 CMPU4 Comparison 4 Update 20 1 CMPU5 Comparison 5 Update 21 1 CMPU6 Comparison 6 Update 22 1 CMPU7 Comparison 7 Update 23 1 UNRE Synchronous Channels Update Underrun Error 3 1 WRDY Write Ready for Synchronous Channels Update 0 1 PWM_PWM_LEBR1 PWM Leading-Edge Blanking Register (trg_num = 1) 0x430 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 PWM_PWM_LEBR2 PWM Leading-Edge Blanking Register (trg_num = 2) 0x450 32 read-write n 0x0 0x0 LEBDELAY Leading-Edge Blanking Delay for TRGINx 0 7 PWMHFEN PWMH Falling Edge Enable 18 1 PWMHREN PWMH Rising Edge Enable 19 1 PWMLFEN PWML Falling Edge Enable 16 1 PWMLREN PWML Rising Edge Enable 17 1 PWM_PWM_OOV PWM Output Override Value Register 0x44 32 read-write n 0x0 0x0 OOVH0 Output Override Value for PWMH output of the channel 0 0 1 OOVH1 Output Override Value for PWMH output of the channel 1 1 1 OOVH2 Output Override Value for PWMH output of the channel 2 2 1 OOVH3 Output Override Value for PWMH output of the channel 3 3 1 OOVL0 Output Override Value for PWML output of the channel 0 16 1 OOVL1 Output Override Value for PWML output of the channel 1 17 1 OOVL2 Output Override Value for PWML output of the channel 2 18 1 OOVL3 Output Override Value for PWML output of the channel 3 19 1 PWM_PWM_OS PWM Output Selection Register 0x48 32 read-write n 0x0 0x0 OSH0 Output Selection for PWMH output of the channel 0 0 1 OSH1 Output Selection for PWMH output of the channel 1 1 1 OSH2 Output Selection for PWMH output of the channel 2 2 1 OSH3 Output Selection for PWMH output of the channel 3 3 1 OSL0 Output Selection for PWML output of the channel 0 16 1 OSL1 Output Selection for PWML output of the channel 1 17 1 OSL2 Output Selection for PWML output of the channel 2 18 1 OSL3 Output Selection for PWML output of the channel 3 19 1 PWM_PWM_OSC PWM Output Selection Clear Register 0x50 32 write-only n 0x0 0x0 OSCH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCL3 Output Selection Clear for PWML output of the channel 3 19 1 PWM_PWM_OSCUPD PWM Output Selection Clear Update Register 0x58 32 write-only n 0x0 0x0 OSCUPH0 Output Selection Clear for PWMH output of the channel 0 0 1 OSCUPH1 Output Selection Clear for PWMH output of the channel 1 1 1 OSCUPH2 Output Selection Clear for PWMH output of the channel 2 2 1 OSCUPH3 Output Selection Clear for PWMH output of the channel 3 3 1 OSCUPL0 Output Selection Clear for PWML output of the channel 0 16 1 OSCUPL1 Output Selection Clear for PWML output of the channel 1 17 1 OSCUPL2 Output Selection Clear for PWML output of the channel 2 18 1 OSCUPL3 Output Selection Clear for PWML output of the channel 3 19 1 PWM_PWM_OSS PWM Output Selection Set Register 0x4C 32 write-only n 0x0 0x0 OSSH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSL0 Output Selection Set for PWML output of the channel 0 16 1 OSSL1 Output Selection Set for PWML output of the channel 1 17 1 OSSL2 Output Selection Set for PWML output of the channel 2 18 1 OSSL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_PWM_OSSUPD PWM Output Selection Set Update Register 0x54 32 write-only n 0x0 0x0 OSSUPH0 Output Selection Set for PWMH output of the channel 0 0 1 OSSUPH1 Output Selection Set for PWMH output of the channel 1 1 1 OSSUPH2 Output Selection Set for PWMH output of the channel 2 2 1 OSSUPH3 Output Selection Set for PWMH output of the channel 3 3 1 OSSUPL0 Output Selection Set for PWML output of the channel 0 16 1 OSSUPL1 Output Selection Set for PWML output of the channel 1 17 1 OSSUPL2 Output Selection Set for PWML output of the channel 2 18 1 OSSUPL3 Output Selection Set for PWML output of the channel 3 19 1 PWM_PWM_SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 0x0 PTRCS DMA Controller Transfer Request Comparison Selection 21 3 PTRM DMA Controller Transfer Request Mode 20 1 SYNC0 Synchronous Channel 0 0 1 SYNC1 Synchronous Channel 1 1 1 SYNC2 Synchronous Channel 2 2 1 SYNC3 Synchronous Channel 3 3 1 UPDM Synchronous Channels Update Mode 16 2 UPDMSelect MODE0 Manual write of double buffer registers and manual update of synchronous channels 0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 2 PWM_PWM_SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 PWM_PWM_SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 0x0 UPR Update Period 0 4 UPRCNT Update Period Counter 4 4 PWM_PWM_SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n 0x0 0x0 UPRUPD Update Period Update 0 4 PWM_PWM_SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 0x0 DOWN0 DOWN Count 16 1 DOWN1 DOWN Count 17 1 GCEN0 Gray Count ENable 0 1 GCEN1 Gray Count ENable 1 1 PWM_PWM_SR PWM Status Register 0xC 32 read-only n 0x0 0x0 CHID0 Channel ID 0 1 CHID1 Channel ID 1 1 CHID2 Channel ID 2 1 CHID3 Channel ID 3 1 PWM_PWM_SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 0x0 SPRD Spread Spectrum Limit Value 0 24 SPRDM Spread Spectrum Counter Mode 24 1 PWM_PWM_SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n 0x0 0x0 SPRDUP Spread Spectrum Limit Value Update 0 24 PWM_PWM_WPCR PWM Write Protection Control Register 0xE4 32 write-only n 0x0 0x0 WPCMD Write Protection Command 0 2 WPCMDSelect DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 2 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 5265229 WPRG0 Write Protection Register Group 0 2 1 WPRG1 Write Protection Register Group 1 3 1 WPRG2 Write Protection Register Group 2 4 1 WPRG3 Write Protection Register Group 3 5 1 WPRG4 Write Protection Register Group 4 6 1 WPRG5 Write Protection Register Group 5 7 1 PWM_PWM_WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPHWS0 Write Protect HW Status 8 1 WPHWS1 Write Protect HW Status 9 1 WPHWS2 Write Protect HW Status 10 1 WPHWS3 Write Protect HW Status 11 1 WPHWS4 Write Protect HW Status 12 1 WPHWS5 Write Protect HW Status 13 1 WPSWS0 Write Protect SW Status 0 1 WPSWS1 Write Protect SW Status 1 1 WPSWS2 Write Protect SW Status 2 1 WPSWS3 Write Protect SW Status 3 1 WPSWS4 Write Protect SW Status 4 1 WPSWS5 Write Protect SW Status 5 1 WPVS Write Protect Violation Status 7 1 WPVSRC Write Protect Violation Source 16 16 SCM PWM Sync Channels Mode Register 0x20 32 read-write n 0x0 PTRCS DMA Controller Transfer Request Comparison Selection 21 3 read-write PTRM DMA Controller Transfer Request Mode 20 1 read-write SYNC0 Synchronous Channel 0 0 1 read-write SYNC1 Synchronous Channel 1 1 1 read-write SYNC2 Synchronous Channel 2 2 1 read-write SYNC3 Synchronous Channel 3 3 1 read-write UPDM Synchronous Channels Update Mode 16 2 read-write MODE0 Manual write of double buffer registers and manual update of synchronous channels 0x0 MODE1 Manual write of double buffer registers and automatic update of synchronous channels 0x1 MODE2 Automatic write of duty-cycle update registers by the DMA Controller and automatic update of synchronous channels 0x2 SCUC PWM Sync Channels Update Control Register 0x28 32 read-write n 0x0 UPDULOCK Synchronous Channels Update Unlock 0 1 read-write SCUP PWM Sync Channels Update Period Register 0x2C 32 read-write n 0x0 UPR Update Period 0 4 read-write UPRCNT Update Period Counter 4 4 read-write SCUPUPD PWM Sync Channels Update Period Update Register 0x30 32 write-only n UPRUPD Update Period Update 0 4 write-only SMMR PWM Stepper Motor Mode Register 0xB0 32 read-write n 0x0 DOWN0 DOWN Count 16 1 read-write DOWN1 DOWN Count 17 1 read-write GCEN0 Gray Count ENable 0 1 read-write GCEN1 Gray Count ENable 1 1 read-write SR PWM Status Register 0xC 32 read-only n 0x0 CHID0 Channel ID 0 1 read-only CHID1 Channel ID 1 1 read-only CHID2 Channel ID 2 1 read-only CHID3 Channel ID 3 1 read-only SSPR PWM Spread Spectrum Register 0xA0 32 read-write n 0x0 SPRD Spread Spectrum Limit Value 0 24 read-write SPRDM Spread Spectrum Counter Mode 24 1 read-write SSPUP PWM Spread Spectrum Update Register 0xA4 32 write-only n SPRDUP Spread Spectrum Limit Value Update 0 24 write-only WPCR PWM Write Protection Control Register 0xE4 32 write-only n WPCMD Write Protection Command 0 2 write-only DISABLE_SW_PROT Disables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x0 ENABLE_SW_PROT Enables the software write protection of the register groups of which the bit WPRGx is at '1'. 0x1 ENABLE_HW_PROT Enables the hardware write protection of the register groups of which the bit WPRGx is at '1'. Only a hardware reset of the PWM controller can disable the hardware write protection. Moreover, to meet security requirements, the PIO lines associated with the PWM can not be configured through the PIO interface. 0x2 WPKEY Write Protection Key 8 24 write-only PASSWD Writing any other value in this field aborts the write operation of the WPCMD field.Always reads as 0 0x50574D WPRG0 Write Protection Register Group 0 2 1 write-only WPRG1 Write Protection Register Group 1 3 1 write-only WPRG2 Write Protection Register Group 2 4 1 write-only WPRG3 Write Protection Register Group 3 5 1 write-only WPRG4 Write Protection Register Group 4 6 1 write-only WPRG5 Write Protection Register Group 5 7 1 write-only WPSR PWM Write Protection Status Register 0xE8 32 read-only n 0x0 WPHWS0 Write Protect HW Status 8 1 read-only WPHWS1 Write Protect HW Status 9 1 read-only WPHWS2 Write Protect HW Status 10 1 read-only WPHWS3 Write Protect HW Status 11 1 read-only WPHWS4 Write Protect HW Status 12 1 read-only WPHWS5 Write Protect HW Status 13 1 read-only WPSWS0 Write Protect SW Status 0 1 read-only WPSWS1 Write Protect SW Status 1 1 read-only WPSWS2 Write Protect SW Status 2 1 read-only WPSWS3 Write Protect SW Status 3 1 read-only WPSWS4 Write Protect SW Status 4 1 read-only WPSWS5 Write Protect SW Status 5 1 read-only WPVS Write Protect Violation Status 7 1 read-only WPVSRC Write Protect Violation Source 16 16 read-only QSPI Quad Serial Peripheral Interface QSPI 0x0 0x0 0x4000 registers n QSPI 43 CR Control Register 0x0 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 QSPIDIS QSPI Disable 1 1 QSPIEN QSPI Enable 0 1 SWRST QSPI Software Reset 7 1 IAR Instruction Address Register 0x30 32 read-write n 0x0 0x0 ADDR Address 0 32 ICR Instruction Code Register 0x34 32 read-write n 0x0 0x0 INST Instruction Code 0 8 OPT Option Code 16 8 IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 CSR Chip Select Rise Interrupt Disable 8 1 CSS Chip Select Status Interrupt Disable 9 1 INSTRE Instruction End Interrupt Disable 10 1 OVRES Overrun Error Interrupt Disable 3 1 RDRF Receive Data Register Full Interrupt Disable 0 1 TDRE Transmit Data Register Empty Interrupt Disable 1 1 TXEMPTY Transmission Registers Empty Disable 2 1 IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 CSR Chip Select Rise Interrupt Enable 8 1 CSS Chip Select Status Interrupt Enable 9 1 INSTRE Instruction End Interrupt Enable 10 1 OVRES Overrun Error Interrupt Enable 3 1 RDRF Receive Data Register Full Interrupt Enable 0 1 TDRE Transmit Data Register Empty Interrupt Enable 1 1 TXEMPTY Transmission Registers Empty Enable 2 1 IFR Instruction Frame Register 0x38 32 read-write n 0x0 0x0 ADDREN Address Enable 5 1 ADDRL Address Length 10 1 ADDRLSelect _24_BIT The address is 24 bits long. 0 _32_BIT The address is 32 bits long. 1 CRM Continuous Read Mode 14 1 CRMSelect DISABLED The Continuous Read mode is disabled. 0 ENABLED The Continuous Read mode is enabled. 1 DATAEN Data Enable 7 1 INSTEN Instruction Enable 4 1 NBDUM Number Of Dummy Cycles 16 5 OPTEN Option Enable 6 1 OPTL Option Code Length 8 2 OPTLSelect OPTION_1BIT The option code is 1 bit long. 0 OPTION_2BIT The option code is 2 bits long. 1 OPTION_4BIT The option code is 4 bits long. 2 OPTION_8BIT The option code is 8 bits long. 3 TFRTYP Data Transfer Type 12 2 TFRTYPSelect TRSFR_READ Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial Flash memory is not possible. 0 TRSFR_READ_MEMORY Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial Flash memory is possible. 1 TRSFR_WRITE Write transfer into the serial memory.Scrambling is not performed. 2 TRSFR_WRITE_MEMORY Write data transfer into the serial memory.If enabled, scrambling is performed. 3 WIDTH Width of Instruction Code, Address, Option Code and Data 0 3 WIDTHSelect SINGLE_BIT_SPI Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI 0 DUAL_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI 1 QUAD_OUTPUT Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI 2 DUAL_IO Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI 3 QUAD_IO Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI 4 DUAL_CMD Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI 5 QUAD_CMD Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI 6 IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 CSR Chip Select Rise Interrupt Mask 8 1 CSS Chip Select Status Interrupt Mask 9 1 INSTRE Instruction End Interrupt Mask 10 1 OVRES Overrun Error Interrupt Mask 3 1 RDRF Receive Data Register Full Interrupt Mask 0 1 TDRE Transmit Data Register Empty Interrupt Mask 1 1 TXEMPTY Transmission Registers Empty Mask 2 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 CSMODE Chip Select Mode 4 2 CSMODESelect NOT_RELOADED The chip select is deasserted if QSPI_TDR.TD has not been reloaded before the end of the current transfer. 0 LASTXFER The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in QSPI_TDR.TD has been transferred. 1 SYSTEMATICALLY The chip select is deasserted systematically after each transfer. 2 DLYBCT Delay Between Consecutive Transfers 16 8 DLYCS Minimum Inactive QCS Delay 24 8 LLB Local Loopback Enable 1 1 LLBSelect DISABLED Local loopback path disabled. 0 ENABLED Local loopback path enabled. 1 NBBITS Number Of Bits Per Transfer 8 4 NBBITSSelect _8_BIT 8 bits for transfer 0 _16_BIT 16 bits for transfer 8 SMM Serial Memory Mode 0 1 SMMSelect SPI The QSPI is in SPI mode. 0 MEMORY The QSPI is in Serial Memory mode. 1 WDRBT Wait Data Read Before Transfer 2 1 WDRBTSelect DISABLED No effect. In SPI mode, a transfer can be initiated whatever the state of the QSPI_RDR is. 0 ENABLED In SPI mode, a transfer can start only if the QSPI_RDR is empty, i.e., does not contain any unread data. This mode prevents overrun error in reception. 1 RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 RD Receive Data 0 16 SCR Serial Clock Register 0x20 32 read-write n 0x0 0x0 CPHA Clock Phase 1 1 CPOL Clock Polarity 0 1 DLYBS Delay Before QSCK 16 8 SCBR Serial Clock Baud Rate 8 8 SKR Scrambling Key Register 0x44 32 write-only n 0x0 0x0 USRK Scrambling User Key 0 32 SMR Scrambling Mode Register 0x40 32 read-write n 0x0 0x0 RVDIS Scrambling/Unscrambling Random Value Disable 1 1 SCREN Scrambling/Unscrambling Enable 0 1 SCRENSelect DISABLED The scrambling/unscrambling is disabled. 0 ENABLED The scrambling/unscrambling is enabled. 1 SR Status Register 0x10 32 read-only n 0x0 0x0 CSR Chip Select Rise (cleared on read) 8 1 CSS Chip Select Status 9 1 INSTRE Instruction End Status (cleared on read) 10 1 OVRES Overrun Error Status (cleared on read) 3 1 QSPIENS QSPI Enable Status 24 1 RDRF Receive Data Register Full (cleared by reading SPI_RDR) 0 1 TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) 1 1 TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) 2 1 TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 TD Transmit Data 0 16 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5329744 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 8 RSTC Reset Controller RSTC 0x0 0x0 0xC registers n RSTC 1 CR Control Register 0x0 32 write-only n 0x0 0x0 EXTRST External Reset 3 1 KEY System Reset Key 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 165 PROCRST Processor Reset 0 1 MR Mode Register 0x8 32 read-write n 0x0 0x0 ERSTL External Reset Length 8 4 KEY Write Access Password 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 165 URSTEN User Reset Enable 0 1 URSTIEN User Reset Interrupt Enable 4 1 SR Status Register 0x4 32 read-only n 0x0 0x0 NRSTL NRST Pin Level 16 1 RSTTYP Reset Type 8 3 RSTTYPSelect GENERAL_RST First power-up reset 0 BACKUP_RST Return from Backup Mode 1 WDT_RST Watchdog fault occurred 2 SOFT_RST Processor reset required by the software 3 USER_RST NRST pin detected low 4 SRCMP Software Reset Command in Progress 17 1 URSTS User Reset Status 0 1 RSWDT Reinforced Safety Watchdog Timer RSWDT 0x0 0x0 0xC registers n RSWDT 63 CR Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 196 WDRSTT Watchdog Restart 0 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 ALLONES Must Always Be Written with 0xFFF 16 12 WDDBGHLT Watchdog Debug Halt 28 1 WDDIS Watchdog Disable 15 1 WDFIEN Watchdog Fault Interrupt Enable 12 1 WDIDLEHLT Watchdog Idle Halt 29 1 WDRSTEN Watchdog Reset Enable 13 1 WDV Watchdog Counter Value 0 12 SR Status Register 0x8 32 read-only n 0x0 0x0 WDUNF Watchdog Underflow 0 1 RTC Real-time Clock RTC 0x0 0x0 0x30 registers n RTC 2 CALALR Calendar Alarm Register 0x14 32 read-write n 0x0 0x0 DATE Date Alarm 24 6 DATEEN Date Alarm Enable 31 1 MONTH Month Alarm 16 5 MTHEN Month Alarm Enable 23 1 CALR Calendar Register 0xC 32 read-write n 0x0 0x0 CENT Current Century 0 7 DATE Current Day in Current Month 24 6 DAY Current Day in Current Week 21 3 MONTH Current Month 16 5 YEAR Current Year 8 8 CR Control Register 0x0 32 read-write n 0x0 0x0 CALEVSEL Calendar Event Selection 16 2 CALEVSELSelect WEEK Week change (every Monday at time 00:00:00) 0 MONTH Month change (every 01 of each month at time 00:00:00) 1 YEAR Year change (every January 1 at time 00:00:00) 2 TIMEVSEL Time Event Selection 8 2 TIMEVSELSelect MINUTE Minute change 0 HOUR Hour change 1 MIDNIGHT Every day at midnight 2 NOON Every day at noon 3 UPDCAL Update Request Calendar Register 1 1 UPDTIM Update Request Time Register 0 1 IDR Interrupt Disable Register 0x24 32 write-only n 0x0 0x0 ACKDIS Acknowledge Update Interrupt Disable 0 1 ALRDIS Alarm Interrupt Disable 1 1 CALDIS Calendar Event Interrupt Disable 4 1 SECDIS Second Event Interrupt Disable 2 1 TDERRDIS Time and/or Date Error Interrupt Disable 5 1 TIMDIS Time Event Interrupt Disable 3 1 IER Interrupt Enable Register 0x20 32 write-only n 0x0 0x0 ACKEN Acknowledge Update Interrupt Enable 0 1 ALREN Alarm Interrupt Enable 1 1 CALEN Calendar Event Interrupt Enable 4 1 SECEN Second Event Interrupt Enable 2 1 TDERREN Time and/or Date Error Interrupt Enable 5 1 TIMEN Time Event Interrupt Enable 3 1 IMR Interrupt Mask Register 0x28 32 read-only n 0x0 0x0 ACK Acknowledge Update Interrupt Mask 0 1 ALR Alarm Interrupt Mask 1 1 CAL Calendar Event Interrupt Mask 4 1 SEC Second Event Interrupt Mask 2 1 TDERR Time and/or Date Error Mask 5 1 TIM Time Event Interrupt Mask 3 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 CORRECTION Slow Clock Correction 8 7 HIGHPPM HIGH PPM Correction 15 1 HRMOD 12-/24-hour Mode 0 1 NEGPPM NEGative PPM Correction 4 1 OUT0 RTCOUT0 OutputSource Selection 16 3 OUT0Select NO_WAVE No waveform, stuck at '0' 0 FREQ1HZ 1 Hz square wave 1 FREQ32HZ 32 Hz square wave 2 FREQ64HZ 64 Hz square wave 3 FREQ512HZ 512 Hz square wave 4 ALARM_TOGGLE Output toggles when alarm flag rises 5 ALARM_FLAG Output is a copy of the alarm flag 6 PROG_PULSE Duty cycle programmable pulse 7 OUT1 RTCOUT1 Output Source Selection 20 3 OUT1Select NO_WAVE No waveform, stuck at '0' 0 FREQ1HZ 1 Hz square wave 1 FREQ32HZ 32 Hz square wave 2 FREQ64HZ 64 Hz square wave 3 FREQ512HZ 512 Hz square wave 4 ALARM_TOGGLE Output toggles when alarm flag rises 5 ALARM_FLAG Output is a copy of the alarm flag 6 PROG_PULSE Duty cycle programmable pulse 7 PERSIAN PERSIAN Calendar 1 1 THIGH High Duration of the Output Pulse 24 3 THIGHSelect H_31MS 31.2 ms 0 H_16MS 15.6 ms 1 H_4MS 3.91 ms 2 H_976US 976 us 3 H_488US 488 us 4 H_122US 122 us 5 H_30US 30.5 us 6 H_15US 15.2 us 7 TPERIOD Period of the Output Pulse 28 2 TPERIODSelect P_1S 1 second 0 P_500MS 500 ms 1 P_250MS 250 ms 2 P_125MS 125 ms 3 SCCR Status Clear Command Register 0x1C 32 write-only n 0x0 0x0 ACKCLR Acknowledge Clear 0 1 ALRCLR Alarm Clear 1 1 CALCLR Calendar Clear 4 1 SECCLR Second Clear 2 1 TDERRCLR Time and/or Date Free Running Error Clear 5 1 TIMCLR Time Clear 3 1 SR Status Register 0x18 32 read-only n 0x0 0x0 ACKUPD Acknowledge for Update 0 1 ACKUPDSelect FREERUN Time and calendar registers cannot be updated. 0 UPDATE Time and calendar registers can be updated. 1 ALARM Alarm Flag 1 1 ALARMSelect NO_ALARMEVENT No alarm matching condition occurred. 0 ALARMEVENT An alarm matching condition has occurred. 1 CALEV Calendar Event 4 1 CALEVSelect NO_CALEVENT No calendar event has occurred since the last clear. 0 CALEVENT At least one calendar event has occurred since the last clear. 1 SEC Second Event 2 1 SECSelect NO_SECEVENT No second event has occurred since the last clear. 0 SECEVENT At least one second event has occurred since the last clear. 1 TDERR Time and/or Date Free Running Error 5 1 TDERRSelect CORRECT The internal free running counters are carrying valid values since the last read of the Status Register (RTC_SR). 0 ERR_TIMEDATE The internal free running counters have been corrupted (invalid date or time, non-BCD values) since the last read and/or they are still invalid. 1 TIMEV Time Event 3 1 TIMEVSelect NO_TIMEVENT No time event has occurred since the last clear. 0 TIMEVENT At least one time event has occurred since the last clear. 1 TIMALR Time Alarm Register 0x10 32 read-write n 0x0 0x0 AMPM AM/PM Indicator 22 1 HOUR Hour Alarm 16 6 HOUREN Hour Alarm Enable 23 1 MIN Minute Alarm 8 7 MINEN Minute Alarm Enable 15 1 SEC Second Alarm 0 7 SECEN Second Alarm Enable 7 1 TIMR Time Register 0x8 32 read-write n 0x0 0x0 AMPM Ante Meridiem Post Meridiem Indicator 22 1 HOUR Current Hour 16 6 MIN Current Minute 8 7 SEC Current Second 0 7 VER Valid Entry Register 0x2C 32 read-only n 0x0 0x0 NVCAL Non-valid Calendar 1 1 NVCALALR Non-valid Calendar Alarm 3 1 NVTIM Non-valid Time 0 1 NVTIMALR Non-valid Time Alarm 2 1 RTT Real-time Timer RTT 0x0 0x0 0x10 registers n RTT 3 AR Alarm Register 0x4 32 read-write n 0x0 0x0 ALMV Alarm Value 0 32 MR Mode Register 0x0 32 read-write n 0x0 0x0 ALMIEN Alarm Interrupt Enable 16 1 RTC1HZ Real-Time Clock 1Hz Clock Selection 24 1 RTPRES Real-time Timer Prescaler Value 0 16 RTTDIS Real-time Timer Disable 20 1 RTTINCIEN Real-time Timer Increment Interrupt Enable 17 1 RTTRST Real-time Timer Restart 18 1 SR Status Register 0xC 32 read-only n 0x0 0x0 ALMS Real-time Alarm Status (cleared on read) 0 1 RTTINC Prescaler Roll-over Status (cleared on read) 1 1 VR Value Register 0x8 32 read-only n 0x0 0x0 CRTV Current Real-time Value 0 32 SCB System Control Block SCB 0x0 0x0 0x24C registers n AFSR Auxiliary Fault Status Register 0x3C 32 read-write n 0x0 0x0 AIRCR Application Interrupt and Reset Control Register 0xC 32 read-write n 0x0 0x0 ENDIANNESS Memory system endianness 15 1 ENDIANNESSSelect VALUE_0 Little-endian 0 VALUE_1 Big-endian 1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 SYSRESETREQ System Reset Request 2 1 SYSRESETREQSelect VALUE_0 no system reset request 0 VALUE_1 asserts a signal to the outer system that requests a reset 1 VECTCLRACTIVE Clears all active state information for fixed and configurable exceptions 1 1 VECTKEY Vector key 16 16 VECTRESET Writing 1 to this bit causes a local system reset 0 1 BFAR BusFault Address Register 0x38 32 read-write n 0x0 0x0 ADDRESS Data address for a precise bus fault 0 32 CCR Configuration and Control Register 0x14 32 read-write n 0x0 0x0 BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 BFHFNMIGNSelect VALUE_0 data bus faults caused by load and store instructions cause a lock-up 0 VALUE_1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions 1 BP Branch prediction enable bi 18 1 DC Cache enable bit 16 1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 DIV_0_TRPSelect VALUE_0 do not trap divide by 0 0 VALUE_1 trap divide by 0 1 IC Instruction cache enable bi 17 1 NONBASETHRDENA Controls whether the processor can enter Thread mode with exceptions active 0 1 NONBASETHRDENASelect VALUE_0 processor can enter Thread mode only when no exception is active 0 VALUE_1 processor can enter Thread mode from any level under the control of an EXC_RETURN value 1 STKALIGN Indicates stack alignment on exception entry 9 1 STKALIGNSelect VALUE_0 4-byte aligned 0 VALUE_1 8-byte aligned 1 UNALIGN_TRP Enables unaligned access traps 3 1 UNALIGN_TRPSelect VALUE_0 do not trap unaligned halfword and word accesses 0 VALUE_1 trap unaligned halfword and word accesses 1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 USERSETMPENDSelect VALUE_0 disable 0 VALUE_1 enable 1 CCSIDR Cache Size ID Register 0x80 32 read-only n 0x0 0x0 Associativity number of ways 3 9 LineSize number of words in each cache line 0 3 NumSets number of sets 12 16 RA Read allocation support 29 1 WA Write allocation support 28 1 WB Write-Back support 30 1 WT Write-Through support 31 1 CFSR Configurable Fault Status Registers 0x28 32 read-write n 0x0 0x0 BFARVALID 15 1 BFARVALIDSelect VALUE_0 value in BFAR is not a valid fault address 0 VALUE_1 BFAR holds a valid fault address 1 DACCVIOL 1 1 DACCVIOLSelect VALUE_0 no data access violation fault 0 VALUE_1 the processor attempted a load or store at a location that does not permit the operation 1 DIVBYZERO 25 1 DIVBYZEROSelect VALUE_0 no divide by zero fault, or divide by zero trapping not enabled 0 VALUE_1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 1 IACCVIOL 0 1 IACCVIOLSelect VALUE_0 no instruction access violation fault 0 VALUE_1 the processor attempted an instruction fetch from a location that does not permit execution 1 IBUSERR 8 1 IBUSERRSelect VALUE_0 no instruction bus error 0 VALUE_1 instruction bus error 1 IMPRECISERR 10 1 IMPRECISERRSelect VALUE_0 no imprecise data bus error 0 VALUE_1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error 1 INVPC 18 1 INVPCSelect VALUE_0 no invalid PC load UsageFault 0 VALUE_1 the processor has attempted an illegal load of EXC_RETURN to the PC 1 INVSTATE 17 1 INVSTATESelect VALUE_0 no invalid state UsageFault 0 VALUE_1 the processor has attempted to execute an instruction that makes illegal use of the EPSR 1 LSPERR 13 1 LSPERRSelect VALUE_0 No bus fault occurred during floating-point lazy state preservation 0 VALUE_1 A bus fault occurred during floating-point lazy state preservation 1 MLSPERR 5 1 MLSPERRSelect VALUE_0 No MemManage fault occurred during floating-point lazy state preservation 0 VALUE_1 A MemManage fault occurred during floating-point lazy state preservation 1 MMARVALID 7 1 MMARVALIDSelect VALUE_0 value in MMAR is not a valid fault address 0 VALUE_1 MMAR holds a valid fault address 1 MSTKERR 4 1 MSTKERRSelect VALUE_0 no stacking fault 0 VALUE_1 stacking for an exception entry has caused one or more access violations 1 MUNSTKERR 3 1 MUNSTKERRSelect VALUE_0 no unstacking fault 0 VALUE_1 unstack for an exception return has caused one or more access violations 1 NOCP 19 1 NOCPSelect VALUE_0 no UsageFault caused by attempting to access a coprocessor 0 VALUE_1 the processor has attempted to access a coprocessor 1 PRECISERR 9 1 PRECISERRSelect VALUE_0 no precise data bus error 0 VALUE_1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault 1 STKERR 12 1 STKERRSelect VALUE_0 no stacking fault 0 VALUE_1 stacking for an exception entry has caused one or more BusFaults 1 UNALIGNED 24 1 UNALIGNEDSelect VALUE_0 no unaligned access fault, or unaligned access trapping not enabled 0 VALUE_1 the processor has made an unaligned memory access 1 UNDEFINSTR 16 1 UNDEFINSTRSelect VALUE_0 no undefined instruction UsageFault 0 VALUE_1 the processor has attempted to execute an undefined instruction 1 UNSTKERR 11 1 UNSTKERRSelect VALUE_0 no unstacking fault 0 VALUE_1 unstack for an exception return has caused one or more BusFaults 1 CLIDR Cache Level ID Register 0x78 32 read-only n 0x0 0x0 LoC Level of Coherency 24 3 LoCSelect LEVEL_1 if neither instruction nor data cache is implemented 0 LEVEL_2 if either cache is implemented 1 LoU Level of Unification 27 3 LoUSelect LEVEL_1 if neither instruction nor data cache is implemented 0 LEVEL_2 if either cache is implemented 1 CPACR Coprocessor Access Control Register 0x88 32 read-write n 0x0 0x0 CP10 Access privileges for coprocessor 10. 20 2 CP11 Access privileges for coprocessor 11. 22 2 CPUID CPUID Base Register 0x0 32 read-only n 0x0 0x0 ARCHITECTURE Indicates architecture. Reads as 0xF 16 4 IMPLEMENTER Implementer code 24 8 PARTNO Indicates part number 4 12 REVISION Indicates patch release: 0x0 = Patch 0 0 4 VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 CSSELR Cache Size Selection Register 0x84 32 read-write n 0x0 0x0 IND selection of instruction or data cache 0 1 INDSelect DATA Data cache 0 INSTRUCTION Instruction cache 1 LEVEL cache level selected 1 3 CTR Cache Type Register 0x7C 32 read-only n 0x0 0x0 CWG Cache Writeback Granule 24 4 DMINLINE Smallest cache line of all the data and unified caches under the core control 16 4 ERG Exclusives Reservation Granule 20 4 FORMAT Register format 29 3 IMINLINE Smallest cache line of all the instruction caches under the control of the processor 0 4 DFSR Debug Fault Status Register 0x30 32 read-write n 0x0 0x0 BKPT debug event generated by BKPT instruction execution or a breakpoint match in FPB 1 1 BKPTSelect VALUE_0 No current breakpoint debug event 0 VALUE_1 At least one current breakpoint debug event 1 DWTTRAP debug event generated by the DWT 2 1 DWTTRAPSelect VALUE_0 No current debug events generated by the DWT 0 VALUE_1 At least one current debug event generated by the DWT 1 EXTERNAL debug event generated because of the assertion of an external debug request 4 1 EXTERNALSelect VALUE_0 No EDBGRQ debug event 0 VALUE_1 EDBGRQ debug event 1 HALTED debug event generated by 0 1 HALTEDSelect VALUE_0 No active halt request debug event 0 VALUE_1 Halt request debug event active 1 VCATCH triggering of a Vector catch 3 1 VCATCHSelect VALUE_0 No Vector catch triggered 0 VALUE_1 Vector catch triggered 1 HFSR HardFault Status register 0x2C 32 read-write n 0x0 0x0 DEBUGEVT Indicates when a Debug event has occurred 31 1 FORCED Indicates that a fault with configurable priority has been escalated to a HardFault exception 30 1 FORCEDSelect VALUE_0 no forced HardFault 0 VALUE_1 forced HardFault 1 VECTTBL Indicates when a fault has occurred because of a vector table read error on exception processing 1 1 VECTTBLSelect VALUE_0 no BusFault on vector table read 0 VALUE_1 BusFault on vector table read 1 ICSR Interrupt Control and State Register 0x4 32 read-write n 0x0 0x0 ISRPENDING Is external interrupt, generated by the NVIC, pending 22 1 ISRPREEMPT Indicates whether a pending exception will be serviced on exit from debug halt state 23 1 ISRPREEMPTSelect VALUE_0 Will not service 0 VALUE_1 Will service a pending exception 1 NMIPENDSET Makes the NMI exception active, or reads the state of the exception 31 1 NMIPENDSETSelect VALUE_0 write: no effect; read: NMI exception is not pending 0 VALUE_1 write: changes NMI exception state to pending; read: NMI exception is pending 1 PENDSTCLR Removes the pending status of the SysTick exception 25 1 PENDSTCLRSelect VALUE_0 no effect 0 VALUE_1 removes the pending state from the SysTick exception 1 PENDSTSET Sets the SysTick exception as pending, or reads the current state of the exception 26 1 PENDSTSETSelect VALUE_0 write: no effect; read: SysTick exception is not pending 0 VALUE_1 write: changes SysTick exception state to pending; read: SysTick exception is pending 1 PENDSVCLR Removes the pending status of the PendSV exception 27 1 PENDSVCLRSelect VALUE_0 no effect 0 VALUE_1 removes the pending state from the PendSV exception 1 PENDSVSET Sets the PendSV exception as pending, or reads the current state of the exception 28 1 PENDSVSETSelect VALUE_0 write: no effect; read: PendSV exception is not pending 0 VALUE_1 write: changes PendSV exception state to pending; read: PendSV exception is pending 1 RETTOBASE Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR 11 1 RETTOBASESelect VALUE_0 there are preempted active exceptions to execute 0 VALUE_1 there are no active exceptions, or the currently-executing exception is the only active exception 1 VECTACTIVE Active exception number 0 9 VECTPENDING Exception number of the highest priority pending enabled exception 12 6 MMFAR MemManage Fault Address Register 0x34 32 read-write n 0x0 0x0 ADDRESS Data address for an MPU fault 0 32 MVFR0 Media and VFP Feature Register 0 0x240 32 read-only n 0x0 0x0 MVFR1 Media and VFP Feature Register 1 0x244 32 read-only n 0x0 0x0 MVFR2 Media and VFP Feature Register 2 0x248 32 read-only n 0x0 0x0 SCR System Control Register 0x10 32 read-write n 0x0 0x0 SEVONPEND Determines whether an interrupt transition from inactive state to pending state is a wakeup event 4 1 SEVONPENDSelect VALUE_0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded 0 VALUE_1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor 1 SLEEPDEEP Provides a qualifying hint indicating that waking from sleep might take longer 2 1 SLEEPDEEPSelect VALUE_0 sleep 0 VALUE_1 deep sleep 1 SLEEPONEXIT Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state 1 1 SLEEPONEXITSelect VALUE_0 o not sleep when returning to Thread mode 0 VALUE_1 enter sleep, or deep sleep, on return from an ISR 1 SHCSR System Handler Control and State Register 0x24 32 read-write n 0x0 0x0 BUSFAULTACT 1 1 BUSFAULTACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 BUSFAULTENA 17 1 BUSFAULTENASelect VALUE_0 disable the exception 0 VALUE_1 enable the exception 1 BUSFAULTPENDED 14 1 BUSFAULTPENDEDSelect VALUE_0 exception is not pending 0 VALUE_1 exception is pending 1 MEMFAULTACT 0 1 MEMFAULTACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 MEMFAULTENA 16 1 MEMFAULTENASelect VALUE_0 disable the exception 0 VALUE_1 enable the exception 1 MEMFAULTPENDED 13 1 MEMFAULTPENDEDSelect VALUE_0 exception is not pending 0 VALUE_1 exception is pending 1 MONITORACT 8 1 MONITORACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 PENDSVACT 10 1 PENDSVACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 SVCALLACT 7 1 SVCALLACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 SVCALLPENDED 15 1 SVCALLPENDEDSelect VALUE_0 exception is not pending 0 VALUE_1 exception is pending 1 SYSTICKACT 11 1 SYSTICKACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 USGFAULTACT 3 1 USGFAULTACTSelect VALUE_0 exception is not active 0 VALUE_1 exception is active 1 USGFAULTENA 18 1 USGFAULTENASelect VALUE_0 disable the exception 0 VALUE_1 enable the exception 1 USGFAULTPENDED 12 1 USGFAULTPENDEDSelect VALUE_0 exception is not pending 0 VALUE_1 exception is pending 1 SHPR1 System Handler Priority Register 1 0x18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 0 8 PRI_5 Priority of system handler 5, BusFault 8 8 PRI_6 Priority of system handler 6, UsageFault 16 8 SHPR2 System Handler Priority Register 2 0x1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11, SVCall 24 8 SHPR3 System Handler Priority Register 3 0x20 32 read-write n 0x0 0x0 PRI_12 Priority of system handler 12, SysTick 0 8 PRI_14 Priority of system handler 14, PendSV 16 8 PRI_15 Priority of system handler 15, SysTick exception 24 8 STIR Software Trigger Interrupt Register 0x200 32 write-only n 0x0 0x0 INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 VTOR Vector Table Offset Register 0x8 32 read-write n 0x0 0x0 TBLOFF Bits[31:7] of the vector table address 7 25 SCnSCB System control not in SCB SCnSCB 0x0 0x0 0xC registers n ACTLR Auxiliary Control Register 0x8 32 read-write n 0x0 0x0 DISBTACALLOC 14 1 DISBTACREAD 13 1 DISCRITAXIRUR 15 1 DISCRITAXIRUW Disable critical AXI read-under-write 27 1 DISDI 16 5 DISDYNADD Disables dynamic allocation of ADD and SUB instructions 26 1 DISFOLD Disables folding of IT instructions 2 1 DISFPUISSOPT Disables dynamic allocation of ADD and SUB instructions 28 1 DISISSCH1 21 5 DISITMATBFLUSH Disables ITM and DWT ATB flush 12 1 DISRAMODE Disables dynamic read allocate mode for Write-Back Write-Allocate memory regions 11 1 FPEXCODIS Disables FPU exception outputs 10 1 ICTR Interrupt Controller Type Register 0x4 32 read-only n 0x0 0x0 INTLINESNUM Total number of interrupt lines supported by an implementation, defined in groups of 32 0 4 SPI0 Serial Peripheral Interface 0 SPI 0x0 0x0 0x4000 registers n SPI0 21 CR Control Register 0x0 32 write-only n LASTXFER Last Transfer 24 1 write-only SPIDIS SPI Disable 1 1 write-only SPIEN SPI Enable 0 1 write-only SWRST SPI Software Reset 7 1 write-only CSR0 Chip Select Register 0x30 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR1 Chip Select Register 0x34 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR2 Chip Select Register 0x38 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR3 Chip Select Register 0x3C 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write IDR Interrupt Disable Register 0x18 32 write-only n MODF Mode Fault Error Interrupt Disable 2 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only UNDES Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x14 32 write-only n MODF Mode Fault Error Interrupt Enable 2 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only UNDES Underrun Error Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 MODF Mode Fault Error Interrupt Mask 2 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only UNDES Underrun Error Interrupt Mask 10 1 read-only MR Mode Register 0x4 32 read-write n 0x0 DLYBCS Delay Between Chip Selects 24 8 read-write LLB Local Loopback Enable 7 1 read-write MODFDIS Mode Fault Detection 4 1 read-write MSTR Master/Slave Mode 0 1 read-write PCS Peripheral Chip Select 16 4 read-write PCSDEC Chip Select Decode 2 1 read-write PS Peripheral Select 1 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write RDR Receive Data Register 0x8 32 read-only n 0x0 clear PCS Peripheral Chip Select 16 4 read-only RD Receive Data 0 16 read-only SPI_SPI_CR Control Register 0x0 32 write-only n 0x0 0x0 FIFODIS FIFO Disable 31 1 FIFOEN FIFO Enable 30 1 LASTXFER Last Transfer 24 1 REQCLR Request to Clear the Comparison Trigger 12 1 RXFCLR Receive FIFO Clear 17 1 SPIDIS SPI Disable 1 1 SPIEN SPI Enable 0 1 SWRST SPI Software Reset 7 1 TXFCLR Transmit FIFO Clear 16 1 SPI_SPI_CSR[0] Chip Select Register 0 0x60 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 BITSSelect _8_BIT 8 bits for transfer 0 _9_BIT 9 bits for transfer 1 _10_BIT 10 bits for transfer 2 _11_BIT 11 bits for transfer 3 _12_BIT 12 bits for transfer 4 _13_BIT 13 bits for transfer 5 _14_BIT 14 bits for transfer 6 _15_BIT 15 bits for transfer 7 _16_BIT 16 bits for transfer 8 CPOL Clock Polarity 0 1 CSAAT Chip Select Active After Transfer 3 1 CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 DLYBCT Delay Between Consecutive Transfers 24 8 DLYBS Delay Before SPCK 16 8 NCPHA Clock Phase 1 1 SCBR Serial Clock Bit Rate 8 8 SPI_SPI_CSR[1] Chip Select Register 0 0x94 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 BITSSelect _8_BIT 8 bits for transfer 0 _9_BIT 9 bits for transfer 1 _10_BIT 10 bits for transfer 2 _11_BIT 11 bits for transfer 3 _12_BIT 12 bits for transfer 4 _13_BIT 13 bits for transfer 5 _14_BIT 14 bits for transfer 6 _15_BIT 15 bits for transfer 7 _16_BIT 16 bits for transfer 8 CPOL Clock Polarity 0 1 CSAAT Chip Select Active After Transfer 3 1 CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 DLYBCT Delay Between Consecutive Transfers 24 8 DLYBS Delay Before SPCK 16 8 NCPHA Clock Phase 1 1 SCBR Serial Clock Bit Rate 8 8 SPI_SPI_CSR[2] Chip Select Register 0 0xCC 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 BITSSelect _8_BIT 8 bits for transfer 0 _9_BIT 9 bits for transfer 1 _10_BIT 10 bits for transfer 2 _11_BIT 11 bits for transfer 3 _12_BIT 12 bits for transfer 4 _13_BIT 13 bits for transfer 5 _14_BIT 14 bits for transfer 6 _15_BIT 15 bits for transfer 7 _16_BIT 16 bits for transfer 8 CPOL Clock Polarity 0 1 CSAAT Chip Select Active After Transfer 3 1 CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 DLYBCT Delay Between Consecutive Transfers 24 8 DLYBS Delay Before SPCK 16 8 NCPHA Clock Phase 1 1 SCBR Serial Clock Bit Rate 8 8 SPI_SPI_CSR[3] Chip Select Register 0 0x108 32 read-write n 0x0 0x0 BITS Bits Per Transfer 4 4 BITSSelect _8_BIT 8 bits for transfer 0 _9_BIT 9 bits for transfer 1 _10_BIT 10 bits for transfer 2 _11_BIT 11 bits for transfer 3 _12_BIT 12 bits for transfer 4 _13_BIT 13 bits for transfer 5 _14_BIT 14 bits for transfer 6 _15_BIT 15 bits for transfer 7 _16_BIT 16 bits for transfer 8 CPOL Clock Polarity 0 1 CSAAT Chip Select Active After Transfer 3 1 CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 DLYBCT Delay Between Consecutive Transfers 24 8 DLYBS Delay Before SPCK 16 8 NCPHA Clock Phase 1 1 SCBR Serial Clock Bit Rate 8 8 SPI_SPI_IDR Interrupt Disable Register 0x18 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Disable 2 1 NSSR NSS Rising Interrupt Disable 8 1 OVRES Overrun Error Interrupt Disable 3 1 RDRF Receive Data Register Full Interrupt Disable 0 1 TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 TXEMPTY Transmission Registers Empty Disable 9 1 UNDES Underrun Error Interrupt Disable 10 1 SPI_SPI_IER Interrupt Enable Register 0x14 32 write-only n 0x0 0x0 MODF Mode Fault Error Interrupt Enable 2 1 NSSR NSS Rising Interrupt Enable 8 1 OVRES Overrun Error Interrupt Enable 3 1 RDRF Receive Data Register Full Interrupt Enable 0 1 TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 TXEMPTY Transmission Registers Empty Enable 9 1 UNDES Underrun Error Interrupt Enable 10 1 SPI_SPI_IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 0x0 MODF Mode Fault Error Interrupt Mask 2 1 NSSR NSS Rising Interrupt Mask 8 1 OVRES Overrun Error Interrupt Mask 3 1 RDRF Receive Data Register Full Interrupt Mask 0 1 TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 TXEMPTY Transmission Registers Empty Mask 9 1 UNDES Underrun Error Interrupt Mask 10 1 SPI_SPI_MR Mode Register 0x4 32 read-write n 0x0 0x0 DLYBCS Delay Between Chip Selects 24 8 LLB Local Loopback Enable 7 1 MODFDIS Mode Fault Detection 4 1 MSTR Master/Slave Mode 0 1 PCS Peripheral Chip Select 16 4 PCSDEC Chip Select Decode 2 1 PS Peripheral Select 1 1 WDRBT Wait Data Read Before Transfer 5 1 SPI_SPI_RDR Receive Data Register 0x8 32 read-only n 0x0 0x0 PCS Peripheral Chip Select 16 4 RD Receive Data 0 16 SPI_SPI_SR Status Register 0x10 32 read-only n 0x0 0x0 MODF Mode Fault Error (cleared on read) 2 1 NSSR NSS Rising (cleared on read) 8 1 OVRES Overrun Error Status (cleared on read) 3 1 RDRF Receive Data Register Full (cleared by reading SPI_RDR) 0 1 SPIENS SPI Enable Status 16 1 TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) 1 1 TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) 9 1 UNDES Underrun Error Status (Slave mode only) (cleared on read) 10 1 SPI_SPI_TDR Transmit Data Register 0xC 32 write-only n 0x0 0x0 LASTXFER Last Transfer 24 1 PCS Peripheral Chip Select 16 4 TD Transmit Data 0 16 SPI_SPI_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5460041 SPI_SPI_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 8 SR Status Register 0x10 32 read-only n 0x0 MODF Mode Fault Error (cleared on read) 2 1 read-only NSSR NSS Rising (cleared on read) 8 1 read-only OVRES Overrun Error Status (cleared on read) 3 1 read-only RDRF Receive Data Register Full (cleared by reading SPI_RDR) 0 1 read-only SPIENS SPI Enable Status 16 1 read-only TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) 1 1 read-only TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) 9 1 read-only UNDES Underrun Error Status (Slave mode only) (cleared on read) 10 1 read-only TDR Transmit Data Register 0xC 32 write-only n LASTXFER Last Transfer 24 1 write-only PCS Peripheral Chip Select 16 4 write-only TD Transmit Data 0 16 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535049 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only SPI1 Serial Peripheral Interface 1 SPI 0x0 0x0 0x4000 registers n SPI1 42 CR Control Register 0x0 32 write-only n LASTXFER Last Transfer 24 1 write-only SPIDIS SPI Disable 1 1 write-only SPIEN SPI Enable 0 1 write-only SWRST SPI Software Reset 7 1 write-only CSR0 Chip Select Register 0x30 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR1 Chip Select Register 0x34 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR2 Chip Select Register 0x38 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write CSR3 Chip Select Register 0x3C 32 read-write n BITS Bits Per Transfer 4 4 read-write 8_BIT 8 bits for transfer 0x0 9_BIT 9 bits for transfer 0x1 10_BIT 10 bits for transfer 0x2 11_BIT 11 bits for transfer 0x3 12_BIT 12 bits for transfer 0x4 13_BIT 13 bits for transfer 0x5 14_BIT 14 bits for transfer 0x6 15_BIT 15 bits for transfer 0x7 16_BIT 16 bits for transfer 0x8 CPOL Clock Polarity 0 1 read-write CSAAT Chip Select Active After Transfer 3 1 read-write CSNAAT Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 2 1 read-write DLYBCT Delay Between Consecutive Transfers 24 8 read-write DLYBS Delay Before SPCK 16 8 read-write NCPHA Clock Phase 1 1 read-write SCBR Serial Clock Bit Rate 8 8 read-write IDR Interrupt Disable Register 0x18 32 write-only n MODF Mode Fault Error Interrupt Disable 2 1 write-only NSSR NSS Rising Interrupt Disable 8 1 write-only OVRES Overrun Error Interrupt Disable 3 1 write-only RDRF Receive Data Register Full Interrupt Disable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Disable 1 1 write-only TXEMPTY Transmission Registers Empty Disable 9 1 write-only UNDES Underrun Error Interrupt Disable 10 1 write-only IER Interrupt Enable Register 0x14 32 write-only n MODF Mode Fault Error Interrupt Enable 2 1 write-only NSSR NSS Rising Interrupt Enable 8 1 write-only OVRES Overrun Error Interrupt Enable 3 1 write-only RDRF Receive Data Register Full Interrupt Enable 0 1 write-only TDRE SPI Transmit Data Register Empty Interrupt Enable 1 1 write-only TXEMPTY Transmission Registers Empty Enable 9 1 write-only UNDES Underrun Error Interrupt Enable 10 1 write-only IMR Interrupt Mask Register 0x1C 32 read-only n 0x0 MODF Mode Fault Error Interrupt Mask 2 1 read-only NSSR NSS Rising Interrupt Mask 8 1 read-only OVRES Overrun Error Interrupt Mask 3 1 read-only RDRF Receive Data Register Full Interrupt Mask 0 1 read-only TDRE SPI Transmit Data Register Empty Interrupt Mask 1 1 read-only TXEMPTY Transmission Registers Empty Mask 9 1 read-only UNDES Underrun Error Interrupt Mask 10 1 read-only MR Mode Register 0x4 32 read-write n 0x0 DLYBCS Delay Between Chip Selects 24 8 read-write LLB Local Loopback Enable 7 1 read-write MODFDIS Mode Fault Detection 4 1 read-write MSTR Master/Slave Mode 0 1 read-write PCS Peripheral Chip Select 16 4 read-write PCSDEC Chip Select Decode 2 1 read-write PS Peripheral Select 1 1 read-write WDRBT Wait Data Read Before Transfer 5 1 read-write RDR Receive Data Register 0x8 32 read-only n 0x0 clear PCS Peripheral Chip Select 16 4 read-only RD Receive Data 0 16 read-only SR Status Register 0x10 32 read-only n 0x0 MODF Mode Fault Error (cleared on read) 2 1 read-only NSSR NSS Rising (cleared on read) 8 1 read-only OVRES Overrun Error Status (cleared on read) 3 1 read-only RDRF Receive Data Register Full (cleared by reading SPI_RDR) 0 1 read-only SPIENS SPI Enable Status 16 1 read-only TDRE Transmit Data Register Empty (cleared by writing SPI_TDR) 1 1 read-only TXEMPTY Transmission Registers Empty (cleared by writing SPI_TDR) 9 1 read-only UNDES Underrun Error Status (Slave mode only) (cleared on read) 10 1 read-only TDR Transmit Data Register 0xC 32 write-only n LASTXFER Last Transfer 24 1 write-only PCS Peripheral Chip Select 16 4 write-only TD Transmit Data 0 16 write-only WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x535049 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 8 read-only SSC Synchronous Serial Controller SSC 0x0 0x0 0x4000 registers n SSC 22 CMR Clock Mode Register 0x4 32 read-write n 0x0 0x0 DIV Clock Divider 0 12 CR Control Register 0x0 32 write-only n 0x0 0x0 RXDIS Receive Disable 1 1 RXEN Receive Enable 0 1 SWRST Software Reset 15 1 TXDIS Transmit Disable 9 1 TXEN Transmit Enable 8 1 IDR Interrupt Disable Register 0x48 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Disable 8 1 CP1 Compare 1 Interrupt Disable 9 1 OVRUN Receive Overrun Interrupt Disable 5 1 RXRDY Receive Ready Interrupt Disable 4 1 RXSYN Rx Sync Interrupt Enable 11 1 TXEMPTY Transmit Empty Interrupt Disable 1 1 TXRDY Transmit Ready Interrupt Disable 0 1 TXSYN Tx Sync Interrupt Enable 10 1 IER Interrupt Enable Register 0x44 32 write-only n 0x0 0x0 CP0 Compare 0 Interrupt Enable 8 1 CP1 Compare 1 Interrupt Enable 9 1 OVRUN Receive Overrun Interrupt Enable 5 1 RXRDY Receive Ready Interrupt Enable 4 1 RXSYN Rx Sync Interrupt Enable 11 1 TXEMPTY Transmit Empty Interrupt Enable 1 1 TXRDY Transmit Ready Interrupt Enable 0 1 TXSYN Tx Sync Interrupt Enable 10 1 IMR Interrupt Mask Register 0x4C 32 read-only n 0x0 0x0 CP0 Compare 0 Interrupt Mask 8 1 CP1 Compare 1 Interrupt Mask 9 1 OVRUN Receive Overrun Interrupt Mask 5 1 RXRDY Receive Ready Interrupt Mask 4 1 RXSYN Rx Sync Interrupt Mask 11 1 TXEMPTY Transmit Empty Interrupt Mask 1 1 TXRDY Transmit Ready Interrupt Mask 0 1 TXSYN Tx Sync Interrupt Mask 10 1 RC0R Receive Compare 0 Register 0x38 32 read-write n 0x0 0x0 CP0 Receive Compare Data 0 0 16 RC1R Receive Compare 1 Register 0x3C 32 read-write n 0x0 0x0 CP1 Receive Compare Data 1 0 16 RCMR Receive Clock Mode Register 0x10 32 read-write n 0x0 0x0 CKG Receive Clock Gating Selection 6 2 CKGSelect CONTINUOUS None 0 EN_RF_LOW Receive Clock enabled only if RF Low 1 EN_RF_HIGH Receive Clock enabled only if RF High 2 CKI Receive Clock Inversion 5 1 CKO Receive Clock Output Mode Selection 2 3 CKOSelect NONE None, RK pin is an input 0 CONTINUOUS Continuous Receive Clock, RK pin is an output 1 TRANSFER Receive Clock only during data transfers, RK pin is an output 2 CKS Receive Clock Selection 0 2 CKSSelect MCK Divided Clock 0 TK TK Clock signal 1 RK RK pin 2 PERIOD Receive Period Divider Selection 24 8 START Receive Start Selection 8 4 STARTSelect CONTINUOUS Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0 TRANSMIT Transmit start 1 RF_LOW Detection of a low level on RF signal 2 RF_HIGH Detection of a high level on RF signal 3 RF_FALLING Detection of a falling edge on RF signal 4 RF_RISING Detection of a rising edge on RF signal 5 RF_LEVEL Detection of any level change on RF signal 6 RF_EDGE Detection of any edge on RF signal 7 CMP_0 Compare 0 8 STOP Receive Stop Selection 12 1 STTDLY Receive Start Delay 16 8 RFMR Receive Frame Mode Register 0x14 32 read-write n 0x0 0x0 DATLEN Data Length 0 5 DATNB Data Number per Frame 8 4 FSEDGE Frame Sync Edge Detection 24 1 FSEDGESelect POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Receive Frame Sync Length 16 4 FSLEN_EXT FSLEN Field Extension 28 4 FSOS Receive Frame Sync Output Selection 20 3 FSOSSelect NONE None, RF pin is an input 0 NEGATIVE Negative Pulse, RF pin is an output 1 POSITIVE Positive Pulse, RF pin is an output 2 LOW Driven Low during data transfer, RF pin is an output 3 HIGH Driven High during data transfer, RF pin is an output 4 TOGGLING Toggling at each start of data transfer, RF pin is an output 5 LOOP Loop Mode 5 1 MSBF Most Significant Bit First 7 1 RHR Receive Holding Register 0x20 32 read-only n 0x0 0x0 RDAT Receive Data 0 32 RSHR Receive Sync. Holding Register 0x30 32 read-only n 0x0 0x0 RSDAT Receive Synchronization Data 0 16 SR Status Register 0x40 32 read-only n 0x0 0x0 CP0 Compare 0 8 1 CP1 Compare 1 9 1 OVRUN Receive Overrun 5 1 RXEN Receive Enable 17 1 RXRDY Receive Ready 4 1 RXSYN Receive Sync 11 1 TXEMPTY Transmit Empty 1 1 TXEN Transmit Enable 16 1 TXRDY Transmit Ready 0 1 TXSYN Transmit Sync 10 1 TCMR Transmit Clock Mode Register 0x18 32 read-write n 0x0 0x0 CKG Transmit Clock Gating Selection 6 2 CKGSelect CONTINUOUS None 0 EN_TF_LOW Transmit Clock enabled only if TF Low 1 EN_TF_HIGH Transmit Clock enabled only if TF High 2 CKI Transmit Clock Inversion 5 1 CKO Transmit Clock Output Mode Selection 2 3 CKOSelect NONE None, TK pin is an input 0 CONTINUOUS Continuous Transmit Clock, TK pin is an output 1 TRANSFER Transmit Clock only during data transfers, TK pin is an output 2 CKS Transmit Clock Selection 0 2 CKSSelect MCK Divided Clock 0 RK RK Clock signal 1 TK TK pin 2 PERIOD Transmit Period Divider Selection 24 8 START Transmit Start Selection 8 4 STARTSelect CONTINUOUS Continuous, as soon as a word is written in the SSC_THR (if Transmit is enabled), and immediately after the end of transfer of the previous data 0 RECEIVE Receive start 1 TF_LOW Detection of a low level on TF signal 2 TF_HIGH Detection of a high level on TF signal 3 TF_FALLING Detection of a falling edge on TF signal 4 TF_RISING Detection of a rising edge on TF signal 5 TF_LEVEL Detection of any level change on TF signal 6 TF_EDGE Detection of any edge on TF signal 7 STTDLY Transmit Start Delay 16 8 TFMR Transmit Frame Mode Register 0x1C 32 read-write n 0x0 0x0 DATDEF Data Default Value 5 1 DATLEN Data Length 0 5 DATNB Data Number per Frame 8 4 FSDEN Frame Sync Data Enable 23 1 FSEDGE Frame Sync Edge Detection 24 1 FSEDGESelect POSITIVE Positive Edge Detection 0 NEGATIVE Negative Edge Detection 1 FSLEN Transmit Frame Sync Length 16 4 FSLEN_EXT FSLEN Field Extension 28 4 FSOS Transmit Frame Sync Output Selection 20 3 FSOSSelect NONE None, TF pin is an input 0 NEGATIVE Negative Pulse, TF pin is an output 1 POSITIVE Positive Pulse, TF pin is an output 2 LOW Driven Low during data transfer 3 HIGH Driven High during data transfer 4 TOGGLING Toggling at each start of data transfer 5 MSBF Most Significant Bit First 7 1 THR Transmit Holding Register 0x24 32 write-only n 0x0 0x0 TDAT Transmit Data 0 32 TSHR Transmit Sync. Holding Register 0x34 32 read-write n 0x0 0x0 TSDAT Transmit Synchronization Data 0 16 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5460803 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protect Violation Source 8 16 SUPC Supply Controller SUPC 0x0 0x0 0x18 registers n SUPC 0 CR Supply Controller Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 165 VROFF Voltage Regulator Off 2 1 VROFFSelect NO_EFFECT No effect. 0 STOP_VREG If KEY is correct, VROFF asserts the vddcore_nreset and stops the voltage regulator. 1 XTALSEL Crystal Oscillator Select 3 1 XTALSELSelect NO_EFFECT No effect. 0 CRYSTAL_SEL If KEY is correct, XTALSEL switches the slow clock on the crystal oscillator output. 1 MR Supply Controller Mode Register 0x8 32 read-write n 0x0 0x0 BKUPRETON SRAM On In Backup Mode 17 1 BODDIS Brownout Detector Disable 13 1 BODDISSelect ENABLE The core brownout detector is enabled. 0 DISABLE The core brownout detector is disabled. 1 BODRSTEN Brownout Detector Reset Enable 12 1 BODRSTENSelect NOT_ENABLE The core reset signal vddcore_nreset is not affected when a brownout detection occurs. 0 ENABLE The core reset signal, vddcore_nreset is asserted when a brownout detection occurs. 1 KEY Password Key 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 165 ONREG Voltage Regulator Enable 14 1 ONREGSelect ONREG_UNUSED Internal voltage regulator is not used (external power supply is used). 0 ONREG_USED Internal voltage regulator is used. 1 OSCBYPASS Oscillator Bypass 20 1 OSCBYPASSSelect NO_EFFECT No effect. Clock selection depends on the value of XTALSEL (SUPC_CR). 0 BYPASS The 32 kHz crystal oscillator is bypassed if XTALSEL (SUPC_CR) is set. OSCBYPASS must be set prior to setting XTALSEL. 1 SMMR Supply Controller Supply Monitor Mode Register 0x4 32 read-write n 0x0 0x0 SMIEN Supply Monitor Interrupt Enable 13 1 SMIENSelect NOT_ENABLE The SUPC interrupt signal is not affected when a supply monitor detection occurs. 0 ENABLE The SUPC interrupt signal is asserted when a supply monitor detection occurs. 1 SMRSTEN Supply Monitor Reset Enable 12 1 SMRSTENSelect NOT_ENABLE The core reset signal vddcore_nreset is not affected when a supply monitor detection occurs. 0 ENABLE The core reset signal, vddcore_nreset is asserted when a supply monitor detection occurs. 1 SMSMPL Supply Monitor Sampling Period 8 3 SMSMPLSelect SMD Supply Monitor disabled 0 CSM Continuous Supply Monitor 1 _32SLCK Supply Monitor enabled one SLCK period every 32 SLCK periods 2 _256SLCK Supply Monitor enabled one SLCK period every 256 SLCK periods 3 _2048SLCK Supply Monitor enabled one SLCK period every 2,048 SLCK periods 4 SMTH Supply Monitor Threshold 0 4 SR Supply Controller Status Register 0x14 32 read-only n 0x0 0x0 BODRSTS Brownout Detector Reset Status (cleared on read) 3 1 BODRSTSSelect NO No core brownout rising edge event has been detected since the last read of the SUPC_SR. 0 PRESENT At least one brownout output rising edge event has been detected since the last read of the SUPC_SR. 1 LPDBCS0 Low-power Debouncer Wake-up Status on WKUP0 (cleared on read) 13 1 LPDBCS0Select NO No wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 0 PRESENT At least one wake-up due to the assertion of the WKUP0 pin has occurred since the last read of SUPC_SR. 1 LPDBCS1 Low-power Debouncer Wake-up Status on WKUP1 (cleared on read) 14 1 LPDBCS1Select NO No wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. 0 PRESENT At least one wake-up due to the assertion of the WKUP1 pin has occurred since the last read of SUPC_SR. 1 OSCSEL 32-kHz Oscillator Selection Status 7 1 OSCSELSelect RC The slow clock, SLCK, is generated by the embedded 32 kHz RC oscillator. 0 CRYST The slow clock, SLCK, is generated by the 32 kHz crystal oscillator. 1 SMOS Supply Monitor Output Status 6 1 SMOSSelect HIGH The supply monitor detected VDDIO higher than its threshold at its last measurement. 0 LOW The supply monitor detected VDDIO lower than its threshold at its last measurement. 1 SMRSTS Supply Monitor Reset Status (cleared on read) 4 1 SMRSTSSelect NO No supply monitor detection has generated a core reset since the last read of the SUPC_SR. 0 PRESENT At least one supply monitor detection has generated a core reset since the last read of the SUPC_SR. 1 SMS Supply Monitor Status (cleared on read) 5 1 SMSSelect NO No supply monitor detection since the last read of SUPC_SR. 0 PRESENT At least one supply monitor detection since the last read of SUPC_SR. 1 SMWS Supply Monitor Detection Wake-up Status (cleared on read) 2 1 SMWSSelect NO No wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 0 PRESENT At least one wake-up due to a supply monitor detection has occurred since the last read of SUPC_SR. 1 WKUPIS0 WKUPx Input Status (cleared on read) 16 1 WKUPIS0Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS1 WKUPx Input Status (cleared on read) 17 1 WKUPIS1Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS10 WKUPx Input Status (cleared on read) 26 1 WKUPIS10Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS11 WKUPx Input Status (cleared on read) 27 1 WKUPIS11Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS12 WKUPx Input Status (cleared on read) 28 1 WKUPIS12Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS13 WKUPx Input Status (cleared on read) 29 1 WKUPIS13Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS2 WKUPx Input Status (cleared on read) 18 1 WKUPIS2Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS3 WKUPx Input Status (cleared on read) 19 1 WKUPIS3Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS4 WKUPx Input Status (cleared on read) 20 1 WKUPIS4Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS5 WKUPx Input Status (cleared on read) 21 1 WKUPIS5Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS6 WKUPx Input Status (cleared on read) 22 1 WKUPIS6Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS7 WKUPx Input Status (cleared on read) 23 1 WKUPIS7Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS8 WKUPx Input Status (cleared on read) 24 1 WKUPIS8Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPIS9 WKUPx Input Status (cleared on read) 25 1 WKUPIS9Select DIS The corresponding wake-up input is disabled, or was inactive at the time the debouncer triggered a wake-up event. 0 EN The corresponding wake-up input was active at the time the debouncer triggered a wake-up event since the last read of SUPC_SR. 1 WKUPS WKUP Wake-up Status (cleared on read) 1 1 WKUPSSelect NO No wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 0 PRESENT At least one wake-up due to the assertion of the WKUP pins has occurred since the last read of SUPC_SR. 1 WUIR Supply Controller Wake-up Inputs Register 0x10 32 read-write n 0x0 0x0 WKUPEN0 Wake-up Input Enable 0 to 0 0 1 WKUPEN0Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN1 Wake-up Input Enable 0 to 1 1 1 WKUPEN1Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN10 Wake-up Input Enable 0 to 10 10 1 WKUPEN10Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN11 Wake-up Input Enable 0 to 11 11 1 WKUPEN11Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN12 Wake-up Input Enable 0 to 12 12 1 WKUPEN12Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN13 Wake-up Input Enable 0 to 13 13 1 WKUPEN13Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN2 Wake-up Input Enable 0 to 2 2 1 WKUPEN2Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN3 Wake-up Input Enable 0 to 3 3 1 WKUPEN3Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN4 Wake-up Input Enable 0 to 4 4 1 WKUPEN4Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN5 Wake-up Input Enable 0 to 5 5 1 WKUPEN5Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN6 Wake-up Input Enable 0 to 6 6 1 WKUPEN6Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN7 Wake-up Input Enable 0 to 7 7 1 WKUPEN7Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN8 Wake-up Input Enable 0 to 8 8 1 WKUPEN8Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPEN9 Wake-up Input Enable 0 to 9 9 1 WKUPEN9Select DISABLE The corresponding wake-up input has no wake-up effect. 0 ENABLE The corresponding wake-up input is enabled for a wake-up of the core power supply. 1 WKUPT0 Wake-up Input Type 0 to 0 16 1 WKUPT0Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT1 Wake-up Input Type 0 to 1 17 1 WKUPT1Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT10 Wake-up Input Type 0 to 10 26 1 WKUPT10Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT11 Wake-up Input Type 0 to 11 27 1 WKUPT11Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT12 Wake-up Input Type 0 to 12 28 1 WKUPT12Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT13 Wake-up Input Type 0 to 13 29 1 WKUPT13Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT2 Wake-up Input Type 0 to 2 18 1 WKUPT2Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT3 Wake-up Input Type 0 to 3 19 1 WKUPT3Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT4 Wake-up Input Type 0 to 4 20 1 WKUPT4Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT5 Wake-up Input Type 0 to 5 21 1 WKUPT5Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT6 Wake-up Input Type 0 to 6 22 1 WKUPT6Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT7 Wake-up Input Type 0 to 7 23 1 WKUPT7Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT8 Wake-up Input Type 0 to 8 24 1 WKUPT8Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WKUPT9 Wake-up Input Type 0 to 9 25 1 WKUPT9Select LOW A falling edge followed by a low level for a period defined by WKUPDBC on the corre-sponding wake-up input forces the wake-up of the core power supply. 0 HIGH A rising edge followed by a high level for a period defined by WKUPDBC on the cor-responding wake-up input forces the wake-up of the core power supply. 1 WUMR Supply Controller Wake-up Mode Register 0xC 32 read-write n 0x0 0x0 LPDBC Low-power Debouncer Period 16 3 LPDBCSelect DISABLE Disable the low-power debouncers. 0 _2_RTCOUT WKUP0/1 in active state for at least 2 RTCOUTx clock periods 1 _3_RTCOUT WKUP0/1 in active state for at least 3 RTCOUTx clock periods 2 _4_RTCOUT WKUP0/1 in active state for at least 4 RTCOUTx clock periods 3 _5_RTCOUT WKUP0/1 in active state for at least 5 RTCOUTx clock periods 4 _6_RTCOUT WKUP0/1 in active state for at least 6 RTCOUTx clock periods 5 _7_RTCOUT WKUP0/1 in active state for at least 7 RTCOUTx clock periods 6 _8_RTCOUT WKUP0/1 in active state for at least 8 RTCOUTx clock periods 7 LPDBCCLR Low-power Debouncer Clear 7 1 LPDBCCLRSelect NOT_ENABLE A low-power debounce event does not create an immediate clear on the first half of GPBR registers. 0 ENABLE A low-power debounce event on WKUP0 or WKUP1 generates an immediate clear on the first half of GPBR registers. 1 LPDBCEN0 Low-power Debouncer Enable WKUP0 5 1 LPDBCEN0Select NOT_ENABLE The WKUP0 input pin is not connected to the low-power debouncer. 0 ENABLE The WKUP0 input pin is connected to the low-power debouncer and forces a system wake-up. 1 LPDBCEN1 Low-power Debouncer Enable WKUP1 6 1 LPDBCEN1Select NOT_ENABLE The WKUP1 input pin is not connected to the low-power debouncer. 0 ENABLE The WKUP1 input pin is connected to the low-power debouncer and forces a system wake-up. 1 RTCEN Real-time Clock Wake-up Enable 3 1 RTCENSelect NOT_ENABLE The RTC alarm signal has no wake-up effect. 0 ENABLE The RTC alarm signal forces the wake-up of the core power supply. 1 RTTEN Real-time Timer Wake-up Enable 2 1 RTTENSelect NOT_ENABLE The RTT alarm signal has no wake-up effect. 0 ENABLE The RTT alarm signal forces the wake-up of the core power supply. 1 SMEN Supply Monitor Wake-up Enable 1 1 SMENSelect NOT_ENABLE The supply monitor detection has no wake-up effect. 0 ENABLE The supply monitor detection forces the wake-up of the core power supply. 1 WKUPDBC Wake-up Inputs Debouncer Period 12 3 WKUPDBCSelect IMMEDIATE Immediate, no debouncing, detected active at least on one Slow Clock edge. 0 _3_SLCK WKUPx shall be in its active state for at least 3 SLCK periods 1 _32_SLCK WKUPx shall be in its active state for at least 32 SLCK periods 2 _512_SLCK WKUPx shall be in its active state for at least 512 SLCK periods 3 _4096_SLCK WKUPx shall be in its active state for at least 4,096 SLCK periods 4 _32768_SLCK WKUPx shall be in its active state for at least 32,768 SLCK periods 5 SysTick System timer SysTick 0x0 0x0 0x10 registers n CALIB Calibration Value Register 0xC 32 read-only n 0x0 0x0 NOREF Indicates whether the device provides a reference clock to the processor 31 1 NOREFSelect VALUE_0 The reference clock is provided 0 VALUE_1 The reference clock is not provided 1 SKEW Indicates whether the TENMS value is exact 30 1 SKEWSelect VALUE_0 10ms calibration value is exact 0 VALUE_1 10ms calibration value is inexact, because of the clock frequency 1 TENMS Reload value to use for 10ms timing 0 24 CSR Control and Status Register 0x0 32 read-write n 0x0 0x0 CLKSOURCE Indicates the clock source 2 1 CLKSOURCESelect VALUE_0 external clock 0 VALUE_1 processor clock 1 COUNTFLAG Returns 1 if timer counted to 0 since last time this was read 16 1 ENABLE Enables the counter 0 1 ENABLESelect VALUE_0 counter disabled 0 VALUE_1 counter enabled 1 TICKINT Enables SysTick exception request 1 1 TICKINTSelect VALUE_0 counting down to 0 does not assert the SysTick exception request 0 VALUE_1 counting down to 0 asserts the SysTick exception request 1 CVR Current Value Register 0x8 32 read-write n 0x0 0x0 CURRENT Current value at the time the register is accessed 0 24 RVR Reload Value Register 0x4 32 read-write n 0x0 0x0 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 TC0 Timer Counter 0 TC 0x0 0x0 0xE8 registers n 0x0 0x4000 registers n TC0 23 TC1 24 TC2 25 BCR Block Control Register 0xC0 32 write-only n SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 CV Counter Value 0 32 read-only EMR0 Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 EMR1 Extended Mode Register (channel = 1) 0x70 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 EMR2 Extended Mode Register (channel = 2) 0xB0 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 RA Register A 0 32 read-write RAB0 Register AB (channel = 0) 0xC 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RAB1 Register AB (channel = 1) 0x4C 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RAB2 Register AB (channel = 2) 0x8C 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only TC_TC_BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 TC_TC_BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0 TIOA1 Signal connected to XC0: TIOA1 2 TIOA2 Signal connected to XC0: TIOA2 3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0 TIOA0 Signal connected to XC1: TIOA0 2 TIOA2 Signal connected to XC1: TIOA2 3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0 TIOA0 Signal connected to XC2: TIOA0 2 TIOA1 Signal connected to XC2: TIOA1 3 TC_TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0x44 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0x70 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0x4C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0xC0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0xC4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0xD0 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0xF0 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0xE8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0xE4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0xEC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0xD4 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0xCC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0xD8 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0xDC 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0xC8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0xE0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 TC_TC_QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5523789 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC1 Timer Counter TC 0x0 0x0 0xE8 registers n 0x0 0x4000 registers n TC3 26 TC4 27 TC5 28 BCR Block Control Register 0xC0 32 write-only n SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 CV Counter Value 0 32 read-only EMR0 Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 EMR1 Extended Mode Register (channel = 1) 0x70 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 EMR2 Extended Mode Register (channel = 2) 0xB0 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 RA Register A 0 32 read-write RAB0 Register AB (channel = 0) 0xC 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RAB1 Register AB (channel = 1) 0x4C 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RAB2 Register AB (channel = 2) 0x8C 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only TC_TC_BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 TC_TC_BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0 TIOA1 Signal connected to XC0: TIOA1 2 TIOA2 Signal connected to XC0: TIOA2 3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0 TIOA0 Signal connected to XC1: TIOA0 2 TIOA2 Signal connected to XC1: TIOA2 3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0 TIOA0 Signal connected to XC2: TIOA0 2 TIOA1 Signal connected to XC2: TIOA1 3 TC_TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0x44 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0x70 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0x4C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0xC0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0xC4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0xD0 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0xF0 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0xE8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0xE4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0xEC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0xD4 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0xCC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0xD8 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0xDC 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0xC8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0xE0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 TC_TC_QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5523789 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC2 Timer Counter TC 0x0 0x0 0xE8 registers n 0x0 0x4000 registers n TC6 47 TC7 48 TC8 49 BCR Block Control Register 0xC0 32 write-only n SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 CV Counter Value 0 32 read-only EMR0 Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 EMR1 Extended Mode Register (channel = 1) 0x70 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 EMR2 Extended Mode Register (channel = 2) 0xB0 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 RA Register A 0 32 read-write RAB0 Register AB (channel = 0) 0xC 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RAB1 Register AB (channel = 1) 0x4C 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RAB2 Register AB (channel = 2) 0x8C 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only TC_TC_BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 TC_TC_BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0 TIOA1 Signal connected to XC0: TIOA1 2 TIOA2 Signal connected to XC0: TIOA2 3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0 TIOA0 Signal connected to XC1: TIOA0 2 TIOA2 Signal connected to XC1: TIOA2 3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0 TIOA0 Signal connected to XC2: TIOA0 2 TIOA1 Signal connected to XC2: TIOA1 3 TC_TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0x44 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0x70 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0x4C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0xC0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0xC4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0xD0 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0xF0 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0xE8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0xE4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0xEC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0xD4 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0xCC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0xD8 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0xDC 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0xC8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0xE0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 TC_TC_QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5523789 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TC3 Timer Counter 3 TC 0x0 0x0 0xE8 registers n 0x0 0x4000 registers n TC9 50 TC10 51 TC11 52 BCR Block Control Register 0xC0 32 write-only n SYNC Synchro Command 0 1 write-only BMR Block Mode Register 0xC4 32 read-write n 0x0 EDGPHA Edge on PHA Count Mode 12 1 read-write IDXPHB Index Pin is PHB Pin 17 1 read-write INVA Inverted PHA 13 1 read-write INVB Inverted PHB 14 1 read-write INVIDX Inverted Index 15 1 read-write MAXFILT Maximum Filter 20 6 read-write POSEN Position Enabled 9 1 read-write QDEN Quadrature Decoder Enabled 8 1 read-write QDTRANS Quadrature Decoding Transparent 11 1 read-write SPEEDEN Speed Enabled 10 1 read-write SWAP Swap PHA and PHB 16 1 read-write TC0XC0S External Clock Signal 0 Selection 0 2 read-write TCLK0 Signal connected to XC0: TCLK0 0x0 TIOA1 Signal connected to XC0: TIOA1 0x2 TIOA2 Signal connected to XC0: TIOA2 0x3 TC1XC1S External Clock Signal 1 Selection 2 2 read-write TCLK1 Signal connected to XC1: TCLK1 0x0 TIOA0 Signal connected to XC1: TIOA0 0x2 TIOA2 Signal connected to XC1: TIOA2 0x3 TC2XC2S External Clock Signal 2 Selection 4 2 read-write TCLK2 Signal connected to XC2: TCLK2 0x0 TIOA0 Signal connected to XC2: TIOA0 0x2 TIOA1 Signal connected to XC2: TIOA1 0x3 CCR0 Channel Control Register (channel = 0) 0x0 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR1 Channel Control Register (channel = 1) 0x40 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CCR2 Channel Control Register (channel = 2) 0x80 32 write-only n CLKDIS Counter Clock Disable Command 1 1 write-only CLKEN Counter Clock Enable Command 0 1 write-only SWTRG Software Trigger Command 2 1 write-only CMR0 Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR0_WAVEFORM_MODE Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR1 Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR1_WAVEFORM_MODE Channel Mode Register (channel = 1) 0x44 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CMR2 Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 ABETRG TIOA or TIOB External Trigger Selection 10 1 read-write BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCTRG RC Compare Trigger Enable 14 1 read-write ETRGEDG External Trigger Edge Selection 8 2 read-write NONE The clock is not gated by an external signal. 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 LDBDIS Counter Clock Disable with RB Loading 7 1 read-write LDBSTOP Counter Clock Stopped with RB Loading 6 1 read-write LDRA RA Loading Edge Selection 16 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 LDRB RB Loading Edge Selection 18 2 read-write NONE None 0x0 RISING Rising edge of TIOA 0x1 FALLING Falling edge of TIOA 0x2 EDGE Each edge of TIOA 0x3 SBSMPLR Loading Edge Subsampling Ratio 20 3 read-write ONE Load a Capture Register each selected edge 0x0 HALF Load a Capture Register every 2 selected edges 0x1 FOURTH Load a Capture Register every 4 selected edges 0x2 EIGHTH Load a Capture Register every 8 selected edges 0x3 SIXTEENTH Load a Capture Register every 16 selected edges 0x4 TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write CMR2_WAVEFORM_MODE Channel Mode Register (channel = 2) 0x84 32 read-write n 0x0 ACPA RA Compare Effect on TIOA 16 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ACPC RC Compare Effect on TIOA 18 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 AEEVT External Event Effect on TIOA 20 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 ASWTRG Software Trigger Effect on TIOA 22 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPB RB Compare Effect on TIOB 24 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BCPC RC Compare Effect on TIOB 26 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BEEVT External Event Effect on TIOB 28 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BSWTRG Software Trigger Effect on TIOB 30 2 read-write NONE None 0x0 SET Set 0x1 CLEAR Clear 0x2 TOGGLE Toggle 0x3 BURST Burst Signal Selection 4 2 read-write NONE The clock is not gated by an external signal. 0x0 XC0 XC0 is ANDed with the selected clock. 0x1 XC1 XC1 is ANDed with the selected clock. 0x2 XC2 XC2 is ANDed with the selected clock. 0x3 CLKI Clock Invert 3 1 read-write CPCDIS Counter Clock Disable with RC Compare 7 1 read-write CPCSTOP Counter Clock Stopped with RC Compare 6 1 read-write EEVT External Event Selection 10 2 read-write TIOB TIOB 0x0 XC0 XC0 0x1 XC1 XC1 0x2 XC2 XC2 0x3 EEVTEDG External Event Edge Selection 8 2 read-write NONE None 0x0 RISING Rising edge 0x1 FALLING Falling edge 0x2 EDGE Each edge 0x3 ENETRG External Event Trigger Enable 12 1 read-write TCCLKS Clock Selection 0 3 read-write TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0x0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 0x1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 0x2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 0x3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 0x4 XC0 Clock selected: XC0 0x5 XC1 Clock selected: XC1 0x6 XC2 Clock selected: XC2 0x7 WAVE Waveform Mode 15 1 read-write WAVSEL Waveform Selection 13 2 read-write UP UP mode without automatic trigger on RC Compare 0x0 UPDOWN UPDOWN mode without automatic trigger on RC Compare 0x1 UP_RC UP mode with automatic trigger on RC Compare 0x2 UPDOWN_RC UPDOWN mode with automatic trigger on RC Compare 0x3 CV0 Counter Value (channel = 0) 0x10 32 read-only n 0x0 CV Counter Value 0 32 read-only CV1 Counter Value (channel = 1) 0x50 32 read-only n 0x0 CV Counter Value 0 32 read-only CV2 Counter Value (channel = 2) 0x90 32 read-only n 0x0 CV Counter Value 0 32 read-only EMR0 Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 EMR1 Extended Mode Register (channel = 1) 0x70 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 EMR2 Extended Mode Register (channel = 2) 0xB0 32 read-write n 0x0 NODIVCLK No Divided Clock 8 1 read-write TRIGSRCA Trigger Source for Input A 0 2 read-write EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 read-write EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP singal of the Ethernet MAC (GMAC). 1 FMR Fault Mode Register 0xD8 32 read-write n 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 read-write ENCF1 Enable Compare Fault Channel 1 1 1 read-write IDR0 Interrupt Disable Register (channel = 0) 0x28 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR1 Interrupt Disable Register (channel = 1) 0x68 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IDR2 Interrupt Disable Register (channel = 2) 0xA8 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER0 Interrupt Enable Register (channel = 0) 0x24 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER1 Interrupt Enable Register (channel = 1) 0x64 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IER2 Interrupt Enable Register (channel = 2) 0xA4 32 write-only n COVFS Counter Overflow 0 1 write-only CPAS RA Compare 2 1 write-only CPBS RB Compare 3 1 write-only CPCS RC Compare 4 1 write-only ETRGS External Trigger 7 1 write-only LDRAS RA Loading 5 1 write-only LDRBS RB Loading 6 1 write-only LOVRS Load Overrun 1 1 write-only IMR0 Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR1 Interrupt Mask Register (channel = 1) 0x6C 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only IMR2 Interrupt Mask Register (channel = 2) 0xAC 32 read-only n 0x0 COVFS Counter Overflow 0 1 read-only CPAS RA Compare 2 1 read-only CPBS RB Compare 3 1 read-only CPCS RC Compare 4 1 read-only ETRGS External Trigger 7 1 read-only LDRAS RA Loading 5 1 read-only LDRBS RB Loading 6 1 read-only LOVRS Load Overrun 1 1 read-only QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIER QDEC Interrupt Enable Register 0xC8 32 write-only n DIRCHG Direction Change 1 1 write-only IDX Index 0 1 write-only QERR Quadrature Error 2 1 write-only QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 DIR Direction 8 1 read-only DIRCHG Direction Change 1 1 read-only IDX Index 0 1 read-only QERR Quadrature Error 2 1 read-only RA0 Register A (channel = 0) 0x14 32 read-write n 0x0 RA Register A 0 32 read-write RA1 Register A (channel = 1) 0x54 32 read-write n 0x0 RA Register A 0 32 read-write RA2 Register A (channel = 2) 0x94 32 read-write n 0x0 RA Register A 0 32 read-write RAB0 Register AB (channel = 0) 0xC 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RAB1 Register AB (channel = 1) 0x4C 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RAB2 Register AB (channel = 2) 0x8C 32 read-only n 0x0 RAB Register A or Register B 0 32 read-only RB0 Register B (channel = 0) 0x18 32 read-write n 0x0 RB Register B 0 32 read-write RB1 Register B (channel = 1) 0x58 32 read-write n 0x0 RB Register B 0 32 read-write RB2 Register B (channel = 2) 0x98 32 read-write n 0x0 RB Register B 0 32 read-write RC0 Register C (channel = 0) 0x1C 32 read-write n 0x0 RC Register C 0 32 read-write RC1 Register C (channel = 1) 0x5C 32 read-write n 0x0 RC Register C 0 32 read-write RC2 Register C (channel = 2) 0x9C 32 read-write n 0x0 RC Register C 0 32 read-write SMMR0 Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR1 Stepper Motor Mode Register (channel = 1) 0x48 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SMMR2 Stepper Motor Mode Register (channel = 2) 0x88 32 read-write n 0x0 DOWN Down Count 1 1 read-write GCEN Gray Count Enable 0 1 read-write SR0 Status Register (channel = 0) 0x20 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR1 Status Register (channel = 1) 0x60 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only SR2 Status Register (channel = 2) 0xA0 32 read-only n 0x0 CLKSTA Clock Enabling Status 16 1 read-only COVFS Counter Overflow Status (cleared on read) 0 1 read-only CPAS RA Compare Status (cleared on read) 2 1 read-only CPBS RB Compare Status (cleared on read) 3 1 read-only CPCS RC Compare Status (cleared on read) 4 1 read-only ETRGS External Trigger Status (cleared on read) 7 1 read-only LDRAS RA Loading Status (cleared on read) 5 1 read-only LDRBS RB Loading Status (cleared on read) 6 1 read-only LOVRS Load Overrun Status (cleared on read) 1 1 read-only MTIOA TIOA Mirror 17 1 read-only MTIOB TIOB Mirror 18 1 read-only TC_TC_BCR Block Control Register 0xC0 32 write-only n 0x0 0x0 SYNC Synchro Command 0 1 TC_TC_BMR Block Mode Register 0xC4 32 read-write n 0x0 0x0 EDGPHA Edge on PHA Count Mode 12 1 IDXPHB Index Pin is PHB Pin 17 1 INVA Inverted PHA 13 1 INVB Inverted PHB 14 1 INVIDX Inverted Index 15 1 MAXFILT Maximum Filter 20 6 POSEN Position Enabled 9 1 QDEN Quadrature Decoder Enabled 8 1 QDTRANS Quadrature Decoding Transparent 11 1 SPEEDEN Speed Enabled 10 1 SWAP Swap PHA and PHB 16 1 TC0XC0S External Clock Signal 0 Selection 0 2 TC0XC0SSelect TCLK0 Signal connected to XC0: TCLK0 0 TIOA1 Signal connected to XC0: TIOA1 2 TIOA2 Signal connected to XC0: TIOA2 3 TC1XC1S External Clock Signal 1 Selection 2 2 TC1XC1SSelect TCLK1 Signal connected to XC1: TCLK1 0 TIOA0 Signal connected to XC1: TIOA0 2 TIOA2 Signal connected to XC1: TIOA2 3 TC2XC2S External Clock Signal 2 Selection 4 2 TC2XC2SSelect TCLK2 Signal connected to XC2: TCLK2 0 TIOA0 Signal connected to XC2: TIOA0 2 TIOA1 Signal connected to XC2: TIOA1 3 TC_TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0x0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0x4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0x10 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0x30 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0x28 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0x24 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0x2C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0x14 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0xC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0x18 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0x1C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0x8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0x20 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0x40 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0x44 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0x50 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0x70 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0x68 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0x64 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0x6C 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0x54 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0x4C 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0x58 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0x5C 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0x48 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0x60 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CCR Channel Control Register (channel = 0) 0xC0 32 write-only n 0x0 0x0 CLKDIS Counter Clock Disable Command 1 1 CLKEN Counter Clock Enable Command 0 1 SWTRG Software Trigger Command 2 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CMR Channel Mode Register (channel = 0) 0xC4 32 read-write n 0x0 0x0 ABETRG TIOAx or TIOBx External Trigger Selection 10 1 BURST Burst Signal Selection 4 2 BURSTSelect NONE The clock is not gated by an external signal. 0 XC0 XC0 is ANDed with the selected clock. 1 XC1 XC1 is ANDed with the selected clock. 2 XC2 XC2 is ANDed with the selected clock. 3 CLKI Clock Invert 3 1 CPCTRG RC Compare Trigger Enable 14 1 ETRGEDG External Trigger Edge Selection 8 2 ETRGEDGSelect NONE The clock is not gated by an external signal. 0 RISING Rising edge 1 FALLING Falling edge 2 EDGE Each edge 3 LDBDIS Counter Clock Disable with RB Loading 7 1 LDBSTOP Counter Clock Stopped with RB Loading 6 1 LDRA RA Loading Edge Selection 16 2 LDRASelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 LDRB RB Loading Edge Selection 18 2 LDRBSelect NONE None 0 RISING Rising edge of TIOAx 1 FALLING Falling edge of TIOAx 2 EDGE Each edge of TIOAx 3 SBSMPLR Loading Edge Subsampling Ratio 20 3 SBSMPLRSelect ONE Load a Capture Register each selected edge 0 HALF Load a Capture Register every 2 selected edges 1 FOURTH Load a Capture Register every 4 selected edges 2 EIGHTH Load a Capture Register every 8 selected edges 3 SIXTEENTH Load a Capture Register every 16 selected edges 4 TCCLKS Clock Selection 0 3 TCCLKSSelect TIMER_CLOCK1 Clock selected: internal PCK6 clock signal (from PMC) 0 TIMER_CLOCK2 Clock selected: internal MCK/8 clock signal (from PMC) 1 TIMER_CLOCK3 Clock selected: internal MCK/32 clock signal (from PMC) 2 TIMER_CLOCK4 Clock selected: internal MCK/128 clock signal (from PMC) 3 TIMER_CLOCK5 Clock selected: internal SLCK clock signal (from PMC) 4 XC0 Clock selected: XC0 5 XC1 Clock selected: XC1 6 XC2 Clock selected: XC2 7 WAVE Waveform Mode 15 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_CV Counter Value (channel = 0) 0xD0 32 read-only n 0x0 0x0 CV Counter Value 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_EMR Extended Mode Register (channel = 0) 0xF0 32 read-write n 0x0 0x0 NODIVCLK No Divided Clock 8 1 TRIGSRCA Trigger Source for Input A 0 2 TRIGSRCASelect EXTERNAL_TIOAx The trigger/capture input A is driven by external pin TIOAx 0 PWMx The trigger/capture input A is driven internally by PWMx 1 TRIGSRCB Trigger Source for Input B 4 2 TRIGSRCBSelect EXTERNAL_TIOBx The trigger/capture input B is driven by external pin TIOBx 0 PWMx For TC0 to TC10: The trigger/capture input B is driven internally by the comparator output (see Figure 7-16) of the PWMx.For TC11: The trigger/capture input B is driven internally by the GTSUCOMP signal of the Ethernet MAC (GMAC). 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IDR Interrupt Disable Register (channel = 0) 0xE8 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IER Interrupt Enable Register (channel = 0) 0xE4 32 write-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_IMR Interrupt Mask Register (channel = 0) 0xEC 32 read-only n 0x0 0x0 COVFS Counter Overflow 0 1 CPAS RA Compare 2 1 CPBS RB Compare 3 1 CPCS RC Compare 4 1 ETRGS External Trigger 7 1 LDRAS RA Loading 5 1 LDRBS RB Loading 6 1 LOVRS Load Overrun 1 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RA Register A (channel = 0) 0xD4 32 read-write n 0x0 0x0 RA Register A 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RAB Register AB (channel = 0) 0xCC 32 read-only n 0x0 0x0 RAB Register A or Register B 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RB Register B (channel = 0) 0xD8 32 read-write n 0x0 0x0 RB Register B 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_RC Register C (channel = 0) 0xDC 32 read-write n 0x0 0x0 RC Register C 0 32 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SMMR Stepper Motor Mode Register (channel = 0) 0xC8 32 read-write n 0x0 0x0 DOWN Down Count 1 1 GCEN Gray Count Enable 0 1 TC_TC_CHANNEL[2]-TC_CHANNEL[1]-TC_CHANNEL[0]-TC_SR Status Register (channel = 0) 0xE0 32 read-only n 0x0 0x0 CLKSTA Clock Enabling Status 16 1 COVFS Counter Overflow Status (cleared on read) 0 1 CPAS RA Compare Status (cleared on read) 2 1 CPBS RB Compare Status (cleared on read) 3 1 CPCS RC Compare Status (cleared on read) 4 1 ETRGS External Trigger Status (cleared on read) 7 1 LDRAS RA Loading Status (cleared on read) 5 1 LDRBS RB Loading Status (cleared on read) 6 1 LOVRS Load Overrun Status (cleared on read) 1 1 MTIOA TIOAx Mirror 17 1 MTIOB TIOBx Mirror 18 1 TC_TC_FMR Fault Mode Register 0xD8 32 read-write n 0x0 0x0 ENCF0 Enable Compare Fault Channel 0 0 1 ENCF1 Enable Compare Fault Channel 1 1 1 TC_TC_QIDR QDEC Interrupt Disable Register 0xCC 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QIER QDEC Interrupt Enable Register 0xC8 32 write-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QIMR QDEC Interrupt Mask Register 0xD0 32 read-only n 0x0 0x0 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_QISR QDEC Interrupt Status Register 0xD4 32 read-only n 0x0 0x0 DIR Direction 8 1 DIRCHG Direction Change 1 1 IDX Index 0 1 QERR Quadrature Error 2 1 TC_TC_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 5523789 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0. 0x54494D TRNG True Random Number Generator TRNG 0x0 0x0 0x54 registers n TRNG 57 CR Control Register 0x0 32 write-only n 0x0 0x0 ENABLE Enables the TRNG to Provide Random Values 0 1 KEY Security Key 8 24 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 5393991 IDR Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Disable 0 1 IER Interrupt Enable Register 0x10 32 write-only n 0x0 0x0 DATRDY Data Ready Interrupt Enable 0 1 IMR Interrupt Mask Register 0x18 32 read-only n 0x0 0x0 DATRDY Data Ready Interrupt Mask 0 1 ISR Interrupt Status Register 0x1C 32 read-only n 0x0 0x0 DATRDY Data Ready 0 1 ODATA Output Data Register 0x50 32 read-only n 0x0 0x0 ODATA Output Data 0 32 TWIHS0 Two-wire Interface High Speed 0 TWIHS 0x0 0x0 0x4000 registers n TWIHS0 19 CR Control Register 0x0 32 write-only n CLEAR Bus CLEAR Command 15 1 write-only HSDIS TWIHS High-Speed Mode Disabled 9 1 write-only HSEN TWIHS High-Speed Mode Enabled 8 1 write-only MSDIS TWIHS Master Mode Disabled 3 1 write-only MSEN TWIHS Master Mode Enabled 2 1 write-only PECDIS Packet Error Checking Disable 13 1 write-only PECEN Packet Error Checking Enable 12 1 write-only PECRQ PEC Request 14 1 write-only QUICK SMBus Quick Command 6 1 write-only SMBDIS SMBus Mode Disabled 11 1 write-only SMBEN SMBus Mode Enabled 10 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWIHS Slave Mode Disabled 5 1 write-only SVEN TWIHS Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time Versus TWCK Falling 24 5 read-write FILTR Filter Register 0x44 32 read-write n 0x0 FILT RX Digital Filter 0 1 read-write PADFCFG PAD Filter Config 2 1 read-write PADFEN PAD Filter Enable 1 1 read-write THRES Digital Filter Threshold 8 3 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n ARBLST Arbitration Lost Interrupt Disable 9 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only MCACK Master Code Acknowledge Interrupt Disable 16 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only PECERR PEC Error Interrupt Disable 19 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SMBDAM SMBus Default Address Match Interrupt Disable 20 1 write-only SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TOUT Timeout Error Interrupt Disable 18 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only UNRE Underrun Error Interrupt Disable 7 1 write-only IER Interrupt Enable Register 0x24 32 write-only n ARBLST Arbitration Lost Interrupt Enable 9 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only MCACK Master Code Acknowledge Interrupt Enable 16 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only PECERR PEC Error Interrupt Enable 19 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SMBDAM SMBus Default Address Match Interrupt Enable 20 1 write-only SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TOUT Timeout Error Interrupt Enable 18 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only UNRE Underrun Error Interrupt Enable 7 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only MCACK Master Code Acknowledge Interrupt Mask 16 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only PECERR PEC Error Interrupt Mask 19 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SMBDAM SMBus Default Address Match Interrupt Mask 20 1 read-only SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TOUT Timeout Error Interrupt Mask 18 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only UNRE Underrun Error Interrupt Mask 7 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 PRESC SMBus Clock Prescaler 0 4 read-write THMAX Clock High Maximum Cycles 24 8 read-write TLOWM Master Clock Stretch Maximum Cycles 16 8 read-write TLOWS Slave Clock Stretch Maximum Cycles 8 8 read-write SMR Slave Mode Register 0x8 32 read-write n 0x0 DATAMEN Data Matching Enable 31 1 read-write MASK Slave Address Mask 8 7 read-write NACKEN Slave Receiver Data Phase NACK enable 0 1 read-write SADR Slave Address 16 7 read-write SADR1EN Slave Address 1 Enable 28 1 read-write SADR2EN Slave Address 2 Enable 29 1 read-write SADR3EN Slave Address 3 Enable 30 1 read-write SCLWSDIS Clock Wait State Disable 6 1 read-write SMDA SMBus Default Address 2 1 read-write SMHH SMBus Host Header 3 1 read-write SR Status Register 0x20 32 read-only n 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 read-only EOSACC End Of Slave Access (cleared on read) 11 1 read-only GACC General Call Access (cleared on read) 5 1 read-only MCACK Master Code Acknowledge (cleared on read) 16 1 read-only NACK Not Acknowledged (cleared on read) 8 1 read-only OVRE Overrun Error (cleared on read) 6 1 read-only PECERR PEC Error (cleared on read) 19 1 read-only RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 read-only SCL SCL Line Value 24 1 read-only SCLWS Clock Wait State 10 1 read-only SDA SDA Line Value 25 1 read-only SMBDAM SMBus Default Address Match (cleared on read) 20 1 read-only SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 read-only SVACC Slave Access 4 1 read-only SVREAD Slave Read 3 1 read-only TOUT Timeout Error (cleared on read) 18 1 read-only TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 read-only TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 read-only UNRE Underrun Error (cleared on read) 7 1 read-only SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 DATAM Data Match 24 8 read-write SADR1 Slave Address 1 0 7 read-write SADR2 Slave Address 2 8 7 read-write SADR3 Slave Address 3 16 7 read-write THR Transmit Holding Register 0x34 32 write-only n 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TWIHS_TWIHS_CR Control Register 0x0 32 write-only n 0x0 0x0 ACMDIS Alternative Command Mode Disable 17 1 ACMEN Alternative Command Mode Enable 16 1 CLEAR Bus CLEAR Command 15 1 FIFODIS FIFO Disable 29 1 FIFOEN FIFO Enable 28 1 HSDIS TWIHS High-Speed Mode Disabled 9 1 HSEN TWIHS High-Speed Mode Enabled 8 1 LOCKCLR Lock Clear 26 1 MSDIS TWIHS Master Mode Disabled 3 1 MSEN TWIHS Master Mode Enabled 2 1 PECDIS Packet Error Checking Disable 13 1 PECEN Packet Error Checking Enable 12 1 PECRQ PEC Request 14 1 QUICK SMBus Quick Command 6 1 SMBDIS SMBus Mode Disabled 11 1 SMBEN SMBus Mode Enabled 10 1 START Send a START Condition 0 1 STOP Send a STOP Condition 1 1 SVDIS TWIHS Slave Mode Disabled 5 1 SVEN TWIHS Slave Mode Enabled 4 1 SWRST Software Reset 7 1 THRCLR Transmit Holding Register Clear 24 1 TWIHS_TWIHS_CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 CKDIV Clock Divider 16 3 CLDIV Clock Low Divider 0 8 HOLD TWD Hold Time Versus TWCK Falling 24 6 TWIHS_TWIHS_FILTR Filter Register 0x44 32 read-write n 0x0 0x0 FILT RX Digital Filter 0 1 PADFCFG PAD Filter Config 2 1 PADFEN PAD Filter Enable 1 1 THRES Digital Filter Threshold 8 3 TWIHS_TWIHS_IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 TWIHS_TWIHS_IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 EOSACC End Of Slave Access Interrupt Disable 11 1 GACC General Call Access Interrupt Disable 5 1 MCACK Master Code Acknowledge Interrupt Disable 16 1 NACK Not Acknowledge Interrupt Disable 8 1 OVRE Overrun Error Interrupt Disable 6 1 PECERR PEC Error Interrupt Disable 19 1 RXRDY Receive Holding Register Ready Interrupt Disable 1 1 SCL_WS Clock Wait State Interrupt Disable 10 1 SMBDAM SMBus Default Address Match Interrupt Disable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 SVACC Slave Access Interrupt Disable 4 1 TOUT Timeout Error Interrupt Disable 18 1 TXCOMP Transmission Completed Interrupt Disable 0 1 TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 UNRE Underrun Error Interrupt Disable 7 1 TWIHS_TWIHS_IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 EOSACC End Of Slave Access Interrupt Enable 11 1 GACC General Call Access Interrupt Enable 5 1 MCACK Master Code Acknowledge Interrupt Enable 16 1 NACK Not Acknowledge Interrupt Enable 8 1 OVRE Overrun Error Interrupt Enable 6 1 PECERR PEC Error Interrupt Enable 19 1 RXRDY Receive Holding Register Ready Interrupt Enable 1 1 SCL_WS Clock Wait State Interrupt Enable 10 1 SMBDAM SMBus Default Address Match Interrupt Enable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 SVACC Slave Access Interrupt Enable 4 1 TOUT Timeout Error Interrupt Enable 18 1 TXCOMP Transmission Completed Interrupt Enable 0 1 TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 UNRE Underrun Error Interrupt Enable 7 1 TWIHS_TWIHS_IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 EOSACC End Of Slave Access Interrupt Mask 11 1 GACC General Call Access Interrupt Mask 5 1 MCACK Master Code Acknowledge Interrupt Mask 16 1 NACK Not Acknowledge Interrupt Mask 8 1 OVRE Overrun Error Interrupt Mask 6 1 PECERR PEC Error Interrupt Mask 19 1 RXRDY Receive Holding Register Ready Interrupt Mask 1 1 SCL_WS Clock Wait State Interrupt Mask 10 1 SMBDAM SMBus Default Address Match Interrupt Mask 20 1 SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 SVACC Slave Access Interrupt Mask 4 1 TOUT Timeout Error Interrupt Mask 18 1 TXCOMP Transmission Completed Interrupt Mask 0 1 TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 UNRE Underrun Error Interrupt Mask 7 1 TWIHS_TWIHS_MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 IADRSZ Internal Device Address Size 8 2 IADRSZSelect NONE No internal device address 0 _1_BYTE One-byte internal device address 1 _2_BYTE Two-byte internal device address 2 _3_BYTE Three-byte internal device address 3 MREAD Master Read Direction 12 1 TWIHS_TWIHS_RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 TWIHS_TWIHS_SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 0x0 PRESC SMBus Clock Prescaler 0 4 THMAX Clock High Maximum Cycles 24 8 TLOWM Master Clock Stretch Maximum Cycles 16 8 TLOWS Slave Clock Stretch Maximum Cycles 8 8 TWIHS_TWIHS_SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 DATAMEN Data Matching Enable 31 1 MASK Slave Address Mask 8 7 NACKEN Slave Receiver Data Phase NACK enable 0 1 SADR Slave Address 16 7 SADR1EN Slave Address 1 Enable 28 1 SADR2EN Slave Address 2 Enable 29 1 SADR3EN Slave Address 3 Enable 30 1 SCLWSDIS Clock Wait State Disable 6 1 SMDA SMBus Default Address 2 1 SMHH SMBus Host Header 3 1 TWIHS_TWIHS_SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 EOSACC End Of Slave Access (cleared on read) 11 1 GACC General Call Access (cleared on read) 5 1 MCACK Master Code Acknowledge (cleared on read) 16 1 NACK Not Acknowledged (cleared on read) 8 1 OVRE Overrun Error (cleared on read) 6 1 PECERR PEC Error (cleared on read) 19 1 RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 SCL SCL Line Value 24 1 SCLWS Clock Wait State 10 1 SDA SDA Line Value 25 1 SMBDAM SMBus Default Address Match (cleared on read) 20 1 SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 SVACC Slave Access 4 1 SVREAD Slave Read 3 1 TOUT Timeout Error (cleared on read) 18 1 TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 UNRE Underrun Error (cleared on read) 7 1 TWIHS_TWIHS_SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 0x0 DATAM Data Match 24 8 SADR1 Slave Address 1 0 7 SADR2 Slave Address 2 8 7 SADR3 Slave Address 3 16 7 TWIHS_TWIHS_THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 TWIHS_TWIHS_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 5527369 TWIHS_TWIHS_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 24 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only TWIHS1 Two-wire Interface High Speed 1 TWIHS 0x0 0x0 0x4000 registers n TWIHS1 20 CR Control Register 0x0 32 write-only n CLEAR Bus CLEAR Command 15 1 write-only HSDIS TWIHS High-Speed Mode Disabled 9 1 write-only HSEN TWIHS High-Speed Mode Enabled 8 1 write-only MSDIS TWIHS Master Mode Disabled 3 1 write-only MSEN TWIHS Master Mode Enabled 2 1 write-only PECDIS Packet Error Checking Disable 13 1 write-only PECEN Packet Error Checking Enable 12 1 write-only PECRQ PEC Request 14 1 write-only QUICK SMBus Quick Command 6 1 write-only SMBDIS SMBus Mode Disabled 11 1 write-only SMBEN SMBus Mode Enabled 10 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWIHS Slave Mode Disabled 5 1 write-only SVEN TWIHS Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time Versus TWCK Falling 24 5 read-write FILTR Filter Register 0x44 32 read-write n 0x0 FILT RX Digital Filter 0 1 read-write PADFCFG PAD Filter Config 2 1 read-write PADFEN PAD Filter Enable 1 1 read-write THRES Digital Filter Threshold 8 3 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n ARBLST Arbitration Lost Interrupt Disable 9 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only MCACK Master Code Acknowledge Interrupt Disable 16 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only PECERR PEC Error Interrupt Disable 19 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SMBDAM SMBus Default Address Match Interrupt Disable 20 1 write-only SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TOUT Timeout Error Interrupt Disable 18 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only UNRE Underrun Error Interrupt Disable 7 1 write-only IER Interrupt Enable Register 0x24 32 write-only n ARBLST Arbitration Lost Interrupt Enable 9 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only MCACK Master Code Acknowledge Interrupt Enable 16 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only PECERR PEC Error Interrupt Enable 19 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SMBDAM SMBus Default Address Match Interrupt Enable 20 1 write-only SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TOUT Timeout Error Interrupt Enable 18 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only UNRE Underrun Error Interrupt Enable 7 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only MCACK Master Code Acknowledge Interrupt Mask 16 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only PECERR PEC Error Interrupt Mask 19 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SMBDAM SMBus Default Address Match Interrupt Mask 20 1 read-only SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TOUT Timeout Error Interrupt Mask 18 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only UNRE Underrun Error Interrupt Mask 7 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 PRESC SMBus Clock Prescaler 0 4 read-write THMAX Clock High Maximum Cycles 24 8 read-write TLOWM Master Clock Stretch Maximum Cycles 16 8 read-write TLOWS Slave Clock Stretch Maximum Cycles 8 8 read-write SMR Slave Mode Register 0x8 32 read-write n 0x0 DATAMEN Data Matching Enable 31 1 read-write MASK Slave Address Mask 8 7 read-write NACKEN Slave Receiver Data Phase NACK enable 0 1 read-write SADR Slave Address 16 7 read-write SADR1EN Slave Address 1 Enable 28 1 read-write SADR2EN Slave Address 2 Enable 29 1 read-write SADR3EN Slave Address 3 Enable 30 1 read-write SCLWSDIS Clock Wait State Disable 6 1 read-write SMDA SMBus Default Address 2 1 read-write SMHH SMBus Host Header 3 1 read-write SR Status Register 0x20 32 read-only n 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 read-only EOSACC End Of Slave Access (cleared on read) 11 1 read-only GACC General Call Access (cleared on read) 5 1 read-only MCACK Master Code Acknowledge (cleared on read) 16 1 read-only NACK Not Acknowledged (cleared on read) 8 1 read-only OVRE Overrun Error (cleared on read) 6 1 read-only PECERR PEC Error (cleared on read) 19 1 read-only RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 read-only SCL SCL Line Value 24 1 read-only SCLWS Clock Wait State 10 1 read-only SDA SDA Line Value 25 1 read-only SMBDAM SMBus Default Address Match (cleared on read) 20 1 read-only SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 read-only SVACC Slave Access 4 1 read-only SVREAD Slave Read 3 1 read-only TOUT Timeout Error (cleared on read) 18 1 read-only TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 read-only TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 read-only UNRE Underrun Error (cleared on read) 7 1 read-only SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 DATAM Data Match 24 8 read-write SADR1 Slave Address 1 0 7 read-write SADR2 Slave Address 2 8 7 read-write SADR3 Slave Address 3 16 7 read-write THR Transmit Holding Register 0x34 32 write-only n 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TWIHS_TWIHS_CR Control Register 0x0 32 write-only n 0x0 0x0 ACMDIS Alternative Command Mode Disable 17 1 ACMEN Alternative Command Mode Enable 16 1 CLEAR Bus CLEAR Command 15 1 FIFODIS FIFO Disable 29 1 FIFOEN FIFO Enable 28 1 HSDIS TWIHS High-Speed Mode Disabled 9 1 HSEN TWIHS High-Speed Mode Enabled 8 1 LOCKCLR Lock Clear 26 1 MSDIS TWIHS Master Mode Disabled 3 1 MSEN TWIHS Master Mode Enabled 2 1 PECDIS Packet Error Checking Disable 13 1 PECEN Packet Error Checking Enable 12 1 PECRQ PEC Request 14 1 QUICK SMBus Quick Command 6 1 SMBDIS SMBus Mode Disabled 11 1 SMBEN SMBus Mode Enabled 10 1 START Send a START Condition 0 1 STOP Send a STOP Condition 1 1 SVDIS TWIHS Slave Mode Disabled 5 1 SVEN TWIHS Slave Mode Enabled 4 1 SWRST Software Reset 7 1 THRCLR Transmit Holding Register Clear 24 1 TWIHS_TWIHS_CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 CKDIV Clock Divider 16 3 CLDIV Clock Low Divider 0 8 HOLD TWD Hold Time Versus TWCK Falling 24 6 TWIHS_TWIHS_FILTR Filter Register 0x44 32 read-write n 0x0 0x0 FILT RX Digital Filter 0 1 PADFCFG PAD Filter Config 2 1 PADFEN PAD Filter Enable 1 1 THRES Digital Filter Threshold 8 3 TWIHS_TWIHS_IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 TWIHS_TWIHS_IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 EOSACC End Of Slave Access Interrupt Disable 11 1 GACC General Call Access Interrupt Disable 5 1 MCACK Master Code Acknowledge Interrupt Disable 16 1 NACK Not Acknowledge Interrupt Disable 8 1 OVRE Overrun Error Interrupt Disable 6 1 PECERR PEC Error Interrupt Disable 19 1 RXRDY Receive Holding Register Ready Interrupt Disable 1 1 SCL_WS Clock Wait State Interrupt Disable 10 1 SMBDAM SMBus Default Address Match Interrupt Disable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 SVACC Slave Access Interrupt Disable 4 1 TOUT Timeout Error Interrupt Disable 18 1 TXCOMP Transmission Completed Interrupt Disable 0 1 TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 UNRE Underrun Error Interrupt Disable 7 1 TWIHS_TWIHS_IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 EOSACC End Of Slave Access Interrupt Enable 11 1 GACC General Call Access Interrupt Enable 5 1 MCACK Master Code Acknowledge Interrupt Enable 16 1 NACK Not Acknowledge Interrupt Enable 8 1 OVRE Overrun Error Interrupt Enable 6 1 PECERR PEC Error Interrupt Enable 19 1 RXRDY Receive Holding Register Ready Interrupt Enable 1 1 SCL_WS Clock Wait State Interrupt Enable 10 1 SMBDAM SMBus Default Address Match Interrupt Enable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 SVACC Slave Access Interrupt Enable 4 1 TOUT Timeout Error Interrupt Enable 18 1 TXCOMP Transmission Completed Interrupt Enable 0 1 TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 UNRE Underrun Error Interrupt Enable 7 1 TWIHS_TWIHS_IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 EOSACC End Of Slave Access Interrupt Mask 11 1 GACC General Call Access Interrupt Mask 5 1 MCACK Master Code Acknowledge Interrupt Mask 16 1 NACK Not Acknowledge Interrupt Mask 8 1 OVRE Overrun Error Interrupt Mask 6 1 PECERR PEC Error Interrupt Mask 19 1 RXRDY Receive Holding Register Ready Interrupt Mask 1 1 SCL_WS Clock Wait State Interrupt Mask 10 1 SMBDAM SMBus Default Address Match Interrupt Mask 20 1 SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 SVACC Slave Access Interrupt Mask 4 1 TOUT Timeout Error Interrupt Mask 18 1 TXCOMP Transmission Completed Interrupt Mask 0 1 TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 UNRE Underrun Error Interrupt Mask 7 1 TWIHS_TWIHS_MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 IADRSZ Internal Device Address Size 8 2 IADRSZSelect NONE No internal device address 0 _1_BYTE One-byte internal device address 1 _2_BYTE Two-byte internal device address 2 _3_BYTE Three-byte internal device address 3 MREAD Master Read Direction 12 1 TWIHS_TWIHS_RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 TWIHS_TWIHS_SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 0x0 PRESC SMBus Clock Prescaler 0 4 THMAX Clock High Maximum Cycles 24 8 TLOWM Master Clock Stretch Maximum Cycles 16 8 TLOWS Slave Clock Stretch Maximum Cycles 8 8 TWIHS_TWIHS_SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 DATAMEN Data Matching Enable 31 1 MASK Slave Address Mask 8 7 NACKEN Slave Receiver Data Phase NACK enable 0 1 SADR Slave Address 16 7 SADR1EN Slave Address 1 Enable 28 1 SADR2EN Slave Address 2 Enable 29 1 SADR3EN Slave Address 3 Enable 30 1 SCLWSDIS Clock Wait State Disable 6 1 SMDA SMBus Default Address 2 1 SMHH SMBus Host Header 3 1 TWIHS_TWIHS_SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 EOSACC End Of Slave Access (cleared on read) 11 1 GACC General Call Access (cleared on read) 5 1 MCACK Master Code Acknowledge (cleared on read) 16 1 NACK Not Acknowledged (cleared on read) 8 1 OVRE Overrun Error (cleared on read) 6 1 PECERR PEC Error (cleared on read) 19 1 RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 SCL SCL Line Value 24 1 SCLWS Clock Wait State 10 1 SDA SDA Line Value 25 1 SMBDAM SMBus Default Address Match (cleared on read) 20 1 SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 SVACC Slave Access 4 1 SVREAD Slave Read 3 1 TOUT Timeout Error (cleared on read) 18 1 TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 UNRE Underrun Error (cleared on read) 7 1 TWIHS_TWIHS_SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 0x0 DATAM Data Match 24 8 SADR1 Slave Address 1 0 7 SADR2 Slave Address 2 8 7 SADR3 Slave Address 3 16 7 TWIHS_TWIHS_THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 TWIHS_TWIHS_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 5527369 TWIHS_TWIHS_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 24 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only TWIHS2 Two-wire Interface High Speed 2 TWIHS 0x0 0x0 0x4000 registers n TWIHS2 41 CR Control Register 0x0 32 write-only n CLEAR Bus CLEAR Command 15 1 write-only HSDIS TWIHS High-Speed Mode Disabled 9 1 write-only HSEN TWIHS High-Speed Mode Enabled 8 1 write-only MSDIS TWIHS Master Mode Disabled 3 1 write-only MSEN TWIHS Master Mode Enabled 2 1 write-only PECDIS Packet Error Checking Disable 13 1 write-only PECEN Packet Error Checking Enable 12 1 write-only PECRQ PEC Request 14 1 write-only QUICK SMBus Quick Command 6 1 write-only SMBDIS SMBus Mode Disabled 11 1 write-only SMBEN SMBus Mode Enabled 10 1 write-only START Send a START Condition 0 1 write-only STOP Send a STOP Condition 1 1 write-only SVDIS TWIHS Slave Mode Disabled 5 1 write-only SVEN TWIHS Slave Mode Enabled 4 1 write-only SWRST Software Reset 7 1 write-only CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 CHDIV Clock High Divider 8 8 read-write CKDIV Clock Divider 16 3 read-write CLDIV Clock Low Divider 0 8 read-write HOLD TWD Hold Time Versus TWCK Falling 24 5 read-write FILTR Filter Register 0x44 32 read-write n 0x0 FILT RX Digital Filter 0 1 read-write PADFCFG PAD Filter Config 2 1 read-write PADFEN PAD Filter Enable 1 1 read-write THRES Digital Filter Threshold 8 3 read-write IADR Internal Address Register 0xC 32 read-write n 0x0 IADR Internal Address 0 24 read-write IDR Interrupt Disable Register 0x28 32 write-only n ARBLST Arbitration Lost Interrupt Disable 9 1 write-only EOSACC End Of Slave Access Interrupt Disable 11 1 write-only GACC General Call Access Interrupt Disable 5 1 write-only MCACK Master Code Acknowledge Interrupt Disable 16 1 write-only NACK Not Acknowledge Interrupt Disable 8 1 write-only OVRE Overrun Error Interrupt Disable 6 1 write-only PECERR PEC Error Interrupt Disable 19 1 write-only RXRDY Receive Holding Register Ready Interrupt Disable 1 1 write-only SCL_WS Clock Wait State Interrupt Disable 10 1 write-only SMBDAM SMBus Default Address Match Interrupt Disable 20 1 write-only SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 write-only SVACC Slave Access Interrupt Disable 4 1 write-only TOUT Timeout Error Interrupt Disable 18 1 write-only TXCOMP Transmission Completed Interrupt Disable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 write-only UNRE Underrun Error Interrupt Disable 7 1 write-only IER Interrupt Enable Register 0x24 32 write-only n ARBLST Arbitration Lost Interrupt Enable 9 1 write-only EOSACC End Of Slave Access Interrupt Enable 11 1 write-only GACC General Call Access Interrupt Enable 5 1 write-only MCACK Master Code Acknowledge Interrupt Enable 16 1 write-only NACK Not Acknowledge Interrupt Enable 8 1 write-only OVRE Overrun Error Interrupt Enable 6 1 write-only PECERR PEC Error Interrupt Enable 19 1 write-only RXRDY Receive Holding Register Ready Interrupt Enable 1 1 write-only SCL_WS Clock Wait State Interrupt Enable 10 1 write-only SMBDAM SMBus Default Address Match Interrupt Enable 20 1 write-only SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 write-only SVACC Slave Access Interrupt Enable 4 1 write-only TOUT Timeout Error Interrupt Enable 18 1 write-only TXCOMP Transmission Completed Interrupt Enable 0 1 write-only TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 write-only UNRE Underrun Error Interrupt Enable 7 1 write-only IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 read-only EOSACC End Of Slave Access Interrupt Mask 11 1 read-only GACC General Call Access Interrupt Mask 5 1 read-only MCACK Master Code Acknowledge Interrupt Mask 16 1 read-only NACK Not Acknowledge Interrupt Mask 8 1 read-only OVRE Overrun Error Interrupt Mask 6 1 read-only PECERR PEC Error Interrupt Mask 19 1 read-only RXRDY Receive Holding Register Ready Interrupt Mask 1 1 read-only SCL_WS Clock Wait State Interrupt Mask 10 1 read-only SMBDAM SMBus Default Address Match Interrupt Mask 20 1 read-only SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 read-only SVACC Slave Access Interrupt Mask 4 1 read-only TOUT Timeout Error Interrupt Mask 18 1 read-only TXCOMP Transmission Completed Interrupt Mask 0 1 read-only TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 read-only UNRE Underrun Error Interrupt Mask 7 1 read-only MMR Master Mode Register 0x4 32 read-write n 0x0 DADR Device Address 16 7 read-write IADRSZ Internal Device Address Size 8 2 read-write NONE No internal device address 0x0 1_BYTE One-byte internal device address 0x1 2_BYTE Two-byte internal device address 0x2 3_BYTE Three-byte internal device address 0x3 MREAD Master Read Direction 12 1 read-write RHR Receive Holding Register 0x30 32 read-only n 0x0 RXDATA Master or Slave Receive Holding Data 0 8 read-only SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 PRESC SMBus Clock Prescaler 0 4 read-write THMAX Clock High Maximum Cycles 24 8 read-write TLOWM Master Clock Stretch Maximum Cycles 16 8 read-write TLOWS Slave Clock Stretch Maximum Cycles 8 8 read-write SMR Slave Mode Register 0x8 32 read-write n 0x0 DATAMEN Data Matching Enable 31 1 read-write MASK Slave Address Mask 8 7 read-write NACKEN Slave Receiver Data Phase NACK enable 0 1 read-write SADR Slave Address 16 7 read-write SADR1EN Slave Address 1 Enable 28 1 read-write SADR2EN Slave Address 2 Enable 29 1 read-write SADR3EN Slave Address 3 Enable 30 1 read-write SCLWSDIS Clock Wait State Disable 6 1 read-write SMDA SMBus Default Address 2 1 read-write SMHH SMBus Host Header 3 1 read-write SR Status Register 0x20 32 read-only n 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 read-only EOSACC End Of Slave Access (cleared on read) 11 1 read-only GACC General Call Access (cleared on read) 5 1 read-only MCACK Master Code Acknowledge (cleared on read) 16 1 read-only NACK Not Acknowledged (cleared on read) 8 1 read-only OVRE Overrun Error (cleared on read) 6 1 read-only PECERR PEC Error (cleared on read) 19 1 read-only RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 read-only SCL SCL Line Value 24 1 read-only SCLWS Clock Wait State 10 1 read-only SDA SDA Line Value 25 1 read-only SMBDAM SMBus Default Address Match (cleared on read) 20 1 read-only SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 read-only SVACC Slave Access 4 1 read-only SVREAD Slave Read 3 1 read-only TOUT Timeout Error (cleared on read) 18 1 read-only TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 read-only TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 read-only UNRE Underrun Error (cleared on read) 7 1 read-only SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 DATAM Data Match 24 8 read-write SADR1 Slave Address 1 0 7 read-write SADR2 Slave Address 2 8 7 read-write SADR3 Slave Address 3 16 7 read-write THR Transmit Holding Register 0x34 32 write-only n 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 write-only TWIHS_TWIHS_CR Control Register 0x0 32 write-only n 0x0 0x0 ACMDIS Alternative Command Mode Disable 17 1 ACMEN Alternative Command Mode Enable 16 1 CLEAR Bus CLEAR Command 15 1 FIFODIS FIFO Disable 29 1 FIFOEN FIFO Enable 28 1 HSDIS TWIHS High-Speed Mode Disabled 9 1 HSEN TWIHS High-Speed Mode Enabled 8 1 LOCKCLR Lock Clear 26 1 MSDIS TWIHS Master Mode Disabled 3 1 MSEN TWIHS Master Mode Enabled 2 1 PECDIS Packet Error Checking Disable 13 1 PECEN Packet Error Checking Enable 12 1 PECRQ PEC Request 14 1 QUICK SMBus Quick Command 6 1 SMBDIS SMBus Mode Disabled 11 1 SMBEN SMBus Mode Enabled 10 1 START Send a START Condition 0 1 STOP Send a STOP Condition 1 1 SVDIS TWIHS Slave Mode Disabled 5 1 SVEN TWIHS Slave Mode Enabled 4 1 SWRST Software Reset 7 1 THRCLR Transmit Holding Register Clear 24 1 TWIHS_TWIHS_CWGR Clock Waveform Generator Register 0x10 32 read-write n 0x0 0x0 CHDIV Clock High Divider 8 8 CKDIV Clock Divider 16 3 CLDIV Clock Low Divider 0 8 HOLD TWD Hold Time Versus TWCK Falling 24 6 TWIHS_TWIHS_FILTR Filter Register 0x44 32 read-write n 0x0 0x0 FILT RX Digital Filter 0 1 PADFCFG PAD Filter Config 2 1 PADFEN PAD Filter Enable 1 1 THRES Digital Filter Threshold 8 3 TWIHS_TWIHS_IADR Internal Address Register 0xC 32 read-write n 0x0 0x0 IADR Internal Address 0 24 TWIHS_TWIHS_IDR Interrupt Disable Register 0x28 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Disable 9 1 EOSACC End Of Slave Access Interrupt Disable 11 1 GACC General Call Access Interrupt Disable 5 1 MCACK Master Code Acknowledge Interrupt Disable 16 1 NACK Not Acknowledge Interrupt Disable 8 1 OVRE Overrun Error Interrupt Disable 6 1 PECERR PEC Error Interrupt Disable 19 1 RXRDY Receive Holding Register Ready Interrupt Disable 1 1 SCL_WS Clock Wait State Interrupt Disable 10 1 SMBDAM SMBus Default Address Match Interrupt Disable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Disable 21 1 SVACC Slave Access Interrupt Disable 4 1 TOUT Timeout Error Interrupt Disable 18 1 TXCOMP Transmission Completed Interrupt Disable 0 1 TXRDY Transmit Holding Register Ready Interrupt Disable 2 1 UNRE Underrun Error Interrupt Disable 7 1 TWIHS_TWIHS_IER Interrupt Enable Register 0x24 32 write-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Enable 9 1 EOSACC End Of Slave Access Interrupt Enable 11 1 GACC General Call Access Interrupt Enable 5 1 MCACK Master Code Acknowledge Interrupt Enable 16 1 NACK Not Acknowledge Interrupt Enable 8 1 OVRE Overrun Error Interrupt Enable 6 1 PECERR PEC Error Interrupt Enable 19 1 RXRDY Receive Holding Register Ready Interrupt Enable 1 1 SCL_WS Clock Wait State Interrupt Enable 10 1 SMBDAM SMBus Default Address Match Interrupt Enable 20 1 SMBHHM SMBus Host Header Address Match Interrupt Enable 21 1 SVACC Slave Access Interrupt Enable 4 1 TOUT Timeout Error Interrupt Enable 18 1 TXCOMP Transmission Completed Interrupt Enable 0 1 TXRDY Transmit Holding Register Ready Interrupt Enable 2 1 UNRE Underrun Error Interrupt Enable 7 1 TWIHS_TWIHS_IMR Interrupt Mask Register 0x2C 32 read-only n 0x0 0x0 ARBLST Arbitration Lost Interrupt Mask 9 1 EOSACC End Of Slave Access Interrupt Mask 11 1 GACC General Call Access Interrupt Mask 5 1 MCACK Master Code Acknowledge Interrupt Mask 16 1 NACK Not Acknowledge Interrupt Mask 8 1 OVRE Overrun Error Interrupt Mask 6 1 PECERR PEC Error Interrupt Mask 19 1 RXRDY Receive Holding Register Ready Interrupt Mask 1 1 SCL_WS Clock Wait State Interrupt Mask 10 1 SMBDAM SMBus Default Address Match Interrupt Mask 20 1 SMBHHM SMBus Host Header Address Match Interrupt Mask 21 1 SVACC Slave Access Interrupt Mask 4 1 TOUT Timeout Error Interrupt Mask 18 1 TXCOMP Transmission Completed Interrupt Mask 0 1 TXRDY Transmit Holding Register Ready Interrupt Mask 2 1 UNRE Underrun Error Interrupt Mask 7 1 TWIHS_TWIHS_MMR Master Mode Register 0x4 32 read-write n 0x0 0x0 DADR Device Address 16 7 IADRSZ Internal Device Address Size 8 2 IADRSZSelect NONE No internal device address 0 _1_BYTE One-byte internal device address 1 _2_BYTE Two-byte internal device address 2 _3_BYTE Three-byte internal device address 3 MREAD Master Read Direction 12 1 TWIHS_TWIHS_RHR Receive Holding Register 0x30 32 read-only n 0x0 0x0 RXDATA Master or Slave Receive Holding Data 0 8 TWIHS_TWIHS_SMBTR SMBus Timing Register 0x38 32 read-write n 0x0 0x0 PRESC SMBus Clock Prescaler 0 4 THMAX Clock High Maximum Cycles 24 8 TLOWM Master Clock Stretch Maximum Cycles 16 8 TLOWS Slave Clock Stretch Maximum Cycles 8 8 TWIHS_TWIHS_SMR Slave Mode Register 0x8 32 read-write n 0x0 0x0 DATAMEN Data Matching Enable 31 1 MASK Slave Address Mask 8 7 NACKEN Slave Receiver Data Phase NACK enable 0 1 SADR Slave Address 16 7 SADR1EN Slave Address 1 Enable 28 1 SADR2EN Slave Address 2 Enable 29 1 SADR3EN Slave Address 3 Enable 30 1 SCLWSDIS Clock Wait State Disable 6 1 SMDA SMBus Default Address 2 1 SMHH SMBus Host Header 3 1 TWIHS_TWIHS_SR Status Register 0x20 32 read-only n 0x0 0x0 ARBLST Arbitration Lost (cleared on read) 9 1 EOSACC End Of Slave Access (cleared on read) 11 1 GACC General Call Access (cleared on read) 5 1 MCACK Master Code Acknowledge (cleared on read) 16 1 NACK Not Acknowledged (cleared on read) 8 1 OVRE Overrun Error (cleared on read) 6 1 PECERR PEC Error (cleared on read) 19 1 RXRDY Receive Holding Register Ready (cleared by reading TWIHS_RHR) 1 1 SCL SCL Line Value 24 1 SCLWS Clock Wait State 10 1 SDA SDA Line Value 25 1 SMBDAM SMBus Default Address Match (cleared on read) 20 1 SMBHHM SMBus Host Header Address Match (cleared on read) 21 1 SVACC Slave Access 4 1 SVREAD Slave Read 3 1 TOUT Timeout Error (cleared on read) 18 1 TXCOMP Transmission Completed (cleared by writing TWIHS_THR) 0 1 TXRDY Transmit Holding Register Ready (cleared by writing TWIHS_THR) 2 1 UNRE Underrun Error (cleared on read) 7 1 TWIHS_TWIHS_SWMR SleepWalking Matching Register 0x4C 32 read-write n 0x0 0x0 DATAM Data Match 24 8 SADR1 Slave Address 1 0 7 SADR2 Slave Address 2 8 7 SADR3 Slave Address 3 16 7 TWIHS_TWIHS_THR Transmit Holding Register 0x34 32 write-only n 0x0 0x0 TXDATA Master or Slave Transmit Holding Data 0 8 TWIHS_TWIHS_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 5527369 TWIHS_TWIHS_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 24 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit.Always reads as 0 0x545749 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 24 read-only UART0 Universal Asynchronous Receiver Transmitter 0 UART 0x0 0x0 0xE8 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n UART0 7 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 CD Clock Divisor 0 16 read-write CMPR Comparison Register 0x24 32 read-write n 0x0 CMPMODE Comparison Mode 12 1 read-write FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 read-write VAL1 First Comparison Value for Received Character 0 8 read-write VAL2 Second Comparison Value for Received Character 16 8 read-write CR Control Register 0x0 32 write-only n REQCLR Request Clear 12 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n CMP Disable Comparison Interrupt 15 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n CMP Enable Comparison Interrupt 15 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 CMP Mask Comparison Interrupt 15 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 BRSRCCK Baud Rate Source Clock 12 1 read-write PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 read-write DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 RXCHR Received Character 0 8 read-only SR Status Register 0x14 32 read-only n CMP Comparison Match 15 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXRDY Receiver Ready 0 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only THR Transmit Holding Register 0x1C 32 write-only n TXCHR Character to be Transmitted 0 8 write-only UART_UART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 UART_UART_CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 UART_UART_CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 UART_UART_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 UART_UART_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0 AUTOMATIC Automatic echo 1 LOCAL_LOOPBACK Local loopback 2 REMOTE_LOOPBACK Remote loopback 3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0 ODD Odd Parity 1 SPACE Space: parity forced to 0 2 MARK Mark: parity forced to 1 3 NO No parity 4 UART_UART_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 UART_UART_SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 UART_UART_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_UART_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 5587282 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 UART1 Universal Asynchronous Receiver Transmitter 1 UART 0x0 0x0 0xE8 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n UART1 8 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 CD Clock Divisor 0 16 read-write CMPR Comparison Register 0x24 32 read-write n 0x0 CMPMODE Comparison Mode 12 1 read-write FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 read-write VAL1 First Comparison Value for Received Character 0 8 read-write VAL2 Second Comparison Value for Received Character 16 8 read-write CR Control Register 0x0 32 write-only n REQCLR Request Clear 12 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n CMP Disable Comparison Interrupt 15 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n CMP Enable Comparison Interrupt 15 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 CMP Mask Comparison Interrupt 15 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 BRSRCCK Baud Rate Source Clock 12 1 read-write PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 read-write DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 RXCHR Received Character 0 8 read-only SR Status Register 0x14 32 read-only n CMP Comparison Match 15 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXRDY Receiver Ready 0 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only THR Transmit Holding Register 0x1C 32 write-only n TXCHR Character to be Transmitted 0 8 write-only UART_UART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 UART_UART_CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 UART_UART_CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 UART_UART_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 UART_UART_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0 AUTOMATIC Automatic echo 1 LOCAL_LOOPBACK Local loopback 2 REMOTE_LOOPBACK Remote loopback 3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0 ODD Odd Parity 1 SPACE Space: parity forced to 0 2 MARK Mark: parity forced to 1 3 NO No parity 4 UART_UART_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 UART_UART_SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 UART_UART_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_UART_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 5587282 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 UART2 Universal Asynchronous Receiver Transmitter UART 0x0 0x0 0xE8 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n UART2 44 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 CD Clock Divisor 0 16 read-write CMPR Comparison Register 0x24 32 read-write n 0x0 CMPMODE Comparison Mode 12 1 read-write FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 read-write VAL1 First Comparison Value for Received Character 0 8 read-write VAL2 Second Comparison Value for Received Character 16 8 read-write CR Control Register 0x0 32 write-only n REQCLR Request Clear 12 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n CMP Disable Comparison Interrupt 15 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n CMP Enable Comparison Interrupt 15 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 CMP Mask Comparison Interrupt 15 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 BRSRCCK Baud Rate Source Clock 12 1 read-write PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 read-write DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 RXCHR Received Character 0 8 read-only SR Status Register 0x14 32 read-only n CMP Comparison Match 15 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXRDY Receiver Ready 0 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only THR Transmit Holding Register 0x1C 32 write-only n TXCHR Character to be Transmitted 0 8 write-only UART_UART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 UART_UART_CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 UART_UART_CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 UART_UART_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 UART_UART_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0 AUTOMATIC Automatic echo 1 LOCAL_LOOPBACK Local loopback 2 REMOTE_LOOPBACK Remote loopback 3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0 ODD Odd Parity 1 SPACE Space: parity forced to 0 2 MARK Mark: parity forced to 1 3 NO No parity 4 UART_UART_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 UART_UART_SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 UART_UART_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_UART_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 5587282 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 UART3 Universal Asynchronous Receiver Transmitter UART 0x0 0x0 0xE8 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n UART3 45 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 CD Clock Divisor 0 16 read-write CMPR Comparison Register 0x24 32 read-write n 0x0 CMPMODE Comparison Mode 12 1 read-write FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 read-write VAL1 First Comparison Value for Received Character 0 8 read-write VAL2 Second Comparison Value for Received Character 16 8 read-write CR Control Register 0x0 32 write-only n REQCLR Request Clear 12 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n CMP Disable Comparison Interrupt 15 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n CMP Enable Comparison Interrupt 15 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 CMP Mask Comparison Interrupt 15 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 BRSRCCK Baud Rate Source Clock 12 1 read-write PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 read-write DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 RXCHR Received Character 0 8 read-only SR Status Register 0x14 32 read-only n CMP Comparison Match 15 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXRDY Receiver Ready 0 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only THR Transmit Holding Register 0x1C 32 write-only n TXCHR Character to be Transmitted 0 8 write-only UART_UART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 UART_UART_CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 UART_UART_CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 UART_UART_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 UART_UART_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0 AUTOMATIC Automatic echo 1 LOCAL_LOOPBACK Local loopback 2 REMOTE_LOOPBACK Remote loopback 3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0 ODD Odd Parity 1 SPACE Space: parity forced to 0 2 MARK Mark: parity forced to 1 3 NO No parity 4 UART_UART_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 UART_UART_SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 UART_UART_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_UART_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 5587282 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 UART4 Universal Asynchronous Receiver Transmitter UART 0x0 0x0 0xE8 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n 0x0 0x200 registers n UART4 46 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 CD Clock Divisor 0 16 read-write CMPR Comparison Register 0x24 32 read-write n 0x0 CMPMODE Comparison Mode 12 1 read-write FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 read-write VAL1 First Comparison Value for Received Character 0 8 read-write VAL2 Second Comparison Value for Received Character 16 8 read-write CR Control Register 0x0 32 write-only n REQCLR Request Clear 12 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only IDR Interrupt Disable Register 0xC 32 write-only n CMP Disable Comparison Interrupt 15 1 write-only FRAME Disable Framing Error Interrupt 6 1 write-only OVRE Disable Overrun Error Interrupt 5 1 write-only PARE Disable Parity Error Interrupt 7 1 write-only RXRDY Disable RXRDY Interrupt 0 1 write-only TXEMPTY Disable TXEMPTY Interrupt 9 1 write-only TXRDY Disable TXRDY Interrupt 1 1 write-only IER Interrupt Enable Register 0x8 32 write-only n CMP Enable Comparison Interrupt 15 1 write-only FRAME Enable Framing Error Interrupt 6 1 write-only OVRE Enable Overrun Error Interrupt 5 1 write-only PARE Enable Parity Error Interrupt 7 1 write-only RXRDY Enable RXRDY Interrupt 0 1 write-only TXEMPTY Enable TXEMPTY Interrupt 9 1 write-only TXRDY Enable TXRDY Interrupt 1 1 write-only IMR Interrupt Mask Register 0x10 32 read-only n 0x0 CMP Mask Comparison Interrupt 15 1 read-only FRAME Mask Framing Error Interrupt 6 1 read-only OVRE Mask Overrun Error Interrupt 5 1 read-only PARE Mask Parity Error Interrupt 7 1 read-only RXRDY Mask RXRDY Interrupt 0 1 read-only TXEMPTY Mask TXEMPTY Interrupt 9 1 read-only TXRDY Disable TXRDY Interrupt 1 1 read-only MR Mode Register 0x4 32 read-write n 0x0 BRSRCCK Baud Rate Source Clock 12 1 read-write PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic echo 0x1 LOCAL_LOOPBACK Local loopback 0x2 REMOTE_LOOPBACK Remote loopback 0x3 FILTER Receiver Digital Filter 4 1 read-write DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 read-write EVEN Even Parity 0x0 ODD Odd Parity 0x1 SPACE Space: parity forced to 0 0x2 MARK Mark: parity forced to 1 0x3 NO No parity 0x4 RHR Receive Holding Register 0x18 32 read-only n 0x0 RXCHR Received Character 0 8 read-only SR Status Register 0x14 32 read-only n CMP Comparison Match 15 1 read-only FRAME Framing Error 6 1 read-only OVRE Overrun Error 5 1 read-only PARE Parity Error 7 1 read-only RXRDY Receiver Ready 0 1 read-only TXEMPTY Transmitter Empty 9 1 read-only TXRDY Transmitter Ready 1 1 read-only THR Transmit Holding Register 0x1C 32 write-only n TXCHR Character to be Transmitted 0 8 write-only UART_UART_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divisor 0 16 UART_UART_CMPR Comparison Register 0x24 32 read-write n 0x0 0x0 CMPMODE Comparison Mode 12 1 CMPMODESelect FLAG_ONLY Any character is received and comparison function drives CMP flag. 0 START_CONDITION Comparison condition must be met to start reception. 1 CMPPAR Compare Parity 14 1 VAL1 First Comparison Value for Received Character 0 8 VAL2 Second Comparison Value for Received Character 16 8 UART_UART_CR Control Register 0x0 32 write-only n 0x0 0x0 REQCLR Request Clear 12 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status 8 1 RSTTX Reset Transmitter 3 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 UART_UART_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CMP Disable Comparison Interrupt 15 1 FRAME Disable Framing Error Interrupt 6 1 OVRE Disable Overrun Error Interrupt 5 1 PARE Disable Parity Error Interrupt 7 1 RXRDY Disable RXRDY Interrupt 0 1 TXEMPTY Disable TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CMP Enable Comparison Interrupt 15 1 FRAME Enable Framing Error Interrupt 6 1 OVRE Enable Overrun Error Interrupt 5 1 PARE Enable Parity Error Interrupt 7 1 RXRDY Enable RXRDY Interrupt 0 1 TXEMPTY Enable TXEMPTY Interrupt 9 1 TXRDY Enable TXRDY Interrupt 1 1 UART_UART_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CMP Mask Comparison Interrupt 15 1 FRAME Mask Framing Error Interrupt 6 1 OVRE Mask Overrun Error Interrupt 5 1 PARE Mask Parity Error Interrupt 7 1 RXRDY Mask RXRDY Interrupt 0 1 TXEMPTY Mask TXEMPTY Interrupt 9 1 TXRDY Disable TXRDY Interrupt 1 1 UART_UART_MR Mode Register 0x4 32 read-write n 0x0 0x0 BRSRCCK Baud Rate Source Clock 12 1 BRSRCCKSelect PERIPH_CLK The baud rate is driven by the peripheral clock 0 PMC_PCK The baud rate is driven by a PMC programmable clock PCK (see section Power Management Controller (PMC)). 1 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0 AUTOMATIC Automatic echo 1 LOCAL_LOOPBACK Local loopback 2 REMOTE_LOOPBACK Remote loopback 3 FILTER Receiver Digital Filter 4 1 FILTERSelect DISABLED UART does not filter the receive line. 0 ENABLED UART filters the receive line using a three-sample filter (16x-bit clock) (2 over 3 majority). 1 PAR Parity Type 9 3 PARSelect EVEN Even Parity 0 ODD Odd Parity 1 SPACE Space: parity forced to 0 2 MARK Mark: parity forced to 1 3 NO No parity 4 UART_UART_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 8 UART_UART_SR Status Register 0x14 32 read-only n 0x0 0x0 CMP Comparison Match 15 1 FRAME Framing Error 6 1 OVRE Overrun Error 5 1 PARE Parity Error 7 1 RXRDY Receiver Ready 0 1 TXEMPTY Transmitter Empty 9 1 TXRDY Transmitter Ready 1 1 UART_UART_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 8 UART_UART_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 5587282 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation.Always reads as 0. 0x554152 USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 USART 0x0 0x0 0x4000 registers n USART0 13 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n DTRDIS Data Terminal Ready Disable 17 1 write-only DTREN Data Terminal Ready Enable 16 1 write-only LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only RETTO Start Time-out Immediately 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Pin Control 19 1 write-only RTSEN Request to Send Pin Control 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Clear TIMEOUT Flag and Start Time-out After Next Character Received 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register 0x0 32 write-only n FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 read-only DCD Image of DCD Input 22 1 read-only DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 read-only DSR Image of DSR Input 21 1 read-only DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 read-only FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 read-only MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 read-only NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RI Image of RI Input 20 1 read-only RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 read-only RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_LIN_MODE Channel Status Register 0x14 32 read-only n 0x0 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only LINBE LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) 25 1 read-only LINBK LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) 13 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINCE LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) 28 1 read-only LINHTE LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) 31 1 read-only LINID LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) 14 1 read-only LINIPE LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 27 1 read-only LINISFE LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) 26 1 read-only LINSNRE LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) 29 1 read-only LINSTE LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) 30 1 read-only LINTC LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) 15 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RXRDY Receiver Ready (cleared by reading US_THR) 0 1 read-only TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.RSTSTA) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_LON_MODE Channel Status Register 0x14 32 read-only n 0x0 LBLOVFE LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) 28 1 read-only LCOL LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) 25 1 read-only LCRCE LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only LFET LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) 26 1 read-only LRXD LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) 27 1 read-only LSFE LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only LTXD LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) 24 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only CSR_SPI_MODE Channel Status Register 0x14 32 read-only n 0x0 NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 23 1 read-only NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 19 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 16 read-write FIDI_LON_MODE FI DI Ratio Register 0x40 32 read-write n 0x0 BETA2 LON BETA2 Length 0 24 read-write ICDIFF IC DIFF Register 0x88 32 read-write n 0x0 ICDIFF IC Differentiator Number 0 4 read-write IDR Interrupt Disable Register 0xC 32 write-only n CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 write-only DSRIC Data Set Ready Input Change Disable 17 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RIIC Ring Indicator Input Change Disable 16 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LIN_MODE Interrupt Disable Register 0xC 32 write-only n FRAME Framing Error Interrupt Disable 6 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINHTE LIN Header Timeout Error Interrupt Disable 31 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LON_MODE Interrupt Disable Register 0xC 32 write-only n LBLOVFE LON Backlog Overflow Error Interrupt Disable 28 1 write-only LCOL LON Collision Interrupt Disable 25 1 write-only LCRCE LON CRC Error Interrupt Disable 7 1 write-only LFET LON Frame Early Termination Interrupt Disable 26 1 write-only LRXD LON Reception Done Interrupt Disable 27 1 write-only LSFE LON Short Frame Error Interrupt Disable 6 1 write-only LTXD LON Transmission Done Interrupt Disable 24 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE Underrun Error Interrupt Disable 10 1 write-only IDR_SPI_MODE Interrupt Disable Register 0xC 32 write-only n NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable 19 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IDTRX LON IDT Rx Register 0x84 32 read-write n 0x0 IDTRX LON Indeterminate Time after Reception (comm_type = 1 mode only) 0 24 read-write IDTTX LON IDT Tx Register 0x80 32 read-write n 0x0 IDTTX LON Indeterminate Time after Transmission (comm_type = 1 mode only) 0 24 read-write IER Interrupt Enable Register 0x8 32 write-only n CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 write-only DSRIC Data Set Ready Input Change Enable 17 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RIIC Ring Indicator Input Change Enable 16 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LIN_MODE Interrupt Enable Register 0x8 32 write-only n FRAME Framing Error Interrupt Enable 6 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINHTE LIN Header Timeout Error Interrupt Enable 31 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LON_MODE Interrupt Enable Register 0x8 32 write-only n LBLOVFE LON Backlog Overflow Error Interrupt Enable 28 1 write-only LCOL LON Collision Interrupt Enable 25 1 write-only LCRCE LON CRC Error Interrupt Enable 7 1 write-only LFET LON Frame Early Termination Interrupt Enable 26 1 write-only LRXD LON Reception Done Interrupt Enable 27 1 write-only LSFE LON Short Frame Error Interrupt Enable 6 1 write-only LTXD LON Transmission Done Interrupt Enable 24 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE Underrun Error Interrupt Enable 10 1 write-only IER_SPI_MODE Interrupt Enable Register 0x8 32 write-only n NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable 19 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 read-only DSRIC Data Set Ready Input Change Mask 17 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RIIC Ring Indicator Input Change Mask 16 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LIN_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 FRAME Framing Error Interrupt Mask 6 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINHTE LIN Header Timeout Error Interrupt Mask 31 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LON_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 LBLOVFE LON Backlog Overflow Error Interrupt Mask 28 1 read-only LCOL LON Collision Interrupt Mask 25 1 read-only LCRCE LON CRC Error Interrupt Mask 7 1 read-only LFET LON Frame Early Termination Interrupt Mask 26 1 read-only LRXD LON Reception Done Interrupt Mask 27 1 read-only LSFE LON Short Frame Error Interrupt Mask 6 1 read-only LTXD LON Transmission Done Interrupt Mask 24 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE Underrun Error Interrupt Mask 10 1 read-only IMR_SPI_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask 19 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only LINIR LIN Identifier Register 0x58 32 read-write n 0x0 IDCHR Identifier Character 0 8 read-write LINMR LIN Mode Register 0x54 32 read-write n 0x0 CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLC Data Length Control 8 8 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write PDCM DMAC Mode 16 1 read-write SYNCDIS Synchronization Disable 17 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write LONB1RX LON Beta1 Rx Register 0x78 32 read-write n 0x0 BETA1RX LON Beta1 Length after Reception 0 24 read-write LONB1TX LON Beta1 Tx Register 0x74 32 read-write n 0x0 BETA1TX LON Beta1 Length after Transmission 0 24 read-write LONBL LON Backlog Register 0x70 32 read-only n 0x0 LONBL LON Node Backlog Value 0 6 read-only LONDL LON Data Length Register 0x68 32 read-write n 0x0 LONDL LON Data Length 0 8 read-write LONL2HDR LON L2HDR Register 0x6C 32 read-write n 0x0 ALTP LON Alternate Path Bit 6 1 read-write BLI LON Backlog Increment 0 6 read-write PB LON Priority Bit 7 1 read-write LONMR LON Mode Register 0x60 32 read-write n 0x0 CDTAIL LON Collision Detection on Frame Tail 3 1 read-write COLDET LON Collision Detection Feature 1 1 read-write COMMT LON comm_type Parameter Value 0 1 read-write DMAM LON DMA Mode 4 1 read-write EOFS End of Frame Condition Size 16 8 read-write LCDS LON Collision Detection Source 5 1 read-write TCOL Terminate Frame upon Collision Notification 2 1 read-write LONPR LON Preamble Register 0x64 32 read-write n 0x0 LONPL LON Preamble Length 0 14 read-write LONPRIO LON Priority Register 0x7C 32 read-write n 0x0 NPS LON Node Priority Slot 8 7 read-write PSNB LON Priority Slot Number 0 7 read-write MAN Manchester Configuration Register 0x50 32 read-write n 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RXIDLEV 31 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 MODEM Modem 0x3 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LON LON 0x9 SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=DIV=8) is selected 0x1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 0x2 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register 0x4 32 read-write n 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 NB_ERRORS Number of Errors 0 8 read-only RHR Receive Holding Register 0x18 32 read-only n 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 TO Time-out Value 0 17 read-write THR Transmit Holding Register 0x1C 32 write-only n TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 TG Timeguard Value 0 8 read-write TTGR_LON_MODE Transmitter Timeguard Register 0x28 32 read-write n 0x0 PCYCLE LON PCYCLE Length 0 24 read-write USART_US_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 FP Fractional Part 16 3 USART_US_CR Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTREN Data Terminal Ready Enable 16 1 LINABT Abort LIN Transmission 20 1 LINWKUP Send LIN Wakeup Signal 21 1 RETTO Start Time-out Immediately 15 1 RSTIT Reset Iterations 13 1 RSTNACK Reset Non Acknowledge 14 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RTSDIS Request to Send Pin Control 19 1 RTSEN Request to Send Pin Control 18 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 SENDA Send Address 12 1 STPBRK Stop Break 10 1 STTBRK Start Break 9 1 STTTO Clear TIMEOUT Flag and Start Time-out After Next Character Received 11 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 USART_US_CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 DCD Image of DCD Input 22 1 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSR Image of DSR Input 21 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RI Image of RI Input 20 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 USART_US_FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 16 USART_US_ICDIFF IC DIFF Register 0x88 32 read-write n 0x0 0x0 ICDIFF IC Differentiator Number 0 4 USART_US_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 ITER Max Number of Repetitions Reached Interrupt Disable 10 1 MANE Manchester Error Interrupt Disable 24 1 NACK Non Acknowledge Interrupt Disable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXBRK Receiver Break Interrupt Disable 2 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Time-out Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 USART_US_IDTRX LON IDT Rx Register 0x84 32 read-write n 0x0 0x0 IDTRX LON Indeterminate Time after Reception (comm_type = 1 mode only) 0 24 USART_US_IDTTX LON IDT Tx Register 0x80 32 read-write n 0x0 0x0 IDTTX LON Indeterminate Time after Transmission (comm_type = 1 mode only) 0 24 USART_US_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DSRIC Data Set Ready Input Change Enable 17 1 FRAME Framing Error Interrupt Enable 6 1 ITER Max number of Repetitions Reached Interrupt Enable 10 1 MANE Manchester Error Interrupt Enable 24 1 NACK Non Acknowledge Interrupt Enable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RIIC Ring Indicator Input Change Enable 16 1 RXBRK Receiver Break Interrupt Enable 2 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Time-out Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 USART_US_IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 USART_US_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 ITER Max Number of Repetitions Reached Interrupt Mask 10 1 MANE Manchester Error Interrupt Mask 24 1 NACK Non Acknowledge Interrupt Mask 13 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXBRK Receiver Break Interrupt Mask 2 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Time-out Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 USART_US_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 USART_US_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 USART_US_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The USART transmits the response. 0 SUBSCRIBE The USART receives the response. 1 IGNORE The USART does not transmit and does not receive the response. 2 PARDIS Parity Disable 2 1 PDCM DMAC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 USART_US_LONB1RX LON Beta1 Rx Register 0x78 32 read-write n 0x0 0x0 BETA1RX LON Beta1 Length after Reception 0 24 USART_US_LONB1TX LON Beta1 Tx Register 0x74 32 read-write n 0x0 0x0 BETA1TX LON Beta1 Length after Transmission 0 24 USART_US_LONBL LON Backlog Register 0x70 32 read-only n 0x0 0x0 LONBL LON Node Backlog Value 0 6 USART_US_LONDL LON Data Length Register 0x68 32 read-write n 0x0 0x0 LONDL LON Data Length 0 8 USART_US_LONL2HDR LON L2HDR Register 0x6C 32 read-write n 0x0 0x0 ALTP LON Alternate Path Bit 6 1 BLI LON Backlog Increment 0 6 PB LON Priority Bit 7 1 USART_US_LONMR LON Mode Register 0x60 32 read-write n 0x0 0x0 CDTAIL LON Collision Detection on Frame Tail 3 1 COLDET LON Collision Detection Feature 1 1 COMMT LON comm_type Parameter Value 0 1 DMAM LON DMA Mode 4 1 EOFS End of Frame Condition Size 16 8 LCDS LON Collision Detection Source 5 1 TCOL Terminate Frame upon Collision Notification 2 1 USART_US_LONPR LON Preamble Register 0x64 32 read-write n 0x0 0x0 LONPL LON Preamble Length 0 14 USART_US_LONPRIO LON Priority Register 0x7C 32 read-write n 0x0 0x0 NPS LON Node Priority Slot 8 7 PSNB LON Priority Slot Number 0 7 USART_US_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 ONE Must Be Set to 1 29 1 RXIDLEV 31 1 RX_MPOL Receiver Manchester Polarity 28 1 RX_PL Receiver Preamble Length 16 4 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect ALL_ONE The preamble is composed of '1's 0 ALL_ZERO The preamble is composed of '0's 1 ZERO_ONE The preamble is composed of '01's 2 ONE_ZERO The preamble is composed of '10's 3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_PL Transmitter Preamble Length 0 4 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect ALL_ONE The preamble is composed of '1's 0 ALL_ZERO The preamble is composed of '0's 1 ZERO_ONE The preamble is composed of '01's 2 ONE_ZERO The preamble is composed of '10's 3 USART_US_MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 3 CHRL Character Length 6 2 CHRLSelect _5_BIT Character length is 5 bits 0 _6_BIT Character length is 6 bits 1 _7_BIT Character length is 7 bits 2 _8_BIT Character length is 8 bits 3 CLKO Clock Output Select 18 1 DSNACK Disable Successive NACK 21 1 FILTER Receive Line Filter 28 1 INACK Inhibit Non Acknowledge 20 1 INVDATA Inverted Data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MAX_ITERATION Maximum Number of Automatic Iteration 24 3 MODE9 9-bit Character Length 17 1 MODSYNC Manchester Synchronization Mode 30 1 MSBF Bit Order 16 1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect _1_BIT 1 stop bit 0 _1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 1 _2_BIT 2 stop bits 2 ONEBIT Start Frame Delimiter Selector 31 1 OVER Oversampling Mode 19 1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0 ODD Odd parity 1 SPACE Parity forced to 0 (Space) 2 MARK Parity forced to 1 (Mark) 3 NO No parity 4 MULTIDROP Multidrop mode 6 SYNC Synchronous Mode Select 8 1 USART_MODE USART Mode of Operation 0 4 USART_MODESelect NORMAL Normal mode 0 RS485 RS485 1 SPI_MASTER SPI master 14 SPI_SLAVE SPI Slave 15 HW_HANDSHAKING Hardware Handshaking 2 MODEM Modem 3 IS07816_T_0 IS07816 Protocol: T = 0 4 IS07816_T_1 IS07816 Protocol: T = 1 6 IRDA IrDA 8 LON LON 9 USCLKS Clock Selection 4 2 USCLKSSelect MCK Peripheral clock is selected 0 DIV Peripheral clock divided (DIV=DIV=8) is selected 1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 2 SCK Serial clock (SCK) is selected 3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 USART_US_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 USART_US_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 USART_US_RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 USART_US_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be Transmitted 15 1 USART_US_TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 USART_US_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5591873 USART_US_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART1 Universal Synchronous Asynchronous Receiver Transmitter 1 USART 0x0 0x0 0x4000 registers n USART1 14 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n DTRDIS Data Terminal Ready Disable 17 1 write-only DTREN Data Terminal Ready Enable 16 1 write-only LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only RETTO Start Time-out Immediately 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Pin Control 19 1 write-only RTSEN Request to Send Pin Control 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Clear TIMEOUT Flag and Start Time-out After Next Character Received 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register 0x0 32 write-only n FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 read-only DCD Image of DCD Input 22 1 read-only DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 read-only DSR Image of DSR Input 21 1 read-only DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 read-only FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 read-only MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 read-only NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RI Image of RI Input 20 1 read-only RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 read-only RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_LIN_MODE Channel Status Register 0x14 32 read-only n 0x0 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only LINBE LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) 25 1 read-only LINBK LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) 13 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINCE LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) 28 1 read-only LINHTE LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) 31 1 read-only LINID LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) 14 1 read-only LINIPE LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 27 1 read-only LINISFE LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) 26 1 read-only LINSNRE LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) 29 1 read-only LINSTE LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) 30 1 read-only LINTC LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) 15 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RXRDY Receiver Ready (cleared by reading US_THR) 0 1 read-only TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.RSTSTA) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_LON_MODE Channel Status Register 0x14 32 read-only n 0x0 LBLOVFE LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) 28 1 read-only LCOL LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) 25 1 read-only LCRCE LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only LFET LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) 26 1 read-only LRXD LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) 27 1 read-only LSFE LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only LTXD LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) 24 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only CSR_SPI_MODE Channel Status Register 0x14 32 read-only n 0x0 NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 23 1 read-only NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 19 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 16 read-write FIDI_LON_MODE FI DI Ratio Register 0x40 32 read-write n 0x0 BETA2 LON BETA2 Length 0 24 read-write ICDIFF IC DIFF Register 0x88 32 read-write n 0x0 ICDIFF IC Differentiator Number 0 4 read-write IDR Interrupt Disable Register 0xC 32 write-only n CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 write-only DSRIC Data Set Ready Input Change Disable 17 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RIIC Ring Indicator Input Change Disable 16 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LIN_MODE Interrupt Disable Register 0xC 32 write-only n FRAME Framing Error Interrupt Disable 6 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINHTE LIN Header Timeout Error Interrupt Disable 31 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LON_MODE Interrupt Disable Register 0xC 32 write-only n LBLOVFE LON Backlog Overflow Error Interrupt Disable 28 1 write-only LCOL LON Collision Interrupt Disable 25 1 write-only LCRCE LON CRC Error Interrupt Disable 7 1 write-only LFET LON Frame Early Termination Interrupt Disable 26 1 write-only LRXD LON Reception Done Interrupt Disable 27 1 write-only LSFE LON Short Frame Error Interrupt Disable 6 1 write-only LTXD LON Transmission Done Interrupt Disable 24 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE Underrun Error Interrupt Disable 10 1 write-only IDR_SPI_MODE Interrupt Disable Register 0xC 32 write-only n NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable 19 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IDTRX LON IDT Rx Register 0x84 32 read-write n 0x0 IDTRX LON Indeterminate Time after Reception (comm_type = 1 mode only) 0 24 read-write IDTTX LON IDT Tx Register 0x80 32 read-write n 0x0 IDTTX LON Indeterminate Time after Transmission (comm_type = 1 mode only) 0 24 read-write IER Interrupt Enable Register 0x8 32 write-only n CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 write-only DSRIC Data Set Ready Input Change Enable 17 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RIIC Ring Indicator Input Change Enable 16 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LIN_MODE Interrupt Enable Register 0x8 32 write-only n FRAME Framing Error Interrupt Enable 6 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINHTE LIN Header Timeout Error Interrupt Enable 31 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LON_MODE Interrupt Enable Register 0x8 32 write-only n LBLOVFE LON Backlog Overflow Error Interrupt Enable 28 1 write-only LCOL LON Collision Interrupt Enable 25 1 write-only LCRCE LON CRC Error Interrupt Enable 7 1 write-only LFET LON Frame Early Termination Interrupt Enable 26 1 write-only LRXD LON Reception Done Interrupt Enable 27 1 write-only LSFE LON Short Frame Error Interrupt Enable 6 1 write-only LTXD LON Transmission Done Interrupt Enable 24 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE Underrun Error Interrupt Enable 10 1 write-only IER_SPI_MODE Interrupt Enable Register 0x8 32 write-only n NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable 19 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 read-only DSRIC Data Set Ready Input Change Mask 17 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RIIC Ring Indicator Input Change Mask 16 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LIN_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 FRAME Framing Error Interrupt Mask 6 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINHTE LIN Header Timeout Error Interrupt Mask 31 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LON_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 LBLOVFE LON Backlog Overflow Error Interrupt Mask 28 1 read-only LCOL LON Collision Interrupt Mask 25 1 read-only LCRCE LON CRC Error Interrupt Mask 7 1 read-only LFET LON Frame Early Termination Interrupt Mask 26 1 read-only LRXD LON Reception Done Interrupt Mask 27 1 read-only LSFE LON Short Frame Error Interrupt Mask 6 1 read-only LTXD LON Transmission Done Interrupt Mask 24 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE Underrun Error Interrupt Mask 10 1 read-only IMR_SPI_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask 19 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only LINIR LIN Identifier Register 0x58 32 read-write n 0x0 IDCHR Identifier Character 0 8 read-write LINMR LIN Mode Register 0x54 32 read-write n 0x0 CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLC Data Length Control 8 8 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write PDCM DMAC Mode 16 1 read-write SYNCDIS Synchronization Disable 17 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write LONB1RX LON Beta1 Rx Register 0x78 32 read-write n 0x0 BETA1RX LON Beta1 Length after Reception 0 24 read-write LONB1TX LON Beta1 Tx Register 0x74 32 read-write n 0x0 BETA1TX LON Beta1 Length after Transmission 0 24 read-write LONBL LON Backlog Register 0x70 32 read-only n 0x0 LONBL LON Node Backlog Value 0 6 read-only LONDL LON Data Length Register 0x68 32 read-write n 0x0 LONDL LON Data Length 0 8 read-write LONL2HDR LON L2HDR Register 0x6C 32 read-write n 0x0 ALTP LON Alternate Path Bit 6 1 read-write BLI LON Backlog Increment 0 6 read-write PB LON Priority Bit 7 1 read-write LONMR LON Mode Register 0x60 32 read-write n 0x0 CDTAIL LON Collision Detection on Frame Tail 3 1 read-write COLDET LON Collision Detection Feature 1 1 read-write COMMT LON comm_type Parameter Value 0 1 read-write DMAM LON DMA Mode 4 1 read-write EOFS End of Frame Condition Size 16 8 read-write LCDS LON Collision Detection Source 5 1 read-write TCOL Terminate Frame upon Collision Notification 2 1 read-write LONPR LON Preamble Register 0x64 32 read-write n 0x0 LONPL LON Preamble Length 0 14 read-write LONPRIO LON Priority Register 0x7C 32 read-write n 0x0 NPS LON Node Priority Slot 8 7 read-write PSNB LON Priority Slot Number 0 7 read-write MAN Manchester Configuration Register 0x50 32 read-write n 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RXIDLEV 31 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 MODEM Modem 0x3 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LON LON 0x9 SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=DIV=8) is selected 0x1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 0x2 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register 0x4 32 read-write n 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 NB_ERRORS Number of Errors 0 8 read-only RHR Receive Holding Register 0x18 32 read-only n 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 TO Time-out Value 0 17 read-write THR Transmit Holding Register 0x1C 32 write-only n TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 TG Timeguard Value 0 8 read-write TTGR_LON_MODE Transmitter Timeguard Register 0x28 32 read-write n 0x0 PCYCLE LON PCYCLE Length 0 24 read-write USART_US_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 FP Fractional Part 16 3 USART_US_CR Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTREN Data Terminal Ready Enable 16 1 LINABT Abort LIN Transmission 20 1 LINWKUP Send LIN Wakeup Signal 21 1 RETTO Start Time-out Immediately 15 1 RSTIT Reset Iterations 13 1 RSTNACK Reset Non Acknowledge 14 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RTSDIS Request to Send Pin Control 19 1 RTSEN Request to Send Pin Control 18 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 SENDA Send Address 12 1 STPBRK Stop Break 10 1 STTBRK Start Break 9 1 STTTO Clear TIMEOUT Flag and Start Time-out After Next Character Received 11 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 USART_US_CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 DCD Image of DCD Input 22 1 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSR Image of DSR Input 21 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RI Image of RI Input 20 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 USART_US_FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 16 USART_US_ICDIFF IC DIFF Register 0x88 32 read-write n 0x0 0x0 ICDIFF IC Differentiator Number 0 4 USART_US_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 ITER Max Number of Repetitions Reached Interrupt Disable 10 1 MANE Manchester Error Interrupt Disable 24 1 NACK Non Acknowledge Interrupt Disable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXBRK Receiver Break Interrupt Disable 2 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Time-out Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 USART_US_IDTRX LON IDT Rx Register 0x84 32 read-write n 0x0 0x0 IDTRX LON Indeterminate Time after Reception (comm_type = 1 mode only) 0 24 USART_US_IDTTX LON IDT Tx Register 0x80 32 read-write n 0x0 0x0 IDTTX LON Indeterminate Time after Transmission (comm_type = 1 mode only) 0 24 USART_US_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DSRIC Data Set Ready Input Change Enable 17 1 FRAME Framing Error Interrupt Enable 6 1 ITER Max number of Repetitions Reached Interrupt Enable 10 1 MANE Manchester Error Interrupt Enable 24 1 NACK Non Acknowledge Interrupt Enable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RIIC Ring Indicator Input Change Enable 16 1 RXBRK Receiver Break Interrupt Enable 2 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Time-out Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 USART_US_IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 USART_US_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 ITER Max Number of Repetitions Reached Interrupt Mask 10 1 MANE Manchester Error Interrupt Mask 24 1 NACK Non Acknowledge Interrupt Mask 13 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXBRK Receiver Break Interrupt Mask 2 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Time-out Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 USART_US_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 USART_US_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 USART_US_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The USART transmits the response. 0 SUBSCRIBE The USART receives the response. 1 IGNORE The USART does not transmit and does not receive the response. 2 PARDIS Parity Disable 2 1 PDCM DMAC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 USART_US_LONB1RX LON Beta1 Rx Register 0x78 32 read-write n 0x0 0x0 BETA1RX LON Beta1 Length after Reception 0 24 USART_US_LONB1TX LON Beta1 Tx Register 0x74 32 read-write n 0x0 0x0 BETA1TX LON Beta1 Length after Transmission 0 24 USART_US_LONBL LON Backlog Register 0x70 32 read-only n 0x0 0x0 LONBL LON Node Backlog Value 0 6 USART_US_LONDL LON Data Length Register 0x68 32 read-write n 0x0 0x0 LONDL LON Data Length 0 8 USART_US_LONL2HDR LON L2HDR Register 0x6C 32 read-write n 0x0 0x0 ALTP LON Alternate Path Bit 6 1 BLI LON Backlog Increment 0 6 PB LON Priority Bit 7 1 USART_US_LONMR LON Mode Register 0x60 32 read-write n 0x0 0x0 CDTAIL LON Collision Detection on Frame Tail 3 1 COLDET LON Collision Detection Feature 1 1 COMMT LON comm_type Parameter Value 0 1 DMAM LON DMA Mode 4 1 EOFS End of Frame Condition Size 16 8 LCDS LON Collision Detection Source 5 1 TCOL Terminate Frame upon Collision Notification 2 1 USART_US_LONPR LON Preamble Register 0x64 32 read-write n 0x0 0x0 LONPL LON Preamble Length 0 14 USART_US_LONPRIO LON Priority Register 0x7C 32 read-write n 0x0 0x0 NPS LON Node Priority Slot 8 7 PSNB LON Priority Slot Number 0 7 USART_US_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 ONE Must Be Set to 1 29 1 RXIDLEV 31 1 RX_MPOL Receiver Manchester Polarity 28 1 RX_PL Receiver Preamble Length 16 4 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect ALL_ONE The preamble is composed of '1's 0 ALL_ZERO The preamble is composed of '0's 1 ZERO_ONE The preamble is composed of '01's 2 ONE_ZERO The preamble is composed of '10's 3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_PL Transmitter Preamble Length 0 4 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect ALL_ONE The preamble is composed of '1's 0 ALL_ZERO The preamble is composed of '0's 1 ZERO_ONE The preamble is composed of '01's 2 ONE_ZERO The preamble is composed of '10's 3 USART_US_MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 3 CHRL Character Length 6 2 CHRLSelect _5_BIT Character length is 5 bits 0 _6_BIT Character length is 6 bits 1 _7_BIT Character length is 7 bits 2 _8_BIT Character length is 8 bits 3 CLKO Clock Output Select 18 1 DSNACK Disable Successive NACK 21 1 FILTER Receive Line Filter 28 1 INACK Inhibit Non Acknowledge 20 1 INVDATA Inverted Data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MAX_ITERATION Maximum Number of Automatic Iteration 24 3 MODE9 9-bit Character Length 17 1 MODSYNC Manchester Synchronization Mode 30 1 MSBF Bit Order 16 1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect _1_BIT 1 stop bit 0 _1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 1 _2_BIT 2 stop bits 2 ONEBIT Start Frame Delimiter Selector 31 1 OVER Oversampling Mode 19 1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0 ODD Odd parity 1 SPACE Parity forced to 0 (Space) 2 MARK Parity forced to 1 (Mark) 3 NO No parity 4 MULTIDROP Multidrop mode 6 SYNC Synchronous Mode Select 8 1 USART_MODE USART Mode of Operation 0 4 USART_MODESelect NORMAL Normal mode 0 RS485 RS485 1 SPI_MASTER SPI master 14 SPI_SLAVE SPI Slave 15 HW_HANDSHAKING Hardware Handshaking 2 MODEM Modem 3 IS07816_T_0 IS07816 Protocol: T = 0 4 IS07816_T_1 IS07816 Protocol: T = 1 6 IRDA IrDA 8 LON LON 9 USCLKS Clock Selection 4 2 USCLKSSelect MCK Peripheral clock is selected 0 DIV Peripheral clock divided (DIV=DIV=8) is selected 1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 2 SCK Serial clock (SCK) is selected 3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 USART_US_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 USART_US_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 USART_US_RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 USART_US_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be Transmitted 15 1 USART_US_TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 USART_US_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5591873 USART_US_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USART2 Universal Synchronous Asynchronous Receiver Transmitter 2 USART 0x0 0x0 0x4000 registers n USART2 15 BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 CD Clock Divider 0 16 read-write FP Fractional Part 16 3 read-write CR Control Register 0x0 32 write-only n DTRDIS Data Terminal Ready Disable 17 1 write-only DTREN Data Terminal Ready Enable 16 1 write-only LINABT Abort LIN Transmission 20 1 write-only LINWKUP Send LIN Wakeup Signal 21 1 write-only RETTO Start Time-out Immediately 15 1 write-only RSTIT Reset Iterations 13 1 write-only RSTNACK Reset Non Acknowledge 14 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RTSDIS Request to Send Pin Control 19 1 write-only RTSEN Request to Send Pin Control 18 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only SENDA Send Address 12 1 write-only STPBRK Stop Break 10 1 write-only STTBRK Start Break 9 1 write-only STTTO Clear TIMEOUT Flag and Start Time-out After Next Character Received 11 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CR_SPI_MODE Control Register 0x0 32 write-only n FCS Force SPI Chip Select 18 1 write-only RCS Release SPI Chip Select 19 1 write-only RSTRX Reset Receiver 2 1 write-only RSTSTA Reset Status Bits 8 1 write-only RSTTX Reset Transmitter 3 1 write-only RXDIS Receiver Disable 5 1 write-only RXEN Receiver Enable 4 1 write-only TXDIS Transmitter Disable 7 1 write-only TXEN Transmitter Enable 6 1 write-only CSR Channel Status Register 0x14 32 read-only n 0x0 CTS Image of CTS Input 23 1 read-only CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 read-only DCD Image of DCD Input 22 1 read-only DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 read-only DSR Image of DSR Input 21 1 read-only DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 read-only FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 read-only MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 read-only NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RI Image of RI Input 20 1 read-only RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 read-only RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_LIN_MODE Channel Status Register 0x14 32 read-only n 0x0 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only LINBE LIN Bit Error (cleared by writing a one to bit US_CR.RSTSTA) 25 1 read-only LINBK LIN Break Sent or LIN Break Received (cleared by writing a one to bit US_CR.RSTSTA) 13 1 read-only LINBLS LIN Bus Line Status 23 1 read-only LINCE LIN Checksum Error (cleared by writing a one to bit US_CR.RSTSTA) 28 1 read-only LINHTE LIN Header Timeout Error (cleared by writing a one to bit US_CR.RSTSTA) 31 1 read-only LINID LIN Identifier Sent or LIN Identifier Received (cleared by writing a one to bit US_CR.RSTSTA) 14 1 read-only LINIPE LIN Identifier Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 27 1 read-only LINISFE LIN Inconsistent Synch Field Error (cleared by writing a one to bit US_CR.RSTSTA) 26 1 read-only LINSNRE LIN Slave Not Responding Error (cleared by writing a one to bit US_CR.RSTSTA) 29 1 read-only LINSTE LIN Synch Tolerance Error (cleared by writing a one to bit US_CR.RSTSTA) 30 1 read-only LINTC LIN Transfer Completed (cleared by writing a one to bit US_CR.RSTSTA) 15 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only RXRDY Receiver Ready (cleared by reading US_THR) 0 1 read-only TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.RSTSTA) 8 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only CSR_LON_MODE Channel Status Register 0x14 32 read-only n 0x0 LBLOVFE LON Backlog Overflow Error (cleared by writing a one to bit US_CR.RSTSTA) 28 1 read-only LCOL LON Collision Detected Flag (cleared by writing a one to bit US_CR.RSTSTA) 25 1 read-only LCRCE LON CRC Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 read-only LFET LON Frame Early Termination (cleared by writing a one to bit US_CR.RSTSTA) 26 1 read-only LRXD LON Reception End Flag (cleared by writing a one to bit US_CR.RSTSTA) 27 1 read-only LSFE LON Short Frame Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 read-only LTXD LON Transmission End Flag (cleared by writing a one to bit US_CR.RSTSTA) 24 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only CSR_SPI_MODE Channel Status Register 0x14 32 read-only n 0x0 NSS NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 23 1 read-only NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event (cleared on read) 19 1 read-only OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 read-only RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 read-only TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 read-only TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 read-only UNRE Underrun Error (cleared by writing a one to bit US_CR.RSTSTA) 10 1 read-only FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 16 read-write FIDI_LON_MODE FI DI Ratio Register 0x40 32 read-write n 0x0 BETA2 LON BETA2 Length 0 24 read-write ICDIFF IC DIFF Register 0x88 32 read-write n 0x0 ICDIFF IC Differentiator Number 0 4 read-write IDR Interrupt Disable Register 0xC 32 write-only n CTSIC Clear to Send Input Change Interrupt Disable 19 1 write-only DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 write-only DSRIC Data Set Ready Input Change Disable 17 1 write-only FRAME Framing Error Interrupt Disable 6 1 write-only ITER Max Number of Repetitions Reached Interrupt Disable 10 1 write-only MANE Manchester Error Interrupt Disable 24 1 write-only NACK Non Acknowledge Interrupt Disable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RIIC Ring Indicator Input Change Disable 16 1 write-only RXBRK Receiver Break Interrupt Disable 2 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LIN_MODE Interrupt Disable Register 0xC 32 write-only n FRAME Framing Error Interrupt Disable 6 1 write-only LINBE LIN Bus Error Interrupt Disable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Disable 13 1 write-only LINCE LIN Checksum Error Interrupt Disable 28 1 write-only LINHTE LIN Header Timeout Error Interrupt Disable 31 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Disable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Disable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Disable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Disable 29 1 write-only LINSTE LIN Synch Tolerance Error Interrupt Disable 30 1 write-only LINTC LIN Transfer Completed Interrupt Disable 15 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only PARE Parity Error Interrupt Disable 7 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TIMEOUT Time-out Interrupt Disable 8 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only IDR_LON_MODE Interrupt Disable Register 0xC 32 write-only n LBLOVFE LON Backlog Overflow Error Interrupt Disable 28 1 write-only LCOL LON Collision Interrupt Disable 25 1 write-only LCRCE LON CRC Error Interrupt Disable 7 1 write-only LFET LON Frame Early Termination Interrupt Disable 26 1 write-only LRXD LON Reception Done Interrupt Disable 27 1 write-only LSFE LON Short Frame Error Interrupt Disable 6 1 write-only LTXD LON Transmission Done Interrupt Disable 24 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE Underrun Error Interrupt Disable 10 1 write-only IDR_SPI_MODE Interrupt Disable Register 0xC 32 write-only n NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable 19 1 write-only OVRE Overrun Error Interrupt Disable 5 1 write-only RXRDY RXRDY Interrupt Disable 0 1 write-only TXEMPTY TXEMPTY Interrupt Disable 9 1 write-only TXRDY TXRDY Interrupt Disable 1 1 write-only UNRE SPI Underrun Error Interrupt Disable 10 1 write-only IDTRX LON IDT Rx Register 0x84 32 read-write n 0x0 IDTRX LON Indeterminate Time after Reception (comm_type = 1 mode only) 0 24 read-write IDTTX LON IDT Tx Register 0x80 32 read-write n 0x0 IDTTX LON Indeterminate Time after Transmission (comm_type = 1 mode only) 0 24 read-write IER Interrupt Enable Register 0x8 32 write-only n CTSIC Clear to Send Input Change Interrupt Enable 19 1 write-only DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 write-only DSRIC Data Set Ready Input Change Enable 17 1 write-only FRAME Framing Error Interrupt Enable 6 1 write-only ITER Max number of Repetitions Reached Interrupt Enable 10 1 write-only MANE Manchester Error Interrupt Enable 24 1 write-only NACK Non Acknowledge Interrupt Enable 13 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RIIC Ring Indicator Input Change Enable 16 1 write-only RXBRK Receiver Break Interrupt Enable 2 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LIN_MODE Interrupt Enable Register 0x8 32 write-only n FRAME Framing Error Interrupt Enable 6 1 write-only LINBE LIN Bus Error Interrupt Enable 25 1 write-only LINBK LIN Break Sent or LIN Break Received Interrupt Enable 13 1 write-only LINCE LIN Checksum Error Interrupt Enable 28 1 write-only LINHTE LIN Header Timeout Error Interrupt Enable 31 1 write-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Enable 14 1 write-only LINIPE LIN Identifier Parity Interrupt Enable 27 1 write-only LINISFE LIN Inconsistent Synch Field Error Interrupt Enable 26 1 write-only LINSNRE LIN Slave Not Responding Error Interrupt Enable 29 1 write-only LINSTE LIN Synch Tolerance Error Interrupt Enable 30 1 write-only LINTC LIN Transfer Completed Interrupt Enable 15 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only PARE Parity Error Interrupt Enable 7 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TIMEOUT Time-out Interrupt Enable 8 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only IER_LON_MODE Interrupt Enable Register 0x8 32 write-only n LBLOVFE LON Backlog Overflow Error Interrupt Enable 28 1 write-only LCOL LON Collision Interrupt Enable 25 1 write-only LCRCE LON CRC Error Interrupt Enable 7 1 write-only LFET LON Frame Early Termination Interrupt Enable 26 1 write-only LRXD LON Reception Done Interrupt Enable 27 1 write-only LSFE LON Short Frame Error Interrupt Enable 6 1 write-only LTXD LON Transmission Done Interrupt Enable 24 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE Underrun Error Interrupt Enable 10 1 write-only IER_SPI_MODE Interrupt Enable Register 0x8 32 write-only n NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Enable 19 1 write-only OVRE Overrun Error Interrupt Enable 5 1 write-only RXRDY RXRDY Interrupt Enable 0 1 write-only TXEMPTY TXEMPTY Interrupt Enable 9 1 write-only TXRDY TXRDY Interrupt Enable 1 1 write-only UNRE SPI Underrun Error Interrupt Enable 10 1 write-only IF IrDA Filter Register 0x4C 32 read-write n 0x0 IRDA_FILTER IrDA Filter 0 8 read-write IMR Interrupt Mask Register 0x10 32 read-only n 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 read-only DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 read-only DSRIC Data Set Ready Input Change Mask 17 1 read-only FRAME Framing Error Interrupt Mask 6 1 read-only ITER Max Number of Repetitions Reached Interrupt Mask 10 1 read-only MANE Manchester Error Interrupt Mask 24 1 read-only NACK Non Acknowledge Interrupt Mask 13 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RIIC Ring Indicator Input Change Mask 16 1 read-only RXBRK Receiver Break Interrupt Mask 2 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LIN_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 FRAME Framing Error Interrupt Mask 6 1 read-only LINBE LIN Bus Error Interrupt Mask 25 1 read-only LINBK LIN Break Sent or LIN Break Received Interrupt Mask 13 1 read-only LINCE LIN Checksum Error Interrupt Mask 28 1 read-only LINHTE LIN Header Timeout Error Interrupt Mask 31 1 read-only LINID LIN Identifier Sent or LIN Identifier Received Interrupt Mask 14 1 read-only LINIPE LIN Identifier Parity Interrupt Mask 27 1 read-only LINISFE LIN Inconsistent Synch Field Error Interrupt Mask 26 1 read-only LINSNRE LIN Slave Not Responding Error Interrupt Mask 29 1 read-only LINSTE LIN Synch Tolerance Error Interrupt Mask 30 1 read-only LINTC LIN Transfer Completed Interrupt Mask 15 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only PARE Parity Error Interrupt Mask 7 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TIMEOUT Time-out Interrupt Mask 8 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only IMR_LON_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 LBLOVFE LON Backlog Overflow Error Interrupt Mask 28 1 read-only LCOL LON Collision Interrupt Mask 25 1 read-only LCRCE LON CRC Error Interrupt Mask 7 1 read-only LFET LON Frame Early Termination Interrupt Mask 26 1 read-only LRXD LON Reception Done Interrupt Mask 27 1 read-only LSFE LON Short Frame Error Interrupt Mask 6 1 read-only LTXD LON Transmission Done Interrupt Mask 24 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE Underrun Error Interrupt Mask 10 1 read-only IMR_SPI_MODE Interrupt Mask Register 0x10 32 read-only n 0x0 NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask 19 1 read-only OVRE Overrun Error Interrupt Mask 5 1 read-only RXRDY RXRDY Interrupt Mask 0 1 read-only TXEMPTY TXEMPTY Interrupt Mask 9 1 read-only TXRDY TXRDY Interrupt Mask 1 1 read-only UNRE SPI Underrun Error Interrupt Mask 10 1 read-only LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 LINCD Clock Divider after Synchronization 0 16 read-only LINFP Fractional Part after Synchronization 16 3 read-only LINIR LIN Identifier Register 0x58 32 read-write n 0x0 IDCHR Identifier Character 0 8 read-write LINMR LIN Mode Register 0x54 32 read-write n 0x0 CHKDIS Checksum Disable 3 1 read-write CHKTYP Checksum Type 4 1 read-write DLC Data Length Control 8 8 read-write DLM Data Length Mode 5 1 read-write FSDIS Frame Slot Mode Disable 6 1 read-write NACT LIN Node Action 0 2 read-write PUBLISH The USART transmits the response. 0x0 SUBSCRIBE The USART receives the response. 0x1 IGNORE The USART does not transmit and does not receive the response. 0x2 PARDIS Parity Disable 2 1 read-write PDCM DMAC Mode 16 1 read-write SYNCDIS Synchronization Disable 17 1 read-write WKUPTYP Wakeup Signal Type 7 1 read-write LONB1RX LON Beta1 Rx Register 0x78 32 read-write n 0x0 BETA1RX LON Beta1 Length after Reception 0 24 read-write LONB1TX LON Beta1 Tx Register 0x74 32 read-write n 0x0 BETA1TX LON Beta1 Length after Transmission 0 24 read-write LONBL LON Backlog Register 0x70 32 read-only n 0x0 LONBL LON Node Backlog Value 0 6 read-only LONDL LON Data Length Register 0x68 32 read-write n 0x0 LONDL LON Data Length 0 8 read-write LONL2HDR LON L2HDR Register 0x6C 32 read-write n 0x0 ALTP LON Alternate Path Bit 6 1 read-write BLI LON Backlog Increment 0 6 read-write PB LON Priority Bit 7 1 read-write LONMR LON Mode Register 0x60 32 read-write n 0x0 CDTAIL LON Collision Detection on Frame Tail 3 1 read-write COLDET LON Collision Detection Feature 1 1 read-write COMMT LON comm_type Parameter Value 0 1 read-write DMAM LON DMA Mode 4 1 read-write EOFS End of Frame Condition Size 16 8 read-write LCDS LON Collision Detection Source 5 1 read-write TCOL Terminate Frame upon Collision Notification 2 1 read-write LONPR LON Preamble Register 0x64 32 read-write n 0x0 LONPL LON Preamble Length 0 14 read-write LONPRIO LON Priority Register 0x7C 32 read-write n 0x0 NPS LON Node Priority Slot 8 7 read-write PSNB LON Priority Slot Number 0 7 read-write MAN Manchester Configuration Register 0x50 32 read-write n 0x0 DRIFT Drift Compensation 30 1 read-write ONE Must Be Set to 1 29 1 read-write RXIDLEV 31 1 read-write RX_MPOL Receiver Manchester Polarity 28 1 read-write RX_PL Receiver Preamble Length 16 4 read-write RX_PP Receiver Preamble Pattern detected 24 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 TX_MPOL Transmitter Manchester Polarity 12 1 read-write TX_PL Transmitter Preamble Length 0 4 read-write TX_PP Transmitter Preamble Pattern 8 2 read-write ALL_ONE The preamble is composed of '1's 0x0 ALL_ZERO The preamble is composed of '0's 0x1 ZERO_ONE The preamble is composed of '01's 0x2 ONE_ZERO The preamble is composed of '10's 0x3 MR Mode Register 0x4 32 read-write n 0x0 CHMODE Channel Mode 14 2 read-write NORMAL Normal mode 0x0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 0x1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 0x2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 0x3 CHRL Character Length 6 2 read-write 5_BIT Character length is 5 bits 0x0 6_BIT Character length is 6 bits 0x1 7_BIT Character length is 7 bits 0x2 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write DSNACK Disable Successive NACK 21 1 read-write FILTER Receive Line Filter 28 1 read-write INACK Inhibit Non Acknowledge 20 1 read-write INVDATA Inverted Data 23 1 read-write MAN Manchester Encoder/Decoder Enable 29 1 read-write MAX_ITERATION Maximum Number of Automatic Iteration 24 3 read-write MODE9 9-bit Character Length 17 1 read-write MODSYNC Manchester Synchronization Mode 30 1 read-write MSBF Bit Order 16 1 read-write NBSTOP Number of Stop Bits 12 2 read-write 1_BIT 1 stop bit 0x0 1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 0x1 2_BIT 2 stop bits 0x2 ONEBIT Start Frame Delimiter Selector 31 1 read-write OVER Oversampling Mode 19 1 read-write PAR Parity Type 9 3 read-write EVEN Even parity 0x0 ODD Odd parity 0x1 SPACE Parity forced to 0 (Space) 0x2 MARK Parity forced to 1 (Mark) 0x3 NO No parity 0x4 MULTIDROP Multidrop mode 0x6 SYNC Synchronous Mode Select 8 1 read-write USART_MODE USART Mode of Operation 0 4 read-write NORMAL Normal mode 0x0 RS485 RS485 0x1 HW_HANDSHAKING Hardware Handshaking 0x2 MODEM Modem 0x3 IS07816_T_0 IS07816 Protocol: T = 0 0x4 IS07816_T_1 IS07816 Protocol: T = 1 0x6 IRDA IrDA 0x8 LON LON 0x9 SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=DIV=8) is selected 0x1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 0x2 SCK Serial clock (SCK) is selected 0x3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 read-write MR_SPI_MODE Mode Register 0x4 32 read-write n 0x0 CHRL Character Length 6 2 read-write 8_BIT Character length is 8 bits 0x3 CLKO Clock Output Select 18 1 read-write CPHA SPI Clock Phase 8 1 read-write CPOL SPI Clock Polarity 16 1 read-write USART_MODE USART Mode of Operation 0 4 read-write SPI_MASTER SPI master 0xE SPI_SLAVE SPI Slave 0xF USCLKS Clock Selection 4 2 read-write MCK Peripheral clock is selected 0x0 DIV Peripheral clock divided (DIV=DIV=8) is selected 0x1 SCK Serial Clock SLK is selected 0x3 WRDBT Wait Read Data Before Transfer 20 1 read-write NER Number of Errors Register 0x44 32 read-only n 0x0 NB_ERRORS Number of Errors 0 8 read-only RHR Receive Holding Register 0x18 32 read-only n 0x0 RXCHR Received Character 0 9 read-only RXSYNH Received Sync 15 1 read-only RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 TO Time-out Value 0 17 read-write THR Transmit Holding Register 0x1C 32 write-only n TXCHR Character to be Transmitted 0 9 write-only TXSYNH Sync Field to be Transmitted 15 1 write-only TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 TG Timeguard Value 0 8 read-write TTGR_LON_MODE Transmitter Timeguard Register 0x28 32 read-write n 0x0 PCYCLE LON PCYCLE Length 0 24 read-write USART_US_BRGR Baud Rate Generator Register 0x20 32 read-write n 0x0 0x0 CD Clock Divider 0 16 FP Fractional Part 16 3 USART_US_CR Control Register 0x0 32 write-only n 0x0 0x0 DTRDIS Data Terminal Ready Disable 17 1 DTREN Data Terminal Ready Enable 16 1 LINABT Abort LIN Transmission 20 1 LINWKUP Send LIN Wakeup Signal 21 1 RETTO Start Time-out Immediately 15 1 RSTIT Reset Iterations 13 1 RSTNACK Reset Non Acknowledge 14 1 RSTRX Reset Receiver 2 1 RSTSTA Reset Status Bits 8 1 RSTTX Reset Transmitter 3 1 RTSDIS Request to Send Pin Control 19 1 RTSEN Request to Send Pin Control 18 1 RXDIS Receiver Disable 5 1 RXEN Receiver Enable 4 1 SENDA Send Address 12 1 STPBRK Stop Break 10 1 STTBRK Start Break 9 1 STTTO Clear TIMEOUT Flag and Start Time-out After Next Character Received 11 1 TXDIS Transmitter Disable 7 1 TXEN Transmitter Enable 6 1 USART_US_CSR Channel Status Register 0x14 32 read-only n 0x0 0x0 CTS Image of CTS Input 23 1 CTSIC Clear to Send Input Change Flag (cleared on read) 19 1 DCD Image of DCD Input 22 1 DCDIC Data Carrier Detect Input Change Flag (cleared on read) 18 1 DSR Image of DSR Input 21 1 DSRIC Data Set Ready Input Change Flag (cleared on read) 17 1 FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA) 6 1 ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT) 10 1 MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA) 24 1 NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK) 13 1 OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA) 5 1 PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA) 7 1 RI Image of RI Input 20 1 RIIC Ring Indicator Input Change Flag (cleared on read) 16 1 RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA) 2 1 RXRDY Receiver Ready (cleared by reading US_RHR) 0 1 TIMEOUT Receiver Time-out (cleared by writing a one to bit US_CR.STTTO) 8 1 TXEMPTY Transmitter Empty (cleared by writing US_THR) 9 1 TXRDY Transmitter Ready (cleared by writing US_THR) 1 1 USART_US_FIDI FI DI Ratio Register 0x40 32 read-write n 0x0 0x0 FI_DI_RATIO FI Over DI Ratio Value 0 16 USART_US_ICDIFF IC DIFF Register 0x88 32 read-write n 0x0 0x0 ICDIFF IC Differentiator Number 0 4 USART_US_IDR Interrupt Disable Register 0xC 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Disable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Disable 18 1 DSRIC Data Set Ready Input Change Disable 17 1 FRAME Framing Error Interrupt Disable 6 1 ITER Max Number of Repetitions Reached Interrupt Disable 10 1 MANE Manchester Error Interrupt Disable 24 1 NACK Non Acknowledge Interrupt Disable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Disable 7 1 RIIC Ring Indicator Input Change Disable 16 1 RXBRK Receiver Break Interrupt Disable 2 1 RXRDY RXRDY Interrupt Disable 0 1 TIMEOUT Time-out Interrupt Disable 8 1 TXEMPTY TXEMPTY Interrupt Disable 9 1 TXRDY TXRDY Interrupt Disable 1 1 USART_US_IDTRX LON IDT Rx Register 0x84 32 read-write n 0x0 0x0 IDTRX LON Indeterminate Time after Reception (comm_type = 1 mode only) 0 24 USART_US_IDTTX LON IDT Tx Register 0x80 32 read-write n 0x0 0x0 IDTTX LON Indeterminate Time after Transmission (comm_type = 1 mode only) 0 24 USART_US_IER Interrupt Enable Register 0x8 32 write-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Enable 19 1 DCDIC Data Carrier Detect Input Change Interrupt Enable 18 1 DSRIC Data Set Ready Input Change Enable 17 1 FRAME Framing Error Interrupt Enable 6 1 ITER Max number of Repetitions Reached Interrupt Enable 10 1 MANE Manchester Error Interrupt Enable 24 1 NACK Non Acknowledge Interrupt Enable 13 1 OVRE Overrun Error Interrupt Enable 5 1 PARE Parity Error Interrupt Enable 7 1 RIIC Ring Indicator Input Change Enable 16 1 RXBRK Receiver Break Interrupt Enable 2 1 RXRDY RXRDY Interrupt Enable 0 1 TIMEOUT Time-out Interrupt Enable 8 1 TXEMPTY TXEMPTY Interrupt Enable 9 1 TXRDY TXRDY Interrupt Enable 1 1 USART_US_IF IrDA Filter Register 0x4C 32 read-write n 0x0 0x0 IRDA_FILTER IrDA Filter 0 8 USART_US_IMR Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 CTSIC Clear to Send Input Change Interrupt Mask 19 1 DCDIC Data Carrier Detect Input Change Interrupt Mask 18 1 DSRIC Data Set Ready Input Change Mask 17 1 FRAME Framing Error Interrupt Mask 6 1 ITER Max Number of Repetitions Reached Interrupt Mask 10 1 MANE Manchester Error Interrupt Mask 24 1 NACK Non Acknowledge Interrupt Mask 13 1 OVRE Overrun Error Interrupt Mask 5 1 PARE Parity Error Interrupt Mask 7 1 RIIC Ring Indicator Input Change Mask 16 1 RXBRK Receiver Break Interrupt Mask 2 1 RXRDY RXRDY Interrupt Mask 0 1 TIMEOUT Time-out Interrupt Mask 8 1 TXEMPTY TXEMPTY Interrupt Mask 9 1 TXRDY TXRDY Interrupt Mask 1 1 USART_US_LINBRR LIN Baud Rate Register 0x5C 32 read-only n 0x0 0x0 LINCD Clock Divider after Synchronization 0 16 LINFP Fractional Part after Synchronization 16 3 USART_US_LINIR LIN Identifier Register 0x58 32 read-write n 0x0 0x0 IDCHR Identifier Character 0 8 USART_US_LINMR LIN Mode Register 0x54 32 read-write n 0x0 0x0 CHKDIS Checksum Disable 3 1 CHKTYP Checksum Type 4 1 DLC Data Length Control 8 8 DLM Data Length Mode 5 1 FSDIS Frame Slot Mode Disable 6 1 NACT LIN Node Action 0 2 NACTSelect PUBLISH The USART transmits the response. 0 SUBSCRIBE The USART receives the response. 1 IGNORE The USART does not transmit and does not receive the response. 2 PARDIS Parity Disable 2 1 PDCM DMAC Mode 16 1 SYNCDIS Synchronization Disable 17 1 WKUPTYP Wakeup Signal Type 7 1 USART_US_LONB1RX LON Beta1 Rx Register 0x78 32 read-write n 0x0 0x0 BETA1RX LON Beta1 Length after Reception 0 24 USART_US_LONB1TX LON Beta1 Tx Register 0x74 32 read-write n 0x0 0x0 BETA1TX LON Beta1 Length after Transmission 0 24 USART_US_LONBL LON Backlog Register 0x70 32 read-only n 0x0 0x0 LONBL LON Node Backlog Value 0 6 USART_US_LONDL LON Data Length Register 0x68 32 read-write n 0x0 0x0 LONDL LON Data Length 0 8 USART_US_LONL2HDR LON L2HDR Register 0x6C 32 read-write n 0x0 0x0 ALTP LON Alternate Path Bit 6 1 BLI LON Backlog Increment 0 6 PB LON Priority Bit 7 1 USART_US_LONMR LON Mode Register 0x60 32 read-write n 0x0 0x0 CDTAIL LON Collision Detection on Frame Tail 3 1 COLDET LON Collision Detection Feature 1 1 COMMT LON comm_type Parameter Value 0 1 DMAM LON DMA Mode 4 1 EOFS End of Frame Condition Size 16 8 LCDS LON Collision Detection Source 5 1 TCOL Terminate Frame upon Collision Notification 2 1 USART_US_LONPR LON Preamble Register 0x64 32 read-write n 0x0 0x0 LONPL LON Preamble Length 0 14 USART_US_LONPRIO LON Priority Register 0x7C 32 read-write n 0x0 0x0 NPS LON Node Priority Slot 8 7 PSNB LON Priority Slot Number 0 7 USART_US_MAN Manchester Configuration Register 0x50 32 read-write n 0x0 0x0 DRIFT Drift Compensation 30 1 ONE Must Be Set to 1 29 1 RXIDLEV 31 1 RX_MPOL Receiver Manchester Polarity 28 1 RX_PL Receiver Preamble Length 16 4 RX_PP Receiver Preamble Pattern detected 24 2 RX_PPSelect ALL_ONE The preamble is composed of '1's 0 ALL_ZERO The preamble is composed of '0's 1 ZERO_ONE The preamble is composed of '01's 2 ONE_ZERO The preamble is composed of '10's 3 TX_MPOL Transmitter Manchester Polarity 12 1 TX_PL Transmitter Preamble Length 0 4 TX_PP Transmitter Preamble Pattern 8 2 TX_PPSelect ALL_ONE The preamble is composed of '1's 0 ALL_ZERO The preamble is composed of '0's 1 ZERO_ONE The preamble is composed of '01's 2 ONE_ZERO The preamble is composed of '10's 3 USART_US_MR Mode Register 0x4 32 read-write n 0x0 0x0 CHMODE Channel Mode 14 2 CHMODESelect NORMAL Normal mode 0 AUTOMATIC Automatic Echo. Receiver input is connected to the TXD pin. 1 LOCAL_LOOPBACK Local Loopback. Transmitter output is connected to the Receiver Input. 2 REMOTE_LOOPBACK Remote Loopback. RXD pin is internally connected to the TXD pin. 3 CHRL Character Length 6 2 CHRLSelect _5_BIT Character length is 5 bits 0 _6_BIT Character length is 6 bits 1 _7_BIT Character length is 7 bits 2 _8_BIT Character length is 8 bits 3 CLKO Clock Output Select 18 1 DSNACK Disable Successive NACK 21 1 FILTER Receive Line Filter 28 1 INACK Inhibit Non Acknowledge 20 1 INVDATA Inverted Data 23 1 MAN Manchester Encoder/Decoder Enable 29 1 MAX_ITERATION Maximum Number of Automatic Iteration 24 3 MODE9 9-bit Character Length 17 1 MODSYNC Manchester Synchronization Mode 30 1 MSBF Bit Order 16 1 NBSTOP Number of Stop Bits 12 2 NBSTOPSelect _1_BIT 1 stop bit 0 _1_5_BIT 1.5 stop bit (SYNC = 0) or reserved (SYNC = 1) 1 _2_BIT 2 stop bits 2 ONEBIT Start Frame Delimiter Selector 31 1 OVER Oversampling Mode 19 1 PAR Parity Type 9 3 PARSelect EVEN Even parity 0 ODD Odd parity 1 SPACE Parity forced to 0 (Space) 2 MARK Parity forced to 1 (Mark) 3 NO No parity 4 MULTIDROP Multidrop mode 6 SYNC Synchronous Mode Select 8 1 USART_MODE USART Mode of Operation 0 4 USART_MODESelect NORMAL Normal mode 0 RS485 RS485 1 SPI_MASTER SPI master 14 SPI_SLAVE SPI Slave 15 HW_HANDSHAKING Hardware Handshaking 2 MODEM Modem 3 IS07816_T_0 IS07816 Protocol: T = 0 4 IS07816_T_1 IS07816 Protocol: T = 1 6 IRDA IrDA 8 LON LON 9 USCLKS Clock Selection 4 2 USCLKSSelect MCK Peripheral clock is selected 0 DIV Peripheral clock divided (DIV=DIV=8) is selected 1 PCK PMC programmable clock (PCK) is selected. If the SCK pin is driven (CLKO = 1), the CD field must be greater than 1. 2 SCK Serial clock (SCK) is selected 3 VAR_SYNC Variable Synchronization of Command/Data Sync Start Frame Delimiter 22 1 USART_US_NER Number of Errors Register 0x44 32 read-only n 0x0 0x0 NB_ERRORS Number of Errors 0 8 USART_US_RHR Receive Holding Register 0x18 32 read-only n 0x0 0x0 RXCHR Received Character 0 9 RXSYNH Received Sync 15 1 USART_US_RTOR Receiver Time-out Register 0x24 32 read-write n 0x0 0x0 TO Time-out Value 0 17 USART_US_THR Transmit Holding Register 0x1C 32 write-only n 0x0 0x0 TXCHR Character to be Transmitted 0 9 TXSYNH Sync Field to be Transmitted 15 1 USART_US_TTGR Transmitter Timeguard Register 0x28 32 read-write n 0x0 0x0 TG Timeguard Value 0 8 USART_US_WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 0x0 WPEN Write Protection Enable 0 1 WPKEY Write Protection Key 8 24 WPKEYSelect PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 5591873 USART_US_WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 0x0 WPVS Write Protection Violation Status 0 1 WPVSRC Write Protection Violation Source 8 16 WPMR Write Protection Mode Register 0xE4 32 read-write n 0x0 WPEN Write Protection Enable 0 1 read-write WPKEY Write Protection Key 8 24 read-write PASSWD Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. 0x555341 WPSR Write Protection Status Register 0xE8 32 read-only n 0x0 WPVS Write Protection Violation Status 0 1 read-only WPVSRC Write Protection Violation Source 8 16 read-only USBHS USB High-Speed Interface USBHS 0x0 0x0 0x4000 registers n USBHS 34 CTRL General Control Register 0x800 32 read-write n 0x0 0x0 FRZCLK Freeze USB Clock 14 1 RDERRE Remote Device Connection Error Interrupt Enable 4 1 UIMOD USBHS Mode 25 1 UIMODSelect HOST The module is in USB Host mode. 0 DEVICE The module is in USB Device mode. 1 USBE USBHS Enable 15 1 VBUSHWC VBUS Hardware Control 8 1 DEVCTRL Device General Control Register 0x0 32 read-write n 0x0 0x0 ADDEN Address Enable 7 1 DETACH Detach 8 1 LS Low-Speed Mode Force 12 1 OPMODE2 Specific Operational mode 16 1 RMWKUP Remote Wake-Up 9 1 SPDCONF Mode Configuration 10 2 SPDCONFSelect NORMAL The peripheral starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the host is high-speed-capable. 0 LOW_POWER For a better consumption, if high speed is not needed. 1 TSTJ Test mode J 13 1 TSTK Test mode K 14 1 TSTPCKT Test packet mode 15 1 UADD USB Address 0 7 DEVDMAADDRESS1 Device DMA Channel Address Register (n = 1) 0x314 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS2 Device DMA Channel Address Register (n = 2) 0x324 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS3 Device DMA Channel Address Register (n = 3) 0x334 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS4 Device DMA Channel Address Register (n = 4) 0x344 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS5 Device DMA Channel Address Register (n = 5) 0x354 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS6 Device DMA Channel Address Register (n = 6) 0x364 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMAADDRESS7 Device DMA Channel Address Register (n = 7) 0x374 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write DEVDMACONTROL1 Device DMA Channel Control Register (n = 1) 0x318 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL2 Device DMA Channel Control Register (n = 2) 0x328 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL3 Device DMA Channel Control Register (n = 3) 0x338 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL4 Device DMA Channel Control Register (n = 4) 0x348 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL5 Device DMA Channel Control Register (n = 5) 0x358 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL6 Device DMA Channel Control Register (n = 6) 0x368 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMACONTROL7 Device DMA Channel Control Register (n = 7) 0x378 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write DEVDMANXTDSC1 Device DMA Channel Next Descriptor Address Register (n = 1) 0x310 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC2 Device DMA Channel Next Descriptor Address Register (n = 2) 0x320 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC3 Device DMA Channel Next Descriptor Address Register (n = 3) 0x330 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC4 Device DMA Channel Next Descriptor Address Register (n = 4) 0x340 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC5 Device DMA Channel Next Descriptor Address Register (n = 5) 0x350 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC6 Device DMA Channel Next Descriptor Address Register (n = 6) 0x360 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMANXTDSC7 Device DMA Channel Next Descriptor Address Register (n = 7) 0x370 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write DEVDMASTATUS1 Device DMA Channel Status Register (n = 1) 0x31C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS2 Device DMA Channel Status Register (n = 2) 0x32C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS3 Device DMA Channel Status Register (n = 3) 0x33C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS4 Device DMA Channel Status Register (n = 4) 0x34C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS5 Device DMA Channel Status Register (n = 5) 0x35C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS6 Device DMA Channel Status Register (n = 6) 0x36C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMASTATUS7 Device DMA Channel Status Register (n = 7) 0x37C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write DEVDMA[0]-USBHS_DEVDMAADDRESS Device DMA Channel Address Register (n = 1) 0x314 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 DEVDMA[0]-USBHS_DEVDMACONTROL Device DMA Channel Control Register (n = 1) 0x318 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 DEVDMA[0]-USBHS_DEVDMANXTDSC Device DMA Channel Next Descriptor Address Register (n = 1) 0x310 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 DEVDMA[0]-USBHS_DEVDMASTATUS Device DMA Channel Status Register (n = 1) 0x31C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMAADDRESS Device DMA Channel Address Register (n = 1) 0x634 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMACONTROL Device DMA Channel Control Register (n = 1) 0x638 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMANXTDSC Device DMA Channel Next Descriptor Address Register (n = 1) 0x630 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMASTATUS Device DMA Channel Status Register (n = 1) 0x63C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMAADDRESS Device DMA Channel Address Register (n = 1) 0x964 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMACONTROL Device DMA Channel Control Register (n = 1) 0x968 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMANXTDSC Device DMA Channel Next Descriptor Address Register (n = 1) 0x960 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMASTATUS Device DMA Channel Status Register (n = 1) 0x96C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMAADDRESS Device DMA Channel Address Register (n = 1) 0xCA4 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMACONTROL Device DMA Channel Control Register (n = 1) 0xCA8 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMANXTDSC Device DMA Channel Next Descriptor Address Register (n = 1) 0xCA0 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMASTATUS Device DMA Channel Status Register (n = 1) 0xCAC 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMAADDRESS Device DMA Channel Address Register (n = 1) 0xFF4 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMACONTROL Device DMA Channel Control Register (n = 1) 0xFF8 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMANXTDSC Device DMA Channel Next Descriptor Address Register (n = 1) 0xFF0 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMASTATUS Device DMA Channel Status Register (n = 1) 0xFFC 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 DEVDMA[5]-USBHS_DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMAADDRESS Device DMA Channel Address Register (n = 1) 0x1354 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 DEVDMA[5]-USBHS_DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMACONTROL Device DMA Channel Control Register (n = 1) 0x1358 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 DEVDMA[5]-USBHS_DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMANXTDSC Device DMA Channel Next Descriptor Address Register (n = 1) 0x1350 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 DEVDMA[5]-USBHS_DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMASTATUS Device DMA Channel Status Register (n = 1) 0x135C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 DEVDMA[6]-USBHS_DEVDMA[5]-USBHS_DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMAADDRESS Device DMA Channel Address Register (n = 1) 0x16C4 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 DEVDMA[6]-USBHS_DEVDMA[5]-USBHS_DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMACONTROL Device DMA Channel Control Register (n = 1) 0x16C8 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 DEVDMA[6]-USBHS_DEVDMA[5]-USBHS_DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMANXTDSC Device DMA Channel Next Descriptor Address Register (n = 1) 0x16C0 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 DEVDMA[6]-USBHS_DEVDMA[5]-USBHS_DEVDMA[4]-USBHS_DEVDMA[3]-USBHS_DEVDMA[2]-USBHS_DEVDMA[1]-USBHS_DEVDMA[0]-USBHS_DEVDMASTATUS Device DMA Channel Status Register (n = 1) 0x16CC 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 DEVEPT Device Endpoint Register 0x1C 32 read-write n 0x0 0x0 EPEN0 Endpoint 0 Enable 0 1 EPEN1 Endpoint 1 Enable 1 1 EPEN2 Endpoint 2 Enable 2 1 EPEN3 Endpoint 3 Enable 3 1 EPEN4 Endpoint 4 Enable 4 1 EPEN5 Endpoint 5 Enable 5 1 EPEN6 Endpoint 6 Enable 6 1 EPEN7 Endpoint 7 Enable 7 1 EPEN8 Endpoint 8 Enable 8 1 EPEN9 Endpoint 9 Enable 9 1 EPRST0 Endpoint 0 Reset 16 1 EPRST1 Endpoint 1 Reset 17 1 EPRST2 Endpoint 2 Reset 18 1 EPRST3 Endpoint 3 Reset 19 1 EPRST4 Endpoint 4 Reset 20 1 EPRST5 Endpoint 5 Reset 21 1 EPRST6 Endpoint 6 Reset 22 1 EPRST7 Endpoint 7 Reset 23 1 EPRST8 Endpoint 8 Reset 24 1 EPRST9 Endpoint 9 Reset 25 1 DEVEPTCFG0 Device Endpoint Configuration Register (n = 0) 0x100 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG1 Device Endpoint Configuration Register (n = 0) 0x104 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG2 Device Endpoint Configuration Register (n = 0) 0x108 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG3 Device Endpoint Configuration Register (n = 0) 0x10C 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG4 Device Endpoint Configuration Register (n = 0) 0x110 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG5 Device Endpoint Configuration Register (n = 0) 0x114 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG6 Device Endpoint Configuration Register (n = 0) 0x118 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG7 Device Endpoint Configuration Register (n = 0) 0x11C 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG8 Device Endpoint Configuration Register (n = 0) 0x120 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG9 Device Endpoint Configuration Register (n = 0) 0x124 32 read-write n ALLOC Endpoint Memory Allocate 1 1 read-write AUTOSW Automatic Switch 9 1 read-write EPBK Endpoint Banks 2 2 read-write 1_BANK Single-bank endpoint 0x0 2_BANK Double-bank endpoint 0x1 3_BANK Triple-bank endpoint 0x2 EPDIR Endpoint Direction 8 1 read-write OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 EPTYPE Endpoint Type 11 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 read-write 0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0x0 1_TRANS Default value: one transaction per microframe. 0x1 2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 0x2 3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 0x3 DEVEPTCFG[0] Device Endpoint Configuration Register (n = 0) 0 0x200 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[1] Device Endpoint Configuration Register (n = 0) 0 0x304 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[2] Device Endpoint Configuration Register (n = 0) 0 0x40C 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[3] Device Endpoint Configuration Register (n = 0) 0 0x518 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[4] Device Endpoint Configuration Register (n = 0) 0 0x628 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[5] Device Endpoint Configuration Register (n = 0) 0 0x73C 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[6] Device Endpoint Configuration Register (n = 0) 0 0x854 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[7] Device Endpoint Configuration Register (n = 0) 0 0x970 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[8] Device Endpoint Configuration Register (n = 0) 0 0xA90 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTCFG[9] Device Endpoint Configuration Register (n = 0) 0 0xBB4 32 read-write n 0x0 0x0 ALLOC Endpoint Memory Allocate 1 1 AUTOSW Automatic Switch 9 1 EPBK Endpoint Banks 2 2 EPBKSelect _1_BANK Single-bank endpoint 0 _2_BANK Double-bank endpoint 1 _3_BANK Triple-bank endpoint 2 EPDIR Endpoint Direction 8 1 EPDIRSelect OUT The endpoint direction is OUT. 0 IN The endpoint direction is IN (nor for control endpoints). 1 EPSIZE Endpoint Size 4 3 EPSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 EPTYPE Endpoint Type 11 2 EPTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 NBTRANS Number of transactions per microframe for isochronous endpoint 13 2 NBTRANSSelect _0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability. 0 _1_TRANS Default value: one transaction per microframe. 1 _2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank. 2 _3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank. 3 DEVEPTICR0 Device Endpoint Clear Register (n = 0) 0x160 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR0_ISOENPT Device Endpoint Clear Register (n = 0) 0x160 32 write-only n CRCERRIC CRC Error Interrupt Clear 6 1 write-only HBISOFLUSHIC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 write-only HBISOINERRIC High Bandwidth Isochronous IN Underflow Error Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only DEVEPTICR1 Device Endpoint Clear Register (n = 0) 0x164 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR2 Device Endpoint Clear Register (n = 0) 0x168 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR3 Device Endpoint Clear Register (n = 0) 0x16C 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR4 Device Endpoint Clear Register (n = 0) 0x170 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR5 Device Endpoint Clear Register (n = 0) 0x174 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR6 Device Endpoint Clear Register (n = 0) 0x178 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR7 Device Endpoint Clear Register (n = 0) 0x17C 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR8 Device Endpoint Clear Register (n = 0) 0x180 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR9 Device Endpoint Clear Register (n = 0) 0x184 32 write-only n NAKINIC NAKed IN Interrupt Clear 4 1 write-only NAKOUTIC NAKed OUT Interrupt Clear 3 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXOUTIC Received OUT Data Interrupt Clear 1 1 write-only RXSTPIC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETC Short Packet Interrupt Clear 7 1 write-only STALLEDIC STALLed Interrupt Clear 6 1 write-only TXINIC Transmitted IN Data Interrupt Clear 0 1 write-only DEVEPTICR[0] Device Endpoint Clear Register (n = 0) 0 0x2C0 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[1] Device Endpoint Clear Register (n = 0) 0 0x424 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[2] Device Endpoint Clear Register (n = 0) 0 0x58C 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[3] Device Endpoint Clear Register (n = 0) 0 0x6F8 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[4] Device Endpoint Clear Register (n = 0) 0 0x868 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[5] Device Endpoint Clear Register (n = 0) 0 0x9DC 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[6] Device Endpoint Clear Register (n = 0) 0 0xB54 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[7] Device Endpoint Clear Register (n = 0) 0 0xCD0 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[8] Device Endpoint Clear Register (n = 0) 0 0xE50 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTICR[9] Device Endpoint Clear Register (n = 0) 0 0xFD4 32 write-only n 0x0 0x0 NAKINIC NAKed IN Interrupt Clear 4 1 NAKOUTIC NAKed OUT Interrupt Clear 3 1 OVERFIC Overflow Interrupt Clear 5 1 RXOUTIC Received OUT Data Interrupt Clear 1 1 RXSTPIC Received SETUP Interrupt Clear 2 1 SHORTPACKETC Short Packet Interrupt Clear 7 1 STALLEDIC STALLed Interrupt Clear 6 1 TXINIC Transmitted IN Data Interrupt Clear 0 1 DEVEPTIDR0 Device Endpoint Disable Register (n = 0) 0x220 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR0_ISOENPT Device Endpoint Disable Register (n = 0) 0x220 32 write-only n CRCERREC CRC Error Interrupt Clear 6 1 write-only DATAXEC DataX Interrupt Clear 9 1 write-only EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only ERRORTRANSEC Transaction Error Interrupt Clear 10 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only HBISOFLUSHEC High Bandwidth Isochronous IN Flush Interrupt Clear 4 1 write-only HBISOINERREC High Bandwidth Isochronous IN Error Interrupt Clear 3 1 write-only MDATEC MData Interrupt Clear 8 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only UNDERFEC Underflow Interrupt Clear 2 1 write-only DEVEPTIDR1 Device Endpoint Disable Register (n = 0) 0x224 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR2 Device Endpoint Disable Register (n = 0) 0x228 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR3 Device Endpoint Disable Register (n = 0) 0x22C 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR4 Device Endpoint Disable Register (n = 0) 0x230 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR5 Device Endpoint Disable Register (n = 0) 0x234 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR6 Device Endpoint Disable Register (n = 0) 0x238 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR7 Device Endpoint Disable Register (n = 0) 0x23C 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR8 Device Endpoint Disable Register (n = 0) 0x240 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR9 Device Endpoint Disable Register (n = 0) 0x244 32 write-only n EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 write-only FIFOCONC FIFO Control Clear 14 1 write-only NAKINEC NAKed IN Interrupt Clear 4 1 write-only NAKOUTEC NAKed OUT Interrupt Clear 3 1 write-only NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 write-only NYETDISC NYET Token Disable Clear 17 1 write-only OVERFEC Overflow Interrupt Clear 5 1 write-only RXOUTEC Received OUT Data Interrupt Clear 1 1 write-only RXSTPEC Received SETUP Interrupt Clear 2 1 write-only SHORTPACKETEC Shortpacket Interrupt Clear 7 1 write-only STALLEDEC STALLed Interrupt Clear 6 1 write-only STALLRQC STALL Request Clear 19 1 write-only TXINEC Transmitted IN Interrupt Clear 0 1 write-only DEVEPTIDR[0] Device Endpoint Disable Register (n = 0) 0 0x440 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[1] Device Endpoint Disable Register (n = 0) 0 0x664 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[2] Device Endpoint Disable Register (n = 0) 0 0x88C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[3] Device Endpoint Disable Register (n = 0) 0 0xAB8 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[4] Device Endpoint Disable Register (n = 0) 0 0xCE8 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[5] Device Endpoint Disable Register (n = 0) 0 0xF1C 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[6] Device Endpoint Disable Register (n = 0) 0 0x1154 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[7] Device Endpoint Disable Register (n = 0) 0 0x1390 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[8] Device Endpoint Disable Register (n = 0) 0 0x15D0 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIDR[9] Device Endpoint Disable Register (n = 0) 0 0x1814 32 write-only n 0x0 0x0 EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear 16 1 FIFOCONC FIFO Control Clear 14 1 NAKINEC NAKed IN Interrupt Clear 4 1 NAKOUTEC NAKed OUT Interrupt Clear 3 1 NBUSYBKEC Number of Busy Banks Interrupt Clear 12 1 NYETDISC NYET Token Disable Clear 17 1 OVERFEC Overflow Interrupt Clear 5 1 RXOUTEC Received OUT Data Interrupt Clear 1 1 RXSTPEC Received SETUP Interrupt Clear 2 1 SHORTPACKETEC Shortpacket Interrupt Clear 7 1 STALLEDEC STALLed Interrupt Clear 6 1 STALLRQC STALL Request Clear 19 1 TXINEC Transmitted IN Interrupt Clear 0 1 DEVEPTIER0 Device Endpoint Enable Register (n = 0) 0x1F0 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER0_ISOENPT Device Endpoint Enable Register (n = 0) 0x1F0 32 write-only n CRCERRES CRC Error Interrupt Enable 6 1 write-only DATAXES DataX Interrupt Enable 9 1 write-only EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only ERRORTRANSES Transaction Error Interrupt Enable 10 1 write-only FIFOCONS FIFO Control 14 1 write-only HBISOFLUSHES High Bandwidth Isochronous IN Flush Interrupt Enable 4 1 write-only HBISOINERRES High Bandwidth Isochronous IN Error Interrupt Enable 3 1 write-only KILLBKS Kill IN Bank 13 1 write-only MDATAES MData Interrupt Enable 8 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only UNDERFES Underflow Interrupt Enable 2 1 write-only DEVEPTIER1 Device Endpoint Enable Register (n = 0) 0x1F4 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER2 Device Endpoint Enable Register (n = 0) 0x1F8 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER3 Device Endpoint Enable Register (n = 0) 0x1FC 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER4 Device Endpoint Enable Register (n = 0) 0x200 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER5 Device Endpoint Enable Register (n = 0) 0x204 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER6 Device Endpoint Enable Register (n = 0) 0x208 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER7 Device Endpoint Enable Register (n = 0) 0x20C 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER8 Device Endpoint Enable Register (n = 0) 0x210 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER9 Device Endpoint Enable Register (n = 0) 0x214 32 write-only n EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 write-only FIFOCONS FIFO Control 14 1 write-only KILLBKS Kill IN Bank 13 1 write-only NAKINES NAKed IN Interrupt Enable 4 1 write-only NAKOUTES NAKed OUT Interrupt Enable 3 1 write-only NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 write-only NYETDISS NYET Token Disable Enable 17 1 write-only OVERFES Overflow Interrupt Enable 5 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXOUTES Received OUT Data Interrupt Enable 1 1 write-only RXSTPES Received SETUP Interrupt Enable 2 1 write-only SHORTPACKETES Short Packet Interrupt Enable 7 1 write-only STALLEDES STALLed Interrupt Enable 6 1 write-only STALLRQS STALL Request Enable 19 1 write-only TXINES Transmitted IN Data Interrupt Enable 0 1 write-only DEVEPTIER[0] Device Endpoint Enable Register (n = 0) 0 0x3E0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[1] Device Endpoint Enable Register (n = 0) 0 0x5D4 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[2] Device Endpoint Enable Register (n = 0) 0 0x7CC 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[3] Device Endpoint Enable Register (n = 0) 0 0x9C8 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[4] Device Endpoint Enable Register (n = 0) 0 0xBC8 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[5] Device Endpoint Enable Register (n = 0) 0 0xDCC 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[6] Device Endpoint Enable Register (n = 0) 0 0xFD4 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[7] Device Endpoint Enable Register (n = 0) 0 0x11E0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[8] Device Endpoint Enable Register (n = 0) 0 0x13F0 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIER[9] Device Endpoint Enable Register (n = 0) 0 0x1604 32 write-only n 0x0 0x0 EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable 16 1 FIFOCONS FIFO Control 14 1 KILLBKS Kill IN Bank 13 1 NAKINES NAKed IN Interrupt Enable 4 1 NAKOUTES NAKed OUT Interrupt Enable 3 1 NBUSYBKES Number of Busy Banks Interrupt Enable 12 1 NYETDISS NYET Token Disable Enable 17 1 OVERFES Overflow Interrupt Enable 5 1 RSTDTS Reset Data Toggle Enable 18 1 RXOUTES Received OUT Data Interrupt Enable 1 1 RXSTPES Received SETUP Interrupt Enable 2 1 SHORTPACKETES Short Packet Interrupt Enable 7 1 STALLEDES STALLed Interrupt Enable 6 1 STALLRQS STALL Request Enable 19 1 TXINES Transmitted IN Data Interrupt Enable 0 1 DEVEPTIFR0 Device Endpoint Set Register (n = 0) 0x190 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR0_ISOENPT Device Endpoint Set Register (n = 0) 0x190 32 write-only n CRCERRIS CRC Error Interrupt Set 6 1 write-only HBISOFLUSHIS High Bandwidth Isochronous IN Flush Interrupt Set 4 1 write-only HBISOINERRIS High Bandwidth Isochronous IN Underflow Error Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only DEVEPTIFR1 Device Endpoint Set Register (n = 0) 0x194 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR2 Device Endpoint Set Register (n = 0) 0x198 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR3 Device Endpoint Set Register (n = 0) 0x19C 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR4 Device Endpoint Set Register (n = 0) 0x1A0 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR5 Device Endpoint Set Register (n = 0) 0x1A4 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR6 Device Endpoint Set Register (n = 0) 0x1A8 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR7 Device Endpoint Set Register (n = 0) 0x1AC 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR8 Device Endpoint Set Register (n = 0) 0x1B0 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR9 Device Endpoint Set Register (n = 0) 0x1B4 32 write-only n NAKINIS NAKed IN Interrupt Set 4 1 write-only NAKOUTIS NAKed OUT Interrupt Set 3 1 write-only NBUSYBKS Number of Busy Banks Interrupt Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only RXOUTIS Received OUT Data Interrupt Set 1 1 write-only RXSTPIS Received SETUP Interrupt Set 2 1 write-only SHORTPACKETS Short Packet Interrupt Set 7 1 write-only STALLEDIS STALLed Interrupt Set 6 1 write-only TXINIS Transmitted IN Data Interrupt Set 0 1 write-only DEVEPTIFR[0] Device Endpoint Set Register (n = 0) 0 0x320 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[1] Device Endpoint Set Register (n = 0) 0 0x4B4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[2] Device Endpoint Set Register (n = 0) 0 0x64C 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[3] Device Endpoint Set Register (n = 0) 0 0x7E8 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[4] Device Endpoint Set Register (n = 0) 0 0x988 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[5] Device Endpoint Set Register (n = 0) 0 0xB2C 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[6] Device Endpoint Set Register (n = 0) 0 0xCD4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[7] Device Endpoint Set Register (n = 0) 0 0xE80 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[8] Device Endpoint Set Register (n = 0) 0 0x1030 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIFR[9] Device Endpoint Set Register (n = 0) 0 0x11E4 32 write-only n 0x0 0x0 NAKINIS NAKed IN Interrupt Set 4 1 NAKOUTIS NAKed OUT Interrupt Set 3 1 NBUSYBKS Number of Busy Banks Interrupt Set 12 1 OVERFIS Overflow Interrupt Set 5 1 RXOUTIS Received OUT Data Interrupt Set 1 1 RXSTPIS Received SETUP Interrupt Set 2 1 SHORTPACKETS Short Packet Interrupt Set 7 1 STALLEDIS STALLed Interrupt Set 6 1 TXINIS Transmitted IN Data Interrupt Set 0 1 DEVEPTIMR0 Device Endpoint Mask Register (n = 0) 0x1C0 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR0_ISOENPT Device Endpoint Mask Register (n = 0) 0x1C0 32 read-only n CRCERRE CRC Error Interrupt 6 1 read-only DATAXE DataX Interrupt 9 1 read-only EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only ERRORTRANSE Transaction Error Interrupt 10 1 read-only FIFOCON FIFO Control 14 1 read-only HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt 4 1 read-only HBISOINERRE High Bandwidth Isochronous IN Error Interrupt 3 1 read-only KILLBK Kill IN Bank 13 1 read-only MDATAE MData Interrupt 8 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only UNDERFE Underflow Interrupt 2 1 read-only DEVEPTIMR1 Device Endpoint Mask Register (n = 0) 0x1C4 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR2 Device Endpoint Mask Register (n = 0) 0x1C8 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR3 Device Endpoint Mask Register (n = 0) 0x1CC 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR4 Device Endpoint Mask Register (n = 0) 0x1D0 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR5 Device Endpoint Mask Register (n = 0) 0x1D4 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR6 Device Endpoint Mask Register (n = 0) 0x1D8 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR7 Device Endpoint Mask Register (n = 0) 0x1DC 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR8 Device Endpoint Mask Register (n = 0) 0x1E0 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR9 Device Endpoint Mask Register (n = 0) 0x1E4 32 read-only n EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 read-only FIFOCON FIFO Control 14 1 read-only KILLBK Kill IN Bank 13 1 read-only NAKINE NAKed IN Interrupt 4 1 read-only NAKOUTE NAKed OUT Interrupt 3 1 read-only NBUSYBKE Number of Busy Banks Interrupt 12 1 read-only NYETDIS NYET Token Disable 17 1 read-only OVERFE Overflow Interrupt 5 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXOUTE Received OUT Data Interrupt 1 1 read-only RXSTPE Received SETUP Interrupt 2 1 read-only SHORTPACKETE Short Packet Interrupt 7 1 read-only STALLEDE STALLed Interrupt 6 1 read-only STALLRQ STALL Request 19 1 read-only TXINE Transmitted IN Data Interrupt 0 1 read-only DEVEPTIMR[0] Device Endpoint Mask Register (n = 0) 0 0x380 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[1] Device Endpoint Mask Register (n = 0) 0 0x544 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[2] Device Endpoint Mask Register (n = 0) 0 0x70C 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[3] Device Endpoint Mask Register (n = 0) 0 0x8D8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[4] Device Endpoint Mask Register (n = 0) 0 0xAA8 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[5] Device Endpoint Mask Register (n = 0) 0 0xC7C 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[6] Device Endpoint Mask Register (n = 0) 0 0xE54 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[7] Device Endpoint Mask Register (n = 0) 0 0x1030 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[8] Device Endpoint Mask Register (n = 0) 0 0x1210 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTIMR[9] Device Endpoint Mask Register (n = 0) 0 0x13F4 32 read-only n 0x0 0x0 EPDISHDMA Endpoint Interrupts Disable HDMA Request 16 1 FIFOCON FIFO Control 14 1 KILLBK Kill IN Bank 13 1 NAKINE NAKed IN Interrupt 4 1 NAKOUTE NAKed OUT Interrupt 3 1 NBUSYBKE Number of Busy Banks Interrupt 12 1 NYETDIS NYET Token Disable 17 1 OVERFE Overflow Interrupt 5 1 RSTDT Reset Data Toggle 18 1 RXOUTE Received OUT Data Interrupt 1 1 RXSTPE Received SETUP Interrupt 2 1 SHORTPACKETE Short Packet Interrupt 7 1 STALLEDE STALLed Interrupt 6 1 STALLRQ STALL Request 19 1 TXINE Transmitted IN Data Interrupt 0 1 DEVEPTISR0 Device Endpoint Status Register (n = 0) 0x130 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR0_ISOENPT Device Endpoint Status Register (n = 0) 0x130 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CRCERRI CRC Error Interrupt 6 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Data2 toggle sequence (for high-bandwidth isochronous endpoint) 0x2 MDATA MData toggle sequence (for high-bandwidth isochronous endpoint) 0x3 ERRORTRANS High-bandwidth Isochronous OUT Endpoint Transaction Error Interrupt 10 1 read-only HBISOFLUSHI High Bandwidth Isochronous IN Flush Interrupt 4 1 read-only HBISOINERRI High Bandwidth Isochronous IN Underflow Error Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only UNDERFI Underflow Interrupt 2 1 read-only DEVEPTISR1 Device Endpoint Status Register (n = 0) 0x134 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR2 Device Endpoint Status Register (n = 0) 0x138 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR3 Device Endpoint Status Register (n = 0) 0x13C 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR4 Device Endpoint Status Register (n = 0) 0x140 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR5 Device Endpoint Status Register (n = 0) 0x144 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR6 Device Endpoint Status Register (n = 0) 0x148 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR7 Device Endpoint Status Register (n = 0) 0x14C 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR8 Device Endpoint Status Register (n = 0) 0x150 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR9 Device Endpoint Status Register (n = 0) 0x154 32 read-only n BYCT Byte Count 20 11 read-only CFGOK Configuration OK Status 18 1 read-only CTRLDIR Control Direction 17 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0x0 DATA1 Data1 toggle sequence 0x1 DATA2 Reserved for high-bandwidth isochronous endpoint 0x2 MDATA Reserved for high-bandwidth isochronous endpoint 0x3 NAKINI NAKed IN Interrupt 4 1 read-only NAKOUTI NAKed OUT Interrupt 3 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only RWALL Read/Write Allowed 16 1 read-only RXOUTI Received OUT Data Interrupt 1 1 read-only RXSTPI Received SETUP Interrupt 2 1 read-only SHORTPACKET Short Packet Interrupt 7 1 read-only STALLEDI STALLed Interrupt 6 1 read-only TXINI Transmitted IN Data Interrupt 0 1 read-only DEVEPTISR[0] Device Endpoint Status Register (n = 0) 0 0x260 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[1] Device Endpoint Status Register (n = 0) 0 0x394 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[2] Device Endpoint Status Register (n = 0) 0 0x4CC 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[3] Device Endpoint Status Register (n = 0) 0 0x608 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[4] Device Endpoint Status Register (n = 0) 0 0x748 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[5] Device Endpoint Status Register (n = 0) 0 0x88C 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[6] Device Endpoint Status Register (n = 0) 0 0x9D4 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[7] Device Endpoint Status Register (n = 0) 0 0xB20 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[8] Device Endpoint Status Register (n = 0) 0 0xC70 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVEPTISR[9] Device Endpoint Status Register (n = 0) 0 0xDC4 32 read-only n 0x0 0x0 BYCT Byte Count 20 11 CFGOK Configuration OK Status 18 1 CTRLDIR Control Direction 17 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 DATA2 Reserved for high-bandwidth isochronous endpoint 2 MDATA Reserved for high-bandwidth isochronous endpoint 3 NAKINI NAKed IN Interrupt 4 1 NAKOUTI NAKed OUT Interrupt 3 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 RWALL Read/Write Allowed 16 1 RXOUTI Received OUT Data Interrupt 1 1 RXSTPI Received SETUP Interrupt 2 1 SHORTPACKET Short Packet Interrupt 7 1 STALLEDI STALLed Interrupt 6 1 TXINI Transmitted IN Data Interrupt 0 1 DEVFNUM Device Frame Number Register 0x20 32 read-only n 0x0 0x0 FNCERR Frame Number CRC Error 15 1 FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 DEVICR Device Global Interrupt Clear Register 0x8 32 write-only n 0x0 0x0 EORSMC End of Resume Interrupt Clear 5 1 EORSTC End of Reset Interrupt Clear 3 1 MSOFC Micro Start of Frame Interrupt Clear 1 1 SOFC Start of Frame Interrupt Clear 2 1 SUSPC Suspend Interrupt Clear 0 1 UPRSMC Upstream Resume Interrupt Clear 6 1 WAKEUPC Wake-Up Interrupt Clear 4 1 DEVIDR Device Global Interrupt Disable Register 0x14 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Disable 25 1 DMA_2 DMA Channel 2 Interrupt Disable 26 1 DMA_3 DMA Channel 3 Interrupt Disable 27 1 DMA_4 DMA Channel 4 Interrupt Disable 28 1 DMA_5 DMA Channel 5 Interrupt Disable 29 1 DMA_6 DMA Channel 6 Interrupt Disable 30 1 DMA_7 DMA Channel 7 Interrupt Disable 31 1 EORSMEC End of Resume Interrupt Disable 5 1 EORSTEC End of Reset Interrupt Disable 3 1 MSOFEC Micro Start of Frame Interrupt Disable 1 1 PEP_0 Endpoint 0 Interrupt Disable 12 1 PEP_1 Endpoint 1 Interrupt Disable 13 1 PEP_10 Endpoint 10 Interrupt Disable 22 1 PEP_11 Endpoint 11 Interrupt Disable 23 1 PEP_2 Endpoint 2 Interrupt Disable 14 1 PEP_3 Endpoint 3 Interrupt Disable 15 1 PEP_4 Endpoint 4 Interrupt Disable 16 1 PEP_5 Endpoint 5 Interrupt Disable 17 1 PEP_6 Endpoint 6 Interrupt Disable 18 1 PEP_7 Endpoint 7 Interrupt Disable 19 1 PEP_8 Endpoint 8 Interrupt Disable 20 1 PEP_9 Endpoint 9 Interrupt Disable 21 1 SOFEC Start of Frame Interrupt Disable 2 1 SUSPEC Suspend Interrupt Disable 0 1 UPRSMEC Upstream Resume Interrupt Disable 6 1 WAKEUPEC Wake-Up Interrupt Disable 4 1 DEVIER Device Global Interrupt Enable Register 0x18 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Enable 25 1 DMA_2 DMA Channel 2 Interrupt Enable 26 1 DMA_3 DMA Channel 3 Interrupt Enable 27 1 DMA_4 DMA Channel 4 Interrupt Enable 28 1 DMA_5 DMA Channel 5 Interrupt Enable 29 1 DMA_6 DMA Channel 6 Interrupt Enable 30 1 DMA_7 DMA Channel 7 Interrupt Enable 31 1 EORSMES End of Resume Interrupt Enable 5 1 EORSTES End of Reset Interrupt Enable 3 1 MSOFES Micro Start of Frame Interrupt Enable 1 1 PEP_0 Endpoint 0 Interrupt Enable 12 1 PEP_1 Endpoint 1 Interrupt Enable 13 1 PEP_10 Endpoint 10 Interrupt Enable 22 1 PEP_11 Endpoint 11 Interrupt Enable 23 1 PEP_2 Endpoint 2 Interrupt Enable 14 1 PEP_3 Endpoint 3 Interrupt Enable 15 1 PEP_4 Endpoint 4 Interrupt Enable 16 1 PEP_5 Endpoint 5 Interrupt Enable 17 1 PEP_6 Endpoint 6 Interrupt Enable 18 1 PEP_7 Endpoint 7 Interrupt Enable 19 1 PEP_8 Endpoint 8 Interrupt Enable 20 1 PEP_9 Endpoint 9 Interrupt Enable 21 1 SOFES Start of Frame Interrupt Enable 2 1 SUSPES Suspend Interrupt Enable 0 1 UPRSMES Upstream Resume Interrupt Enable 6 1 WAKEUPES Wake-Up Interrupt Enable 4 1 DEVIFR Device Global Interrupt Set Register 0xC 32 write-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Set 25 1 DMA_2 DMA Channel 2 Interrupt Set 26 1 DMA_3 DMA Channel 3 Interrupt Set 27 1 DMA_4 DMA Channel 4 Interrupt Set 28 1 DMA_5 DMA Channel 5 Interrupt Set 29 1 DMA_6 DMA Channel 6 Interrupt Set 30 1 DMA_7 DMA Channel 7 Interrupt Set 31 1 EORSMS End of Resume Interrupt Set 5 1 EORSTS End of Reset Interrupt Set 3 1 MSOFS Micro Start of Frame Interrupt Set 1 1 SOFS Start of Frame Interrupt Set 2 1 SUSPS Suspend Interrupt Set 0 1 UPRSMS Upstream Resume Interrupt Set 6 1 WAKEUPS Wake-Up Interrupt Set 4 1 DEVIMR Device Global Interrupt Mask Register 0x10 32 read-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt Mask 25 1 DMA_2 DMA Channel 2 Interrupt Mask 26 1 DMA_3 DMA Channel 3 Interrupt Mask 27 1 DMA_4 DMA Channel 4 Interrupt Mask 28 1 DMA_5 DMA Channel 5 Interrupt Mask 29 1 DMA_6 DMA Channel 6 Interrupt Mask 30 1 DMA_7 DMA Channel 7 Interrupt Mask 31 1 EORSME End of Resume Interrupt Mask 5 1 EORSTE End of Reset Interrupt Mask 3 1 MSOFE Micro Start of Frame Interrupt Mask 1 1 PEP_0 Endpoint 0 Interrupt Mask 12 1 PEP_1 Endpoint 1 Interrupt Mask 13 1 PEP_10 Endpoint 10 Interrupt Mask 22 1 PEP_11 Endpoint 11 Interrupt Mask 23 1 PEP_2 Endpoint 2 Interrupt Mask 14 1 PEP_3 Endpoint 3 Interrupt Mask 15 1 PEP_4 Endpoint 4 Interrupt Mask 16 1 PEP_5 Endpoint 5 Interrupt Mask 17 1 PEP_6 Endpoint 6 Interrupt Mask 18 1 PEP_7 Endpoint 7 Interrupt Mask 19 1 PEP_8 Endpoint 8 Interrupt Mask 20 1 PEP_9 Endpoint 9 Interrupt Mask 21 1 SOFE Start of Frame Interrupt Mask 2 1 SUSPE Suspend Interrupt Mask 0 1 UPRSME Upstream Resume Interrupt Mask 6 1 WAKEUPE Wake-Up Interrupt Mask 4 1 DEVISR Device Global Interrupt Status Register 0x4 32 read-only n 0x0 0x0 DMA_1 DMA Channel 1 Interrupt 25 1 DMA_2 DMA Channel 2 Interrupt 26 1 DMA_3 DMA Channel 3 Interrupt 27 1 DMA_4 DMA Channel 4 Interrupt 28 1 DMA_5 DMA Channel 5 Interrupt 29 1 DMA_6 DMA Channel 6 Interrupt 30 1 DMA_7 DMA Channel 7 Interrupt 31 1 EORSM End of Resume Interrupt 5 1 EORST End of Reset Interrupt 3 1 MSOF Micro Start of Frame Interrupt 1 1 PEP_0 Endpoint 0 Interrupt 12 1 PEP_1 Endpoint 1 Interrupt 13 1 PEP_10 Endpoint 10 Interrupt 22 1 PEP_11 Endpoint 11 Interrupt 23 1 PEP_2 Endpoint 2 Interrupt 14 1 PEP_3 Endpoint 3 Interrupt 15 1 PEP_4 Endpoint 4 Interrupt 16 1 PEP_5 Endpoint 5 Interrupt 17 1 PEP_6 Endpoint 6 Interrupt 18 1 PEP_7 Endpoint 7 Interrupt 19 1 PEP_8 Endpoint 8 Interrupt 20 1 PEP_9 Endpoint 9 Interrupt 21 1 SOF Start of Frame Interrupt 2 1 SUSP Suspend Interrupt 0 1 UPRSM Upstream Resume Interrupt 6 1 WAKEUP Wake-Up Interrupt 4 1 HSTADDR1 Host Address 1 Register 0x424 32 read-write n 0x0 0x0 HSTADDRP0 USB Host Address 0 7 HSTADDRP1 USB Host Address 8 7 HSTADDRP2 USB Host Address 16 7 HSTADDRP3 USB Host Address 24 7 HSTADDR2 Host Address 2 Register 0x428 32 read-write n 0x0 0x0 HSTADDRP4 USB Host Address 0 7 HSTADDRP5 USB Host Address 8 7 HSTADDRP6 USB Host Address 16 7 HSTADDRP7 USB Host Address 24 7 HSTADDR3 Host Address 3 Register 0x42C 32 read-write n 0x0 0x0 HSTADDRP8 USB Host Address 0 7 HSTADDRP9 USB Host Address 8 7 HSTCTRL Host General Control Register 0x400 32 read-write n 0x0 0x0 RESET Send USB Reset 9 1 RESUME Send USB Resume 10 1 SOFE Start of Frame Generation Enable 8 1 SPDCONF Mode Configuration 12 2 SPDCONFSelect NORMAL The host starts in Full-speed mode and performs a high-speed reset to switch to High-speed mode if the downstream peripheral is high-speed capable. 0 LOW_POWER For a better consumption, if high speed is not needed. 1 HSTDMAADDRESS1 Host DMA Channel Address Register (n = 1) 0x714 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS2 Host DMA Channel Address Register (n = 2) 0x724 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS3 Host DMA Channel Address Register (n = 3) 0x734 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS4 Host DMA Channel Address Register (n = 4) 0x744 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS5 Host DMA Channel Address Register (n = 5) 0x754 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS6 Host DMA Channel Address Register (n = 6) 0x764 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMAADDRESS7 Host DMA Channel Address Register (n = 7) 0x774 32 read-write n 0x0 BUFF_ADD Buffer Address 0 32 read-write HSTDMACONTROL1 Host DMA Channel Control Register (n = 1) 0x718 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL2 Host DMA Channel Control Register (n = 2) 0x728 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL3 Host DMA Channel Control Register (n = 3) 0x738 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL4 Host DMA Channel Control Register (n = 4) 0x748 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL5 Host DMA Channel Control Register (n = 5) 0x758 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL6 Host DMA Channel Control Register (n = 6) 0x768 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMACONTROL7 Host DMA Channel Control Register (n = 7) 0x778 32 read-write n 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 read-write BURST_LCK Burst Lock Enable 7 1 read-write CHANN_ENB Channel Enable Command 0 1 read-write DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 read-write END_BUFFIT End of Buffer Interrupt Enable 5 1 read-write END_B_EN End of Buffer Enable Control 3 1 read-write END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 read-write END_TR_IT End of Transfer Interrupt Enable 4 1 read-write LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 read-write HSTDMANXTDSC1 Host DMA Channel Next Descriptor Address Register (n = 1) 0x710 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC2 Host DMA Channel Next Descriptor Address Register (n = 2) 0x720 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC3 Host DMA Channel Next Descriptor Address Register (n = 3) 0x730 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC4 Host DMA Channel Next Descriptor Address Register (n = 4) 0x740 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC5 Host DMA Channel Next Descriptor Address Register (n = 5) 0x750 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC6 Host DMA Channel Next Descriptor Address Register (n = 6) 0x760 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMANXTDSC7 Host DMA Channel Next Descriptor Address Register (n = 7) 0x770 32 read-write n 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 read-write HSTDMASTATUS1 Host DMA Channel Status Register (n = 1) 0x71C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS2 Host DMA Channel Status Register (n = 2) 0x72C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS3 Host DMA Channel Status Register (n = 3) 0x73C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS4 Host DMA Channel Status Register (n = 4) 0x74C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS5 Host DMA Channel Status Register (n = 5) 0x75C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS6 Host DMA Channel Status Register (n = 6) 0x76C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMASTATUS7 Host DMA Channel Status Register (n = 7) 0x77C 32 read-write n 0x0 BUFF_COUNT Buffer Byte Count 16 16 read-write CHANN_ACT Channel Active Status 1 1 read-write CHANN_ENB Channel Enable Status 0 1 read-write DESC_LDST Descriptor Loaded Status 6 1 read-write END_BF_ST End of Channel Buffer Status 5 1 read-write END_TR_ST End of Channel Transfer Status 4 1 read-write HSTDMA[0]-USBHS_HSTDMAADDRESS Host DMA Channel Address Register (n = 1) 0x714 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 HSTDMA[0]-USBHS_HSTDMACONTROL Host DMA Channel Control Register (n = 1) 0x718 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 HSTDMA[0]-USBHS_HSTDMANXTDSC Host DMA Channel Next Descriptor Address Register (n = 1) 0x710 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 HSTDMA[0]-USBHS_HSTDMASTATUS Host DMA Channel Status Register (n = 1) 0x71C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMAADDRESS Host DMA Channel Address Register (n = 1) 0xE34 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMACONTROL Host DMA Channel Control Register (n = 1) 0xE38 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMANXTDSC Host DMA Channel Next Descriptor Address Register (n = 1) 0xE30 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMASTATUS Host DMA Channel Status Register (n = 1) 0xE3C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMAADDRESS Host DMA Channel Address Register (n = 1) 0x1564 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMACONTROL Host DMA Channel Control Register (n = 1) 0x1568 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMANXTDSC Host DMA Channel Next Descriptor Address Register (n = 1) 0x1560 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMASTATUS Host DMA Channel Status Register (n = 1) 0x156C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMAADDRESS Host DMA Channel Address Register (n = 1) 0x1CA4 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMACONTROL Host DMA Channel Control Register (n = 1) 0x1CA8 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMANXTDSC Host DMA Channel Next Descriptor Address Register (n = 1) 0x1CA0 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMASTATUS Host DMA Channel Status Register (n = 1) 0x1CAC 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMAADDRESS Host DMA Channel Address Register (n = 1) 0x23F4 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMACONTROL Host DMA Channel Control Register (n = 1) 0x23F8 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMANXTDSC Host DMA Channel Next Descriptor Address Register (n = 1) 0x23F0 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMASTATUS Host DMA Channel Status Register (n = 1) 0x23FC 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 HSTDMA[5]-USBHS_HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMAADDRESS Host DMA Channel Address Register (n = 1) 0x2B54 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 HSTDMA[5]-USBHS_HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMACONTROL Host DMA Channel Control Register (n = 1) 0x2B58 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 HSTDMA[5]-USBHS_HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMANXTDSC Host DMA Channel Next Descriptor Address Register (n = 1) 0x2B50 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 HSTDMA[5]-USBHS_HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMASTATUS Host DMA Channel Status Register (n = 1) 0x2B5C 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 HSTDMA[6]-USBHS_HSTDMA[5]-USBHS_HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMAADDRESS Host DMA Channel Address Register (n = 1) 0x32C4 32 read-write n 0x0 0x0 BUFF_ADD Buffer Address 0 32 HSTDMA[6]-USBHS_HSTDMA[5]-USBHS_HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMACONTROL Host DMA Channel Control Register (n = 1) 0x32C8 32 read-write n 0x0 0x0 BUFF_LENGTH Buffer Byte Length (Write-only) 16 16 BURST_LCK Burst Lock Enable 7 1 CHANN_ENB Channel Enable Command 0 1 DESC_LD_IT Descriptor Loaded Interrupt Enable 6 1 END_BUFFIT End of Buffer Interrupt Enable 5 1 END_B_EN End of Buffer Enable Control 3 1 END_TR_EN End of Transfer Enable Control (OUT transfers only) 2 1 END_TR_IT End of Transfer Interrupt Enable 4 1 LDNXT_DSC Load Next Channel Transfer Descriptor Enable Command 1 1 HSTDMA[6]-USBHS_HSTDMA[5]-USBHS_HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMANXTDSC Host DMA Channel Next Descriptor Address Register (n = 1) 0x32C0 32 read-write n 0x0 0x0 NXT_DSC_ADD Next Descriptor Address 0 32 HSTDMA[6]-USBHS_HSTDMA[5]-USBHS_HSTDMA[4]-USBHS_HSTDMA[3]-USBHS_HSTDMA[2]-USBHS_HSTDMA[1]-USBHS_HSTDMA[0]-USBHS_HSTDMASTATUS Host DMA Channel Status Register (n = 1) 0x32CC 32 read-write n 0x0 0x0 BUFF_COUNT Buffer Byte Count 16 16 CHANN_ACT Channel Active Status 1 1 CHANN_ENB Channel Enable Status 0 1 DESC_LDST Descriptor Loaded Status 6 1 END_BF_ST End of Channel Buffer Status 5 1 END_TR_ST End of Channel Transfer Status 4 1 HSTFNUM Host Frame Number Register 0x420 32 read-write n 0x0 0x0 FLENHIGH Frame Length 16 8 FNUM Frame Number 3 11 MFNUM Micro Frame Number 0 3 HSTICR Host Global Interrupt Clear Register 0x408 32 write-only n 0x0 0x0 DCONNIC Device Connection Interrupt Clear 0 1 DDISCIC Device Disconnection Interrupt Clear 1 1 HSOFIC Host Start of Frame Interrupt Clear 5 1 HWUPIC Host Wake-Up Interrupt Clear 6 1 RSMEDIC Downstream Resume Sent Interrupt Clear 3 1 RSTIC USB Reset Sent Interrupt Clear 2 1 RXRSMIC Upstream Resume Received Interrupt Clear 4 1 HSTIDR Host Global Interrupt Disable Register 0x414 32 write-only n 0x0 0x0 DCONNIEC Device Connection Interrupt Disable 0 1 DDISCIEC Device Disconnection Interrupt Disable 1 1 DMA_1 DMA Channel 1 Interrupt Disable 25 1 DMA_2 DMA Channel 2 Interrupt Disable 26 1 DMA_3 DMA Channel 3 Interrupt Disable 27 1 DMA_4 DMA Channel 4 Interrupt Disable 28 1 DMA_5 DMA Channel 5 Interrupt Disable 29 1 DMA_6 DMA Channel 6 Interrupt Disable 30 1 DMA_7 DMA Channel 7 Interrupt Disable 31 1 HSOFIEC Host Start of Frame Interrupt Disable 5 1 HWUPIEC Host Wake-Up Interrupt Disable 6 1 PEP_0 Pipe 0 Interrupt Disable 8 1 PEP_1 Pipe 1 Interrupt Disable 9 1 PEP_10 Pipe 10 Interrupt Disable 18 1 PEP_11 Pipe 11 Interrupt Disable 19 1 PEP_2 Pipe 2 Interrupt Disable 10 1 PEP_3 Pipe 3 Interrupt Disable 11 1 PEP_4 Pipe 4 Interrupt Disable 12 1 PEP_5 Pipe 5 Interrupt Disable 13 1 PEP_6 Pipe 6 Interrupt Disable 14 1 PEP_7 Pipe 7 Interrupt Disable 15 1 PEP_8 Pipe 8 Interrupt Disable 16 1 PEP_9 Pipe 9 Interrupt Disable 17 1 RSMEDIEC Downstream Resume Sent Interrupt Disable 3 1 RSTIEC USB Reset Sent Interrupt Disable 2 1 RXRSMIEC Upstream Resume Received Interrupt Disable 4 1 HSTIER Host Global Interrupt Enable Register 0x418 32 write-only n 0x0 0x0 DCONNIES Device Connection Interrupt Enable 0 1 DDISCIES Device Disconnection Interrupt Enable 1 1 DMA_1 DMA Channel 1 Interrupt Enable 25 1 DMA_2 DMA Channel 2 Interrupt Enable 26 1 DMA_3 DMA Channel 3 Interrupt Enable 27 1 DMA_4 DMA Channel 4 Interrupt Enable 28 1 DMA_5 DMA Channel 5 Interrupt Enable 29 1 DMA_6 DMA Channel 6 Interrupt Enable 30 1 DMA_7 DMA Channel 7 Interrupt Enable 31 1 HSOFIES Host Start of Frame Interrupt Enable 5 1 HWUPIES Host Wake-Up Interrupt Enable 6 1 PEP_0 Pipe 0 Interrupt Enable 8 1 PEP_1 Pipe 1 Interrupt Enable 9 1 PEP_10 Pipe 10 Interrupt Enable 18 1 PEP_11 Pipe 11 Interrupt Enable 19 1 PEP_2 Pipe 2 Interrupt Enable 10 1 PEP_3 Pipe 3 Interrupt Enable 11 1 PEP_4 Pipe 4 Interrupt Enable 12 1 PEP_5 Pipe 5 Interrupt Enable 13 1 PEP_6 Pipe 6 Interrupt Enable 14 1 PEP_7 Pipe 7 Interrupt Enable 15 1 PEP_8 Pipe 8 Interrupt Enable 16 1 PEP_9 Pipe 9 Interrupt Enable 17 1 RSMEDIES Downstream Resume Sent Interrupt Enable 3 1 RSTIES USB Reset Sent Interrupt Enable 2 1 RXRSMIES Upstream Resume Received Interrupt Enable 4 1 HSTIFR Host Global Interrupt Set Register 0x40C 32 write-only n 0x0 0x0 DCONNIS Device Connection Interrupt Set 0 1 DDISCIS Device Disconnection Interrupt Set 1 1 DMA_1 DMA Channel 1 Interrupt Set 25 1 DMA_2 DMA Channel 2 Interrupt Set 26 1 DMA_3 DMA Channel 3 Interrupt Set 27 1 DMA_4 DMA Channel 4 Interrupt Set 28 1 DMA_5 DMA Channel 5 Interrupt Set 29 1 DMA_6 DMA Channel 6 Interrupt Set 30 1 DMA_7 DMA Channel 7 Interrupt Set 31 1 HSOFIS Host Start of Frame Interrupt Set 5 1 HWUPIS Host Wake-Up Interrupt Set 6 1 RSMEDIS Downstream Resume Sent Interrupt Set 3 1 RSTIS USB Reset Sent Interrupt Set 2 1 RXRSMIS Upstream Resume Received Interrupt Set 4 1 HSTIMR Host Global Interrupt Mask Register 0x410 32 read-only n 0x0 0x0 DCONNIE Device Connection Interrupt Enable 0 1 DDISCIE Device Disconnection Interrupt Enable 1 1 DMA_1 DMA Channel 1 Interrupt Enable 25 1 DMA_2 DMA Channel 2 Interrupt Enable 26 1 DMA_3 DMA Channel 3 Interrupt Enable 27 1 DMA_4 DMA Channel 4 Interrupt Enable 28 1 DMA_5 DMA Channel 5 Interrupt Enable 29 1 DMA_6 DMA Channel 6 Interrupt Enable 30 1 DMA_7 DMA Channel 7 Interrupt Enable 31 1 HSOFIE Host Start of Frame Interrupt Enable 5 1 HWUPIE Host Wake-Up Interrupt Enable 6 1 PEP_0 Pipe 0 Interrupt Enable 8 1 PEP_1 Pipe 1 Interrupt Enable 9 1 PEP_10 Pipe 10 Interrupt Enable 18 1 PEP_11 Pipe 11 Interrupt Enable 19 1 PEP_2 Pipe 2 Interrupt Enable 10 1 PEP_3 Pipe 3 Interrupt Enable 11 1 PEP_4 Pipe 4 Interrupt Enable 12 1 PEP_5 Pipe 5 Interrupt Enable 13 1 PEP_6 Pipe 6 Interrupt Enable 14 1 PEP_7 Pipe 7 Interrupt Enable 15 1 PEP_8 Pipe 8 Interrupt Enable 16 1 PEP_9 Pipe 9 Interrupt Enable 17 1 RSMEDIE Downstream Resume Sent Interrupt Enable 3 1 RSTIE USB Reset Sent Interrupt Enable 2 1 RXRSMIE Upstream Resume Received Interrupt Enable 4 1 HSTISR Host Global Interrupt Status Register 0x404 32 read-only n 0x0 0x0 DCONNI Device Connection Interrupt 0 1 DDISCI Device Disconnection Interrupt 1 1 DMA_1 DMA Channel 1 Interrupt 25 1 DMA_2 DMA Channel 2 Interrupt 26 1 DMA_3 DMA Channel 3 Interrupt 27 1 DMA_4 DMA Channel 4 Interrupt 28 1 DMA_5 DMA Channel 5 Interrupt 29 1 DMA_6 DMA Channel 6 Interrupt 30 1 DMA_7 DMA Channel 7 Interrupt 31 1 HSOFI Host Start of Frame Interrupt 5 1 HWUPI Host Wake-Up Interrupt 6 1 PEP_0 Pipe 0 Interrupt 8 1 PEP_1 Pipe 1 Interrupt 9 1 PEP_10 Pipe 10 Interrupt 18 1 PEP_11 Pipe 11 Interrupt 19 1 PEP_2 Pipe 2 Interrupt 10 1 PEP_3 Pipe 3 Interrupt 11 1 PEP_4 Pipe 4 Interrupt 12 1 PEP_5 Pipe 5 Interrupt 13 1 PEP_6 Pipe 6 Interrupt 14 1 PEP_7 Pipe 7 Interrupt 15 1 PEP_8 Pipe 8 Interrupt 16 1 PEP_9 Pipe 9 Interrupt 17 1 RSMEDI Downstream Resume Sent Interrupt 3 1 RSTI USB Reset Sent Interrupt 2 1 RXRSMI Upstream Resume Received Interrupt 4 1 HSTPIP Host Pipe Register 0x41C 32 read-write n 0x0 0x0 PEN0 Pipe 0 Enable 0 1 PEN1 Pipe 1 Enable 1 1 PEN2 Pipe 2 Enable 2 1 PEN3 Pipe 3 Enable 3 1 PEN4 Pipe 4 Enable 4 1 PEN5 Pipe 5 Enable 5 1 PEN6 Pipe 6 Enable 6 1 PEN7 Pipe 7 Enable 7 1 PEN8 Pipe 8 Enable 8 1 PRST0 Pipe 0 Reset 16 1 PRST1 Pipe 1 Reset 17 1 PRST2 Pipe 2 Reset 18 1 PRST3 Pipe 3 Reset 19 1 PRST4 Pipe 4 Reset 20 1 PRST5 Pipe 5 Reset 21 1 PRST6 Pipe 6 Reset 22 1 PRST7 Pipe 7 Reset 23 1 PRST8 Pipe 8 Reset 24 1 HSTPIPCFG0 Host Pipe Configuration Register (n = 0) 0x500 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG0_HSBOHSCP Host Pipe Configuration Register (n = 0) 0x500 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write BINTERVAL Binterval Parameter for the Bulk-Out/Ping Transaction 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PINGEN Ping Enable 20 1 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 BLK Bulk 0x2 HSTPIPCFG1 Host Pipe Configuration Register (n = 0) 0x504 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG2 Host Pipe Configuration Register (n = 0) 0x508 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG3 Host Pipe Configuration Register (n = 0) 0x50C 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG4 Host Pipe Configuration Register (n = 0) 0x510 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG5 Host Pipe Configuration Register (n = 0) 0x514 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG6 Host Pipe Configuration Register (n = 0) 0x518 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG7 Host Pipe Configuration Register (n = 0) 0x51C 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG8 Host Pipe Configuration Register (n = 0) 0x520 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG9 Host Pipe Configuration Register (n = 0) 0x524 32 read-write n ALLOC Pipe Memory Allocate 1 1 read-write AUTOSW Automatic Switch 10 1 read-write INTFRQ Pipe Interrupt Request Frequency 24 8 read-write PBK Pipe Banks 2 2 read-write 1_BANK Single-bank pipe 0x0 2_BANK Double-bank pipe 0x1 3_BANK Triple-bank pipe 0x2 PEPNUM Pipe Endpoint Number 16 4 read-write PSIZE Pipe Size 4 3 read-write 8_BYTE 8 bytes 0x0 16_BYTE 16 bytes 0x1 32_BYTE 32 bytes 0x2 64_BYTE 64 bytes 0x3 128_BYTE 128 bytes 0x4 256_BYTE 256 bytes 0x5 512_BYTE 512 bytes 0x6 1024_BYTE 1024 bytes 0x7 PTOKEN Pipe Token 8 2 read-write SETUP SETUP 0x0 IN IN 0x1 OUT OUT 0x2 PTYPE Pipe Type 12 2 read-write CTRL Control 0x0 ISO Isochronous 0x1 BLK Bulk 0x2 INTRPT Interrupt 0x3 HSTPIPCFG[0] Host Pipe Configuration Register (n = 0) 0 0xA00 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[1] Host Pipe Configuration Register (n = 0) 0 0xF04 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[2] Host Pipe Configuration Register (n = 0) 0 0x140C 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[3] Host Pipe Configuration Register (n = 0) 0 0x1918 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[4] Host Pipe Configuration Register (n = 0) 0 0x1E28 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[5] Host Pipe Configuration Register (n = 0) 0 0x233C 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[6] Host Pipe Configuration Register (n = 0) 0 0x2854 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[7] Host Pipe Configuration Register (n = 0) 0 0x2D70 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[8] Host Pipe Configuration Register (n = 0) 0 0x3290 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPCFG[9] Host Pipe Configuration Register (n = 0) 0 0x37B4 32 read-write n 0x0 0x0 ALLOC Pipe Memory Allocate 1 1 AUTOSW Automatic Switch 10 1 INTFRQ Pipe Interrupt Request Frequency 24 8 PBK Pipe Banks 2 2 PBKSelect _1_BANK Single-bank pipe 0 _2_BANK Double-bank pipe 1 _3_BANK Triple-bank pipe 2 PEPNUM Pipe Endpoint Number 16 4 PSIZE Pipe Size 4 3 PSIZESelect _8_BYTE 8 bytes 0 _16_BYTE 16 bytes 1 _32_BYTE 32 bytes 2 _64_BYTE 64 bytes 3 _128_BYTE 128 bytes 4 _256_BYTE 256 bytes 5 _512_BYTE 512 bytes 6 _1024_BYTE 1024 bytes 7 PTOKEN Pipe Token 8 2 PTOKENSelect SETUP SETUP 0 IN IN 1 OUT OUT 2 PTYPE Pipe Type 12 2 PTYPESelect CTRL Control 0 ISO Isochronous 1 BLK Bulk 2 INTRPT Interrupt 3 HSTPIPERR0 Host Pipe Error Register (n = 0) 0x680 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR1 Host Pipe Error Register (n = 0) 0x684 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR2 Host Pipe Error Register (n = 0) 0x688 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR3 Host Pipe Error Register (n = 0) 0x68C 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR4 Host Pipe Error Register (n = 0) 0x690 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR5 Host Pipe Error Register (n = 0) 0x694 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR6 Host Pipe Error Register (n = 0) 0x698 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR7 Host Pipe Error Register (n = 0) 0x69C 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR8 Host Pipe Error Register (n = 0) 0x6A0 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR9 Host Pipe Error Register (n = 0) 0x6A4 32 read-write n COUNTER Error Counter 5 2 read-write CRC16 CRC16 Error 4 1 read-write DATAPID Data PID Error 1 1 read-write DATATGL Data Toggle Error 0 1 read-write PID Data PID Error 2 1 read-write TIMEOUT Time-Out Error 3 1 read-write HSTPIPERR[0] Host Pipe Error Register (n = 0) 0 0xD00 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[1] Host Pipe Error Register (n = 0) 0 0x1384 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[2] Host Pipe Error Register (n = 0) 0 0x1A0C 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[3] Host Pipe Error Register (n = 0) 0 0x2098 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[4] Host Pipe Error Register (n = 0) 0 0x2728 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[5] Host Pipe Error Register (n = 0) 0 0x2DBC 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[6] Host Pipe Error Register (n = 0) 0 0x3454 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[7] Host Pipe Error Register (n = 0) 0 0x3AF0 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[8] Host Pipe Error Register (n = 0) 0 0x4190 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPERR[9] Host Pipe Error Register (n = 0) 0 0x4834 32 read-write n 0x0 0x0 COUNTER Error Counter 5 2 CRC16 CRC16 Error 4 1 DATAPID Data PID Error 1 1 DATATGL Data Toggle Error 0 1 PID Data PID Error 2 1 TIMEOUT Time-Out Error 3 1 HSTPIPICR0 Host Pipe Clear Register (n = 0) 0x560 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR0_INTPIPES Host Pipe Clear Register (n = 0) 0x560 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only HSTPIPICR0_ISOPIPES Host Pipe Clear Register (n = 0) 0x560 32 write-only n CRCERRIC CRC Error Interrupt Clear 6 1 write-only NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only UNDERFIC Underflow Interrupt Clear 2 1 write-only HSTPIPICR1 Host Pipe Clear Register (n = 0) 0x564 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR2 Host Pipe Clear Register (n = 0) 0x568 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR3 Host Pipe Clear Register (n = 0) 0x56C 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR4 Host Pipe Clear Register (n = 0) 0x570 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR5 Host Pipe Clear Register (n = 0) 0x574 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR6 Host Pipe Clear Register (n = 0) 0x578 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR7 Host Pipe Clear Register (n = 0) 0x57C 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR8 Host Pipe Clear Register (n = 0) 0x580 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR9 Host Pipe Clear Register (n = 0) 0x584 32 write-only n NAKEDIC NAKed Interrupt Clear 4 1 write-only OVERFIC Overflow Interrupt Clear 5 1 write-only RXINIC Received IN Data Interrupt Clear 0 1 write-only RXSTALLDIC Received STALLed Interrupt Clear 6 1 write-only SHORTPACKETIC Short Packet Interrupt Clear 7 1 write-only TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 write-only TXSTPIC Transmitted SETUP Interrupt Clear 2 1 write-only HSTPIPICR[0] Host Pipe Clear Register (n = 0) 0 0xAC0 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[1] Host Pipe Clear Register (n = 0) 0 0x1024 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[2] Host Pipe Clear Register (n = 0) 0 0x158C 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[3] Host Pipe Clear Register (n = 0) 0 0x1AF8 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[4] Host Pipe Clear Register (n = 0) 0 0x2068 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[5] Host Pipe Clear Register (n = 0) 0 0x25DC 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[6] Host Pipe Clear Register (n = 0) 0 0x2B54 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[7] Host Pipe Clear Register (n = 0) 0 0x30D0 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[8] Host Pipe Clear Register (n = 0) 0 0x3650 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPICR[9] Host Pipe Clear Register (n = 0) 0 0x3BD4 32 write-only n 0x0 0x0 NAKEDIC NAKed Interrupt Clear 4 1 OVERFIC Overflow Interrupt Clear 5 1 RXINIC Received IN Data Interrupt Clear 0 1 RXSTALLDIC Received STALLed Interrupt Clear 6 1 SHORTPACKETIC Short Packet Interrupt Clear 7 1 TXOUTIC Transmitted OUT Data Interrupt Clear 1 1 TXSTPIC Transmitted SETUP Interrupt Clear 2 1 HSTPIPIDR0 Host Pipe Disable Register (n = 0) 0x620 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR0_INTPIPES Host Pipe Disable Register (n = 0) 0x620 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only UNDERFIEC Underflow Interrupt Disable 2 1 write-only HSTPIPIDR0_ISOPIPES Host Pipe Disable Register (n = 0) 0x620 32 write-only n CRCERREC CRC Error Interrupt Disable 6 1 write-only FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only UNDERFIEC Underflow Interrupt Disable 2 1 write-only HSTPIPIDR1 Host Pipe Disable Register (n = 0) 0x624 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR2 Host Pipe Disable Register (n = 0) 0x628 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR3 Host Pipe Disable Register (n = 0) 0x62C 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR4 Host Pipe Disable Register (n = 0) 0x630 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR5 Host Pipe Disable Register (n = 0) 0x634 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR6 Host Pipe Disable Register (n = 0) 0x638 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR7 Host Pipe Disable Register (n = 0) 0x63C 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR8 Host Pipe Disable Register (n = 0) 0x640 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR9 Host Pipe Disable Register (n = 0) 0x644 32 write-only n FIFOCONC FIFO Control Disable 14 1 write-only NAKEDEC NAKed Interrupt Disable 4 1 write-only NBUSYBKEC Number of Busy Banks Disable 12 1 write-only OVERFIEC Overflow Interrupt Disable 5 1 write-only PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 write-only PERREC Pipe Error Interrupt Disable 3 1 write-only PFREEZEC Pipe Freeze Disable 17 1 write-only RXINEC Received IN Data Interrupt Disable 0 1 write-only RXSTALLDEC Received STALLed Interrupt Disable 6 1 write-only SHORTPACKETIEC Short Packet Interrupt Disable 7 1 write-only TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 write-only TXSTPEC Transmitted SETUP Interrupt Disable 2 1 write-only HSTPIPIDR[0] Host Pipe Disable Register (n = 0) 0 0xC40 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[1] Host Pipe Disable Register (n = 0) 0 0x1264 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[2] Host Pipe Disable Register (n = 0) 0 0x188C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[3] Host Pipe Disable Register (n = 0) 0 0x1EB8 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[4] Host Pipe Disable Register (n = 0) 0 0x24E8 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[5] Host Pipe Disable Register (n = 0) 0 0x2B1C 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[6] Host Pipe Disable Register (n = 0) 0 0x3154 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[7] Host Pipe Disable Register (n = 0) 0 0x3790 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[8] Host Pipe Disable Register (n = 0) 0 0x3DD0 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIDR[9] Host Pipe Disable Register (n = 0) 0 0x4414 32 write-only n 0x0 0x0 FIFOCONC FIFO Control Disable 14 1 NAKEDEC NAKed Interrupt Disable 4 1 NBUSYBKEC Number of Busy Banks Disable 12 1 OVERFIEC Overflow Interrupt Disable 5 1 PDISHDMAC Pipe Interrupts Disable HDMA Request Disable 16 1 PERREC Pipe Error Interrupt Disable 3 1 PFREEZEC Pipe Freeze Disable 17 1 RXINEC Received IN Data Interrupt Disable 0 1 RXSTALLDEC Received STALLed Interrupt Disable 6 1 SHORTPACKETIEC Short Packet Interrupt Disable 7 1 TXOUTEC Transmitted OUT Data Interrupt Disable 1 1 TXSTPEC Transmitted SETUP Interrupt Disable 2 1 HSTPIPIER0 Host Pipe Enable Register (n = 0) 0x5F0 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER0_INTPIPES Host Pipe Enable Register (n = 0) 0x5F0 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only UNDERFIES Underflow Interrupt Enable 2 1 write-only HSTPIPIER0_ISOPIPES Host Pipe Enable Register (n = 0) 0x5F0 32 write-only n CRCERRES CRC Error Interrupt Enable 6 1 write-only NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only UNDERFIES Underflow Interrupt Enable 2 1 write-only HSTPIPIER1 Host Pipe Enable Register (n = 0) 0x5F4 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER2 Host Pipe Enable Register (n = 0) 0x5F8 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER3 Host Pipe Enable Register (n = 0) 0x5FC 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER4 Host Pipe Enable Register (n = 0) 0x600 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER5 Host Pipe Enable Register (n = 0) 0x604 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER6 Host Pipe Enable Register (n = 0) 0x608 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER7 Host Pipe Enable Register (n = 0) 0x60C 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER8 Host Pipe Enable Register (n = 0) 0x610 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER9 Host Pipe Enable Register (n = 0) 0x614 32 write-only n NAKEDES NAKed Interrupt Enable 4 1 write-only NBUSYBKES Number of Busy Banks Enable 12 1 write-only OVERFIES Overflow Interrupt Enable 5 1 write-only PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 write-only PERRES Pipe Error Interrupt Enable 3 1 write-only PFREEZES Pipe Freeze Enable 17 1 write-only RSTDTS Reset Data Toggle Enable 18 1 write-only RXINES Received IN Data Interrupt Enable 0 1 write-only RXSTALLDES Received STALLed Interrupt Enable 6 1 write-only SHORTPACKETIES Short Packet Interrupt Enable 7 1 write-only TXOUTES Transmitted OUT Data Interrupt Enable 1 1 write-only TXSTPES Transmitted SETUP Interrupt Enable 2 1 write-only HSTPIPIER[0] Host Pipe Enable Register (n = 0) 0 0xBE0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[1] Host Pipe Enable Register (n = 0) 0 0x11D4 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[2] Host Pipe Enable Register (n = 0) 0 0x17CC 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[3] Host Pipe Enable Register (n = 0) 0 0x1DC8 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[4] Host Pipe Enable Register (n = 0) 0 0x23C8 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[5] Host Pipe Enable Register (n = 0) 0 0x29CC 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[6] Host Pipe Enable Register (n = 0) 0 0x2FD4 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[7] Host Pipe Enable Register (n = 0) 0 0x35E0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[8] Host Pipe Enable Register (n = 0) 0 0x3BF0 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIER[9] Host Pipe Enable Register (n = 0) 0 0x4204 32 write-only n 0x0 0x0 NAKEDES NAKed Interrupt Enable 4 1 NBUSYBKES Number of Busy Banks Enable 12 1 OVERFIES Overflow Interrupt Enable 5 1 PDISHDMAS Pipe Interrupts Disable HDMA Request Enable 16 1 PERRES Pipe Error Interrupt Enable 3 1 PFREEZES Pipe Freeze Enable 17 1 RSTDTS Reset Data Toggle Enable 18 1 RXINES Received IN Data Interrupt Enable 0 1 RXSTALLDES Received STALLed Interrupt Enable 6 1 SHORTPACKETIES Short Packet Interrupt Enable 7 1 TXOUTES Transmitted OUT Data Interrupt Enable 1 1 TXSTPES Transmitted SETUP Interrupt Enable 2 1 HSTPIPIFR0 Host Pipe Set Register (n = 0) 0x590 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR0_INTPIPES Host Pipe Set Register (n = 0) 0x590 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only HSTPIPIFR0_ISOPIPES Host Pipe Set Register (n = 0) 0x590 32 write-only n CRCERRIS CRC Error Interrupt Set 6 1 write-only NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only UNDERFIS Underflow Interrupt Set 2 1 write-only HSTPIPIFR1 Host Pipe Set Register (n = 0) 0x594 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR2 Host Pipe Set Register (n = 0) 0x598 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR3 Host Pipe Set Register (n = 0) 0x59C 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR4 Host Pipe Set Register (n = 0) 0x5A0 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR5 Host Pipe Set Register (n = 0) 0x5A4 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR6 Host Pipe Set Register (n = 0) 0x5A8 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR7 Host Pipe Set Register (n = 0) 0x5AC 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR8 Host Pipe Set Register (n = 0) 0x5B0 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR9 Host Pipe Set Register (n = 0) 0x5B4 32 write-only n NAKEDIS NAKed Interrupt Set 4 1 write-only NBUSYBKS Number of Busy Banks Set 12 1 write-only OVERFIS Overflow Interrupt Set 5 1 write-only PERRIS Pipe Error Interrupt Set 3 1 write-only RXINIS Received IN Data Interrupt Set 0 1 write-only RXSTALLDIS Received STALLed Interrupt Set 6 1 write-only SHORTPACKETIS Short Packet Interrupt Set 7 1 write-only TXOUTIS Transmitted OUT Data Interrupt Set 1 1 write-only TXSTPIS Transmitted SETUP Interrupt Set 2 1 write-only HSTPIPIFR[0] Host Pipe Set Register (n = 0) 0 0xB20 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[1] Host Pipe Set Register (n = 0) 0 0x10B4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[2] Host Pipe Set Register (n = 0) 0 0x164C 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[3] Host Pipe Set Register (n = 0) 0 0x1BE8 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[4] Host Pipe Set Register (n = 0) 0 0x2188 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[5] Host Pipe Set Register (n = 0) 0 0x272C 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[6] Host Pipe Set Register (n = 0) 0 0x2CD4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[7] Host Pipe Set Register (n = 0) 0 0x3280 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[8] Host Pipe Set Register (n = 0) 0 0x3830 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIFR[9] Host Pipe Set Register (n = 0) 0 0x3DE4 32 write-only n 0x0 0x0 NAKEDIS NAKed Interrupt Set 4 1 NBUSYBKS Number of Busy Banks Set 12 1 OVERFIS Overflow Interrupt Set 5 1 PERRIS Pipe Error Interrupt Set 3 1 RXINIS Received IN Data Interrupt Set 0 1 RXSTALLDIS Received STALLed Interrupt Set 6 1 SHORTPACKETIS Short Packet Interrupt Set 7 1 TXOUTIS Transmitted OUT Data Interrupt Set 1 1 TXSTPIS Transmitted SETUP Interrupt Set 2 1 HSTPIPIMR0 Host Pipe Mask Register (n = 0) 0x5C0 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR0_INTPIPES Host Pipe Mask Register (n = 0) 0x5C0 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only UNDERFIE Underflow Interrupt Enable 2 1 read-only HSTPIPIMR0_ISOPIPES Host Pipe Mask Register (n = 0) 0x5C0 32 read-only n CRCERRE CRC Error Interrupt Enable 6 1 read-only FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only UNDERFIE Underflow Interrupt Enable 2 1 read-only HSTPIPIMR1 Host Pipe Mask Register (n = 0) 0x5C4 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR2 Host Pipe Mask Register (n = 0) 0x5C8 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR3 Host Pipe Mask Register (n = 0) 0x5CC 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR4 Host Pipe Mask Register (n = 0) 0x5D0 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR5 Host Pipe Mask Register (n = 0) 0x5D4 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR6 Host Pipe Mask Register (n = 0) 0x5D8 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR7 Host Pipe Mask Register (n = 0) 0x5DC 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR8 Host Pipe Mask Register (n = 0) 0x5E0 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR9 Host Pipe Mask Register (n = 0) 0x5E4 32 read-only n FIFOCON FIFO Control 14 1 read-only NAKEDE NAKed Interrupt Enable 4 1 read-only NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 read-only OVERFIE Overflow Interrupt Enable 5 1 read-only PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 read-only PERRE Pipe Error Interrupt Enable 3 1 read-only PFREEZE Pipe Freeze 17 1 read-only RSTDT Reset Data Toggle 18 1 read-only RXINE Received IN Data Interrupt Enable 0 1 read-only RXSTALLDE Received STALLed Interrupt Enable 6 1 read-only SHORTPACKETIE Short Packet Interrupt Enable 7 1 read-only TXOUTE Transmitted OUT Data Interrupt Enable 1 1 read-only TXSTPE Transmitted SETUP Interrupt Enable 2 1 read-only HSTPIPIMR[0] Host Pipe Mask Register (n = 0) 0 0xB80 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[1] Host Pipe Mask Register (n = 0) 0 0x1144 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[2] Host Pipe Mask Register (n = 0) 0 0x170C 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[3] Host Pipe Mask Register (n = 0) 0 0x1CD8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[4] Host Pipe Mask Register (n = 0) 0 0x22A8 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[5] Host Pipe Mask Register (n = 0) 0 0x287C 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[6] Host Pipe Mask Register (n = 0) 0 0x2E54 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[7] Host Pipe Mask Register (n = 0) 0 0x3430 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[8] Host Pipe Mask Register (n = 0) 0 0x3A10 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPIMR[9] Host Pipe Mask Register (n = 0) 0 0x3FF4 32 read-only n 0x0 0x0 FIFOCON FIFO Control 14 1 NAKEDE NAKed Interrupt Enable 4 1 NBUSYBKE Number of Busy Banks Interrupt Enable 12 1 OVERFIE Overflow Interrupt Enable 5 1 PDISHDMA Pipe Interrupts Disable HDMA Request Enable 16 1 PERRE Pipe Error Interrupt Enable 3 1 PFREEZE Pipe Freeze 17 1 RSTDT Reset Data Toggle 18 1 RXINE Received IN Data Interrupt Enable 0 1 RXSTALLDE Received STALLed Interrupt Enable 6 1 SHORTPACKETIE Short Packet Interrupt Enable 7 1 TXOUTE Transmitted OUT Data Interrupt Enable 1 1 TXSTPE Transmitted SETUP Interrupt Enable 2 1 HSTPIPINRQ0 Host Pipe IN Request Register (n = 0) 0x650 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ1 Host Pipe IN Request Register (n = 0) 0x654 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ2 Host Pipe IN Request Register (n = 0) 0x658 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ3 Host Pipe IN Request Register (n = 0) 0x65C 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ4 Host Pipe IN Request Register (n = 0) 0x660 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ5 Host Pipe IN Request Register (n = 0) 0x664 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ6 Host Pipe IN Request Register (n = 0) 0x668 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ7 Host Pipe IN Request Register (n = 0) 0x66C 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ8 Host Pipe IN Request Register (n = 0) 0x670 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ9 Host Pipe IN Request Register (n = 0) 0x674 32 read-write n INMODE IN Request Mode 8 1 read-write INRQ IN Request Number before Freeze 0 8 read-write HSTPIPINRQ[0] Host Pipe IN Request Register (n = 0) 0 0xCA0 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[1] Host Pipe IN Request Register (n = 0) 0 0x12F4 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[2] Host Pipe IN Request Register (n = 0) 0 0x194C 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[3] Host Pipe IN Request Register (n = 0) 0 0x1FA8 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[4] Host Pipe IN Request Register (n = 0) 0 0x2608 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[5] Host Pipe IN Request Register (n = 0) 0 0x2C6C 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[6] Host Pipe IN Request Register (n = 0) 0 0x32D4 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[7] Host Pipe IN Request Register (n = 0) 0 0x3940 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[8] Host Pipe IN Request Register (n = 0) 0 0x3FB0 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPINRQ[9] Host Pipe IN Request Register (n = 0) 0 0x4624 32 read-write n 0x0 0x0 INMODE IN Request Mode 8 1 INRQ IN Request Number before Freeze 0 8 HSTPIPISR0 Host Pipe Status Register (n = 0) 0x530 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR0_INTPIPES Host Pipe Status Register (n = 0) 0x530 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only UNDERFI Underflow Interrupt 2 1 read-only HSTPIPISR0_ISOPIPES Host Pipe Status Register (n = 0) 0x530 32 read-only n CFGOK Configuration OK Status 18 1 read-only CRCERRI CRC Error Interrupt 6 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only UNDERFI Underflow Interrupt 2 1 read-only HSTPIPISR1 Host Pipe Status Register (n = 0) 0x534 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR2 Host Pipe Status Register (n = 0) 0x538 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR3 Host Pipe Status Register (n = 0) 0x53C 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR4 Host Pipe Status Register (n = 0) 0x540 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR5 Host Pipe Status Register (n = 0) 0x544 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR6 Host Pipe Status Register (n = 0) 0x548 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR7 Host Pipe Status Register (n = 0) 0x54C 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR8 Host Pipe Status Register (n = 0) 0x550 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR9 Host Pipe Status Register (n = 0) 0x554 32 read-only n CFGOK Configuration OK Status 18 1 read-only CURRBK Current Bank 14 2 read-only BANK0 Current bank is bank0 0x0 BANK1 Current bank is bank1 0x1 BANK2 Current bank is bank2 0x2 DTSEQ Data Toggle Sequence 8 2 read-only DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 read-only NBUSYBK Number of Busy Banks 12 2 read-only 0_BUSY 0 busy bank (all banks free) 0x0 1_BUSY 1 busy bank 0x1 2_BUSY 2 busy banks 0x2 3_BUSY 3 busy banks 0x3 OVERFI Overflow Interrupt 5 1 read-only PBYCT Pipe Byte Count 20 11 read-only PERRI Pipe Error Interrupt 3 1 read-only RWALL Read/Write Allowed 16 1 read-only RXINI Received IN Data Interrupt 0 1 read-only RXSTALLDI Received STALLed Interrupt 6 1 read-only SHORTPACKETI Short Packet Interrupt 7 1 read-only TXOUTI Transmitted OUT Data Interrupt 1 1 read-only TXSTPI Transmitted SETUP Interrupt 2 1 read-only HSTPIPISR[0] Host Pipe Status Register (n = 0) 0 0xA60 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[1] Host Pipe Status Register (n = 0) 0 0xF94 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[2] Host Pipe Status Register (n = 0) 0 0x14CC 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[3] Host Pipe Status Register (n = 0) 0 0x1A08 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[4] Host Pipe Status Register (n = 0) 0 0x1F48 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[5] Host Pipe Status Register (n = 0) 0 0x248C 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[6] Host Pipe Status Register (n = 0) 0 0x29D4 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[7] Host Pipe Status Register (n = 0) 0 0x2F20 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[8] Host Pipe Status Register (n = 0) 0 0x3470 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 HSTPIPISR[9] Host Pipe Status Register (n = 0) 0 0x39C4 32 read-only n 0x0 0x0 CFGOK Configuration OK Status 18 1 CURRBK Current Bank 14 2 CURRBKSelect BANK0 Current bank is bank0 0 BANK1 Current bank is bank1 1 BANK2 Current bank is bank2 2 DTSEQ Data Toggle Sequence 8 2 DTSEQSelect DATA0 Data0 toggle sequence 0 DATA1 Data1 toggle sequence 1 NAKEDI NAKed Interrupt 4 1 NBUSYBK Number of Busy Banks 12 2 NBUSYBKSelect _0_BUSY 0 busy bank (all banks free) 0 _1_BUSY 1 busy bank 1 _2_BUSY 2 busy banks 2 _3_BUSY 3 busy banks 3 OVERFI Overflow Interrupt 5 1 PBYCT Pipe Byte Count 20 11 PERRI Pipe Error Interrupt 3 1 RWALL Read/Write Allowed 16 1 RXINI Received IN Data Interrupt 0 1 RXSTALLDI Received STALLed Interrupt 6 1 SHORTPACKETI Short Packet Interrupt 7 1 TXOUTI Transmitted OUT Data Interrupt 1 1 TXSTPI Transmitted SETUP Interrupt 2 1 SCR General Status Clear Register 0x808 32 write-only n 0x0 0x0 RDERRIC Remote Device Connection Error Interrupt Clear 4 1 SFR General Status Set Register 0x80C 32 write-only n 0x0 0x0 RDERRIS Remote Device Connection Error Interrupt Set 4 1 VBUSRQS VBUS Request Set 9 1 SR General Status Register 0x804 32 read-only n 0x0 0x0 CLKUSABLE UTMI Clock Usable 14 1 RDERRI Remote Device Connection Error Interrupt (Host mode only) 4 1 SPEED Speed Status (Device mode only) 12 2 SPEEDSelect FULL_SPEED Full-Speed mode 0 HIGH_SPEED High-Speed mode 1 LOW_SPEED Low-Speed mode 2 UTMI USB Transmitter Interface Macrocell UTMI 0x0 0x0 0x30 registers n CKTRIM UTMI Clock Trimming Register 0x30 32 read-write n 0x0 0x0 FREQ UTMI Reference Clock Frequency 0 2 FREQSelect XTAL12 12 MHz reference clock 0 XTAL16 16 MHz reference clock 1 OHCIICR OHCI Interrupt Configuration Register 0x10 32 read-write n 0x0 0x0 APPSTART 5 1 ARIE OHCI Asynchronous Resume Interrupt Enable 4 1 RES0 USB PORTx Reset 0 1 UDPPUDIS USB Device Pull-up Disable 23 1 WDT Watchdog Timer WDT 0x0 0x0 0xC registers n WDT 4 CR Control Register 0x0 32 write-only n 0x0 0x0 KEY Password 24 8 KEYSelect PASSWD Writing any other value in this field aborts the write operation. 165 WDRSTT Watchdog Restart 0 1 MR Mode Register 0x4 32 read-write n 0x0 0x0 WDD Watchdog Delta Value 16 12 WDDBGHLT Watchdog Debug Halt 28 1 WDDIS Watchdog Disable 15 1 WDFIEN Watchdog Fault Interrupt Enable 12 1 WDIDLEHLT Watchdog Idle Halt 29 1 WDRSTEN Watchdog Reset Enable 13 1 WDV Watchdog Counter Value 0 12 SR Status Register 0x8 32 read-only n 0x0 0x0 WDERR Watchdog Error (cleared on read) 1 1 WDUNF Watchdog Underflow (cleared on read) 0 1 XDMAC Extensible DMA Controller XDMAC 0x0 0x0 0x4000 registers n XDMAC 58 CBC0 Channel Block Control Register (chid = 0) 0x74 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC1 Channel Block Control Register (chid = 1) 0xB4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC10 Channel Block Control Register (chid = 10) 0x2F4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC11 Channel Block Control Register (chid = 11) 0x334 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC12 Channel Block Control Register (chid = 12) 0x374 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC13 Channel Block Control Register (chid = 13) 0x3B4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC14 Channel Block Control Register (chid = 14) 0x3F4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC15 Channel Block Control Register (chid = 15) 0x434 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC16 Channel Block Control Register (chid = 16) 0x474 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC17 Channel Block Control Register (chid = 17) 0x4B4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC18 Channel Block Control Register (chid = 18) 0x4F4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC19 Channel Block Control Register (chid = 19) 0x534 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC2 Channel Block Control Register (chid = 2) 0xF4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC20 Channel Block Control Register (chid = 20) 0x574 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC21 Channel Block Control Register (chid = 21) 0x5B4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC22 Channel Block Control Register (chid = 22) 0x5F4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC23 Channel Block Control Register (chid = 23) 0x634 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC3 Channel Block Control Register (chid = 3) 0x134 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC4 Channel Block Control Register (chid = 4) 0x174 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC5 Channel Block Control Register (chid = 5) 0x1B4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC6 Channel Block Control Register (chid = 6) 0x1F4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC7 Channel Block Control Register (chid = 7) 0x234 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC8 Channel Block Control Register (chid = 8) 0x274 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CBC9 Channel Block Control Register (chid = 9) 0x2B4 32 read-write n 0x0 BLEN Channel x Block Length 0 12 read-write CC0 Channel Configuration Register (chid = 0) 0x78 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC1 Channel Configuration Register (chid = 1) 0xB8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC10 Channel Configuration Register (chid = 10) 0x2F8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC11 Channel Configuration Register (chid = 11) 0x338 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC12 Channel Configuration Register (chid = 12) 0x378 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC13 Channel Configuration Register (chid = 13) 0x3B8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC14 Channel Configuration Register (chid = 14) 0x3F8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC15 Channel Configuration Register (chid = 15) 0x438 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC16 Channel Configuration Register (chid = 16) 0x478 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC17 Channel Configuration Register (chid = 17) 0x4B8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC18 Channel Configuration Register (chid = 18) 0x4F8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC19 Channel Configuration Register (chid = 19) 0x538 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC2 Channel Configuration Register (chid = 2) 0xF8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC20 Channel Configuration Register (chid = 20) 0x578 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC21 Channel Configuration Register (chid = 21) 0x5B8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC22 Channel Configuration Register (chid = 22) 0x5F8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC23 Channel Configuration Register (chid = 23) 0x638 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC3 Channel Configuration Register (chid = 3) 0x138 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC4 Channel Configuration Register (chid = 4) 0x178 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC5 Channel Configuration Register (chid = 5) 0x1B8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC6 Channel Configuration Register (chid = 6) 0x1F8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC7 Channel Configuration Register (chid = 7) 0x238 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC8 Channel Configuration Register (chid = 8) 0x278 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CC9 Channel Configuration Register (chid = 9) 0x2B8 32 read-write n 0x0 CSIZE Channel x Chunk Size 8 3 read-write CHK_1 1 data transferred 0x0 CHK_2 2 data transferred 0x1 CHK_4 4 data transferred 0x2 CHK_8 8 data transferred 0x3 CHK_16 16 data transferred 0x4 DAM Channel x Destination Addressing Mode 18 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 DIF Channel x Destination Interface Identifier 14 1 read-write AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 read-write PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 read-write BYTE The data size is set to 8 bits 0x0 HALFWORD The data size is set to 16 bits 0x1 WORD The data size is set to 32 bits 0x2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 read-write TERMINATED Channel initialization is in progress. 0 IN_PROGRESS Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 read-write SINGLE The memory burst size is set to one. 0x0 FOUR The memory burst size is set to four. 0x1 EIGHT The memory burst size is set to eight. 0x2 SIXTEEN The memory burst size is set to sixteen. 0x3 MEMSET Channel x Fill Block of memory 7 1 read-write NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8, 16 or 32 bits basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 read-write RDIP Read in Progress (this bit is read-only) 22 1 read-write DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 read-write FIXED_AM The address remains unchanged. 0x0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 0x1 UBS_AM The microblock stride is added at the microblock boundary. 0x2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 0x3 SIF Channel x Source Interface Identifier 13 1 read-write AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 read-write HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 read-write MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 read-write DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CDA0 Channel Destination Address Register (chid = 0) 0x64 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA1 Channel Destination Address Register (chid = 1) 0xA4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA10 Channel Destination Address Register (chid = 10) 0x2E4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA11 Channel Destination Address Register (chid = 11) 0x324 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA12 Channel Destination Address Register (chid = 12) 0x364 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA13 Channel Destination Address Register (chid = 13) 0x3A4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA14 Channel Destination Address Register (chid = 14) 0x3E4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA15 Channel Destination Address Register (chid = 15) 0x424 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA16 Channel Destination Address Register (chid = 16) 0x464 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA17 Channel Destination Address Register (chid = 17) 0x4A4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA18 Channel Destination Address Register (chid = 18) 0x4E4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA19 Channel Destination Address Register (chid = 19) 0x524 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA2 Channel Destination Address Register (chid = 2) 0xE4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA20 Channel Destination Address Register (chid = 20) 0x564 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA21 Channel Destination Address Register (chid = 21) 0x5A4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA22 Channel Destination Address Register (chid = 22) 0x5E4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA23 Channel Destination Address Register (chid = 23) 0x624 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA3 Channel Destination Address Register (chid = 3) 0x124 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA4 Channel Destination Address Register (chid = 4) 0x164 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA5 Channel Destination Address Register (chid = 5) 0x1A4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA6 Channel Destination Address Register (chid = 6) 0x1E4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA7 Channel Destination Address Register (chid = 7) 0x224 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA8 Channel Destination Address Register (chid = 8) 0x264 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDA9 Channel Destination Address Register (chid = 9) 0x2A4 32 read-write n 0x0 DA Channel x Destination Address 0 32 read-write CDS_MSP0 Channel Data Stride Memory Set Pattern (chid = 0) 0x7C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP1 Channel Data Stride Memory Set Pattern (chid = 1) 0xBC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP10 Channel Data Stride Memory Set Pattern (chid = 10) 0x2FC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP11 Channel Data Stride Memory Set Pattern (chid = 11) 0x33C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP12 Channel Data Stride Memory Set Pattern (chid = 12) 0x37C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP13 Channel Data Stride Memory Set Pattern (chid = 13) 0x3BC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP14 Channel Data Stride Memory Set Pattern (chid = 14) 0x3FC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP15 Channel Data Stride Memory Set Pattern (chid = 15) 0x43C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP16 Channel Data Stride Memory Set Pattern (chid = 16) 0x47C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP17 Channel Data Stride Memory Set Pattern (chid = 17) 0x4BC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP18 Channel Data Stride Memory Set Pattern (chid = 18) 0x4FC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP19 Channel Data Stride Memory Set Pattern (chid = 19) 0x53C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP2 Channel Data Stride Memory Set Pattern (chid = 2) 0xFC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP20 Channel Data Stride Memory Set Pattern (chid = 20) 0x57C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP21 Channel Data Stride Memory Set Pattern (chid = 21) 0x5BC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP22 Channel Data Stride Memory Set Pattern (chid = 22) 0x5FC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP23 Channel Data Stride Memory Set Pattern (chid = 23) 0x63C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP3 Channel Data Stride Memory Set Pattern (chid = 3) 0x13C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP4 Channel Data Stride Memory Set Pattern (chid = 4) 0x17C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP5 Channel Data Stride Memory Set Pattern (chid = 5) 0x1BC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP6 Channel Data Stride Memory Set Pattern (chid = 6) 0x1FC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP7 Channel Data Stride Memory Set Pattern (chid = 7) 0x23C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP8 Channel Data Stride Memory Set Pattern (chid = 8) 0x27C 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDS_MSP9 Channel Data Stride Memory Set Pattern (chid = 9) 0x2BC 32 read-write n 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 read-write SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 read-write CDUS0 Channel Destination Microblock Stride (chid = 0) 0x84 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS1 Channel Destination Microblock Stride (chid = 1) 0xC4 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS10 Channel Destination Microblock Stride (chid = 10) 0x304 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS11 Channel Destination Microblock Stride (chid = 11) 0x344 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS12 Channel Destination Microblock Stride (chid = 12) 0x384 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS13 Channel Destination Microblock Stride (chid = 13) 0x3C4 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS14 Channel Destination Microblock Stride (chid = 14) 0x404 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS15 Channel Destination Microblock Stride (chid = 15) 0x444 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS16 Channel Destination Microblock Stride (chid = 16) 0x484 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS17 Channel Destination Microblock Stride (chid = 17) 0x4C4 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS18 Channel Destination Microblock Stride (chid = 18) 0x504 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS19 Channel Destination Microblock Stride (chid = 19) 0x544 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS2 Channel Destination Microblock Stride (chid = 2) 0x104 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS20 Channel Destination Microblock Stride (chid = 20) 0x584 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS21 Channel Destination Microblock Stride (chid = 21) 0x5C4 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS22 Channel Destination Microblock Stride (chid = 22) 0x604 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS23 Channel Destination Microblock Stride (chid = 23) 0x644 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS3 Channel Destination Microblock Stride (chid = 3) 0x144 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS4 Channel Destination Microblock Stride (chid = 4) 0x184 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS5 Channel Destination Microblock Stride (chid = 5) 0x1C4 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS6 Channel Destination Microblock Stride (chid = 6) 0x204 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS7 Channel Destination Microblock Stride (chid = 7) 0x244 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS8 Channel Destination Microblock Stride (chid = 8) 0x284 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CDUS9 Channel Destination Microblock Stride (chid = 9) 0x2C4 32 read-write n 0x0 DUBS Channel x Destination Microblock Stride 0 24 read-write CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x74 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x78 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x64 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x7C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x84 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x54 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x50 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x58 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x5C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x68 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x6C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x60 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x80 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x70 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x1154 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x1158 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x1144 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x115C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x1164 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x1134 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x1130 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x1138 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x113C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x1148 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x114C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x1140 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x1160 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x1150 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x1464 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x1468 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x1454 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x146C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x1474 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x1444 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x1440 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x1448 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x144C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x1458 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x145C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x1450 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x1470 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x1460 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x17B4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x17B8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x17A4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x17BC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x17C4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x1794 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x1790 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x1798 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x179C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x17A8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x17AC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x17A0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x17C0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x17B0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x1B44 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x1B48 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x1B34 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x1B4C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x1B54 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x1B24 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x1B20 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x1B28 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x1B2C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x1B38 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x1B3C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x1B30 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x1B50 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x1B40 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x1F14 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x1F18 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x1F04 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x1F1C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x1F24 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x1EF4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x1EF0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x1EF8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x1EFC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x1F08 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x1F0C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x1F00 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x1F20 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x1F10 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x2324 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x2328 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x2314 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x232C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x2334 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x2304 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x2300 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x2308 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x230C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x2318 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x231C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x2310 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x2330 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x2320 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x2774 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x2778 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x2764 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x277C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x2784 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x2754 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x2750 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x2758 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x275C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x2768 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x276C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x2760 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x2780 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x2770 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x2C04 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x2C08 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x2BF4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x2C0C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x2C14 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x2BE4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x2BE0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x2BE8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x2BEC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x2BF8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x2BFC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x2BF0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x2C10 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x2C00 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x30D4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x30D8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x30C4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x30DC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x30E4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x30B4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x30B0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x30B8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x30BC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x30C8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x30CC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x30C0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x30E0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x30D0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x35E4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x35E8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x35D4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x35EC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x35F4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x35C4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x35C0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x35C8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x35CC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x35D8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x35DC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x35D0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x35F0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x35E0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x104 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x108 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0xF4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x10C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x114 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0xE4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0xE0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0xE8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0xEC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0xF8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0xFC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0xF0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x110 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x100 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x3B34 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x3B38 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x3B24 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x3B3C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x3B44 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x3B14 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x3B10 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x3B18 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x3B1C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x3B28 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x3B2C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x3B20 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x3B40 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x3B30 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x40C4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x40C8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x40B4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x40CC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x40D4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x40A4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x40A0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x40A8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x40AC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x40B8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x40BC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x40B0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x40D0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x40C0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x4694 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x4698 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x4684 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x469C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x46A4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x4674 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x4670 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x4678 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x467C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x4688 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x468C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x4680 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x46A0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x4690 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x4CA4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x4CA8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x4C94 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x4CAC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x4CB4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x4C84 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x4C80 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x4C88 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x4C8C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x4C98 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x4C9C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x4C90 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x4CB0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[23]-XDMAC_CHID[22]-XDMAC_CHID[21]-XDMAC_CHID[20]-XDMAC_CHID[19]-XDMAC_CHID[18]-XDMAC_CHID[17]-XDMAC_CHID[16]-XDMAC_CHID[15]-XDMAC_CHID[14]-XDMAC_CHID[13]-XDMAC_CHID[12]-XDMAC_CHID[11]-XDMAC_CHID[10]-XDMAC_CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x4CA0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x1D4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x1D8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x1C4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x1DC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x1E4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x1B4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x1B0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x1B8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x1BC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x1C8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x1CC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x1C0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x1E0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x1D0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x2E4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x2E8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x2D4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x2EC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x2F4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x2C4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x2C0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x2C8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x2CC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x2D8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x2DC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x2D0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x2F0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x2E0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x434 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x438 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x424 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x43C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x444 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x414 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x410 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x418 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x41C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x428 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x42C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x420 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x440 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x430 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x5C4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x5C8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x5B4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x5CC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x5D4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x5A4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x5A0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x5A8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x5AC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x5B8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x5BC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x5B0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x5D0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x5C0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x794 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x798 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x784 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x79C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x7A4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x774 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x770 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x778 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x77C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x788 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x78C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x780 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x7A0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x790 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0x9A4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0x9A8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0x994 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0x9AC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0x9B4 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0x984 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0x980 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0x988 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0x98C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0x998 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0x99C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0x990 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0x9B0 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0x9A0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0xBF4 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0xBF8 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0xBE4 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0xBFC 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0xC04 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0xBD4 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0xBD0 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0xBD8 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0xBDC 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0xBE8 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0xBEC 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0xBE0 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0xC00 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0xBF0 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CBC Channel Block Control Register (chid = 0) 0xE84 32 read-write n 0x0 0x0 BLEN Channel x Block Length 0 12 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CC Channel Configuration Register (chid = 0) 0xE88 32 read-write n 0x0 0x0 CSIZE Channel x Chunk Size 8 3 CSIZESelect CHK_1 1 data transferred 0 CHK_2 2 data transferred 1 CHK_4 4 data transferred 2 CHK_8 8 data transferred 3 CHK_16 16 data transferred 4 DAM Channel x Destination Addressing Mode 18 2 DAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 DIF Channel x Destination Interface Identifier 14 1 DIFSelect AHB_IF0 The data is written through the system bus interface 0. 0 AHB_IF1 The data is written though the system bus interface 1. 1 DSYNC Channel x Synchronization 4 1 DSYNCSelect PER2MEM Peripheral to Memory transfer. 0 MEM2PER Memory to Peripheral transfer. 1 DWIDTH Channel x Data Width 11 2 DWIDTHSelect BYTE The data size is set to 8 bits 0 HALFWORD The data size is set to 16 bits 1 WORD The data size is set to 32 bits 2 INITD Channel Initialization Terminated (this bit is read-only) 21 1 INITDSelect IN_PROGRESS Channel initialization is in progress. 0 TERMINATED Channel initialization is completed. 1 MBSIZE Channel x Memory Burst Size 1 2 MBSIZESelect SINGLE The memory burst size is set to one. 0 FOUR The memory burst size is set to four. 1 EIGHT The memory burst size is set to eight. 2 SIXTEEN The memory burst size is set to sixteen. 3 MEMSET Channel x Fill Block of memory 7 1 MEMSETSelect NORMAL_MODE Memset is not activated. 0 HW_MODE Sets the block of memory pointed by DA field to the specified value. This operation is performed on 8-, 16- or 32-bit basis. 1 PERID Channel x Peripheral Hardware Request Line Identifier 24 7 RDIP Read in Progress (this bit is read-only) 22 1 RDIPSelect DONE No Active read transaction on the bus. 0 IN_PROGRESS A read transaction is in progress. 1 SAM Channel x Source Addressing Mode 16 2 SAMSelect FIXED_AM The address remains unchanged. 0 INCREMENTED_AM The addressing mode is incremented (the increment size is set to the data size). 1 UBS_AM The microblock stride is added at the microblock boundary. 2 UBS_DS_AM The microblock stride is added at the microblock boundary, the data stride is added at the data boundary. 3 SIF Channel x Source Interface Identifier 13 1 SIFSelect AHB_IF0 The data is read through the system bus interface 0. 0 AHB_IF1 The data is read through the system bus interface 1. 1 SWREQ Channel x Software Request Trigger 6 1 SWREQSelect HWR_CONNECTED Hardware request line is connected to the peripheral request line. 0 SWR_CONNECTED Software request is connected to the peripheral request line. 1 TYPE Channel x Transfer Type 0 1 TYPESelect MEM_TRAN Self triggered mode (Memory to Memory Transfer). 0 PER_TRAN Synchronized mode (Peripheral to Memory or Memory to Peripheral Transfer). 1 WRIP Write in Progress (this bit is read-only) 23 1 WRIPSelect DONE No Active write transaction on the bus. 0 IN_PROGRESS A Write transaction is in progress. 1 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDA Channel Destination Address Register (chid = 0) 0xE74 32 read-write n 0x0 0x0 DA Channel x Destination Address 0 32 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDS_MSP Channel Data Stride Memory Set Pattern (chid = 0) 0xE8C 32 read-write n 0x0 0x0 DDS_MSP Channel x Destination Data Stride or Memory Set Pattern 16 16 SDS_MSP Channel x Source Data stride or Memory Set Pattern 0 16 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CDUS Channel Destination Microblock Stride (chid = 0) 0xE94 32 read-write n 0x0 0x0 DUBS Channel x Destination Microblock Stride 0 24 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CID Channel Interrupt Disable Register (chid = 0) 0xE64 32 write-only n 0x0 0x0 BID End of Block Interrupt Disable Bit 0 1 DID End of Disable Interrupt Disable Bit 2 1 FID End of Flush Interrupt Disable Bit 3 1 LID End of Linked List Interrupt Disable Bit 1 1 RBEID Read Bus Error Interrupt Disable Bit 4 1 ROID Request Overflow Error Interrupt Disable Bit 6 1 WBEID Write Bus Error Interrupt Disable Bit 5 1 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIE Channel Interrupt Enable Register (chid = 0) 0xE60 32 write-only n 0x0 0x0 BIE End of Block Interrupt Enable Bit 0 1 DIE End of Disable Interrupt Enable Bit 2 1 FIE End of Flush Interrupt Enable Bit 3 1 LIE End of Linked List Interrupt Enable Bit 1 1 RBIE Read Bus Error Interrupt Enable Bit 4 1 ROIE Request Overflow Error Interrupt Enable Bit 6 1 WBIE Write Bus Error Interrupt Enable Bit 5 1 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIM Channel Interrupt Mask Register (chid = 0) 0xE68 32 read-only n 0x0 0x0 BIM End of Block Interrupt Mask Bit 0 1 DIM End of Disable Interrupt Mask Bit 2 1 FIM End of Flush Interrupt Mask Bit 3 1 LIM End of Linked List Interrupt Mask Bit 1 1 RBEIM Read Bus Error Interrupt Mask Bit 4 1 ROIM Request Overflow Error Interrupt Mask Bit 6 1 WBEIM Write Bus Error Interrupt Mask Bit 5 1 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CIS Channel Interrupt Status Register (chid = 0) 0xE6C 32 read-only n 0x0 0x0 BIS End of Block Interrupt Status Bit 0 1 DIS End of Disable Interrupt Status Bit 2 1 FIS End of Flush Interrupt Status Bit 3 1 LIS End of Linked List Interrupt Status Bit 1 1 RBEIS Read Bus Error Interrupt Status Bit 4 1 ROIS Request Overflow Error Interrupt Status Bit 6 1 WBEIS Write Bus Error Interrupt Status Bit 5 1 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDA Channel Next Descriptor Address Register (chid = 0) 0xE78 32 read-write n 0x0 0x0 NDA Channel x Next Descriptor Address 2 30 NDAIF Channel x Next Descriptor Interface 0 1 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CNDC Channel Next Descriptor Control Register (chid = 0) 0xE7C 32 read-write n 0x0 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 NDDUPSelect DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 NDESelect DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 NDSUPSelect SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 NDVIEWSelect NDV0 Next Descriptor View 0 0 NDV1 Next Descriptor View 1 1 NDV2 Next Descriptor View 2 2 NDV3 Next Descriptor View 3 3 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSA Channel Source Address Register (chid = 0) 0xE70 32 read-write n 0x0 0x0 SA Channel x Source Address 0 32 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CSUS Channel Source Microblock Stride (chid = 0) 0xE90 32 read-write n 0x0 0x0 SUBS Channel x Source Microblock Stride 0 24 CHID[9]-XDMAC_CHID[8]-XDMAC_CHID[7]-XDMAC_CHID[6]-XDMAC_CHID[5]-XDMAC_CHID[4]-XDMAC_CHID[3]-XDMAC_CHID[2]-XDMAC_CHID[1]-XDMAC_CHID[0]-XDMAC_CUBC Channel Microblock Control Register (chid = 0) 0xE80 32 read-write n 0x0 0x0 UBLEN Channel x Microblock Length 0 24 CID0 Channel Interrupt Disable Register (chid = 0) 0x54 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID1 Channel Interrupt Disable Register (chid = 1) 0x94 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID10 Channel Interrupt Disable Register (chid = 10) 0x2D4 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID11 Channel Interrupt Disable Register (chid = 11) 0x314 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID12 Channel Interrupt Disable Register (chid = 12) 0x354 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID13 Channel Interrupt Disable Register (chid = 13) 0x394 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID14 Channel Interrupt Disable Register (chid = 14) 0x3D4 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID15 Channel Interrupt Disable Register (chid = 15) 0x414 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID16 Channel Interrupt Disable Register (chid = 16) 0x454 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID17 Channel Interrupt Disable Register (chid = 17) 0x494 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID18 Channel Interrupt Disable Register (chid = 18) 0x4D4 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID19 Channel Interrupt Disable Register (chid = 19) 0x514 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID2 Channel Interrupt Disable Register (chid = 2) 0xD4 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID20 Channel Interrupt Disable Register (chid = 20) 0x554 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID21 Channel Interrupt Disable Register (chid = 21) 0x594 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID22 Channel Interrupt Disable Register (chid = 22) 0x5D4 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID23 Channel Interrupt Disable Register (chid = 23) 0x614 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID3 Channel Interrupt Disable Register (chid = 3) 0x114 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID4 Channel Interrupt Disable Register (chid = 4) 0x154 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID5 Channel Interrupt Disable Register (chid = 5) 0x194 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID6 Channel Interrupt Disable Register (chid = 6) 0x1D4 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID7 Channel Interrupt Disable Register (chid = 7) 0x214 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID8 Channel Interrupt Disable Register (chid = 8) 0x254 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CID9 Channel Interrupt Disable Register (chid = 9) 0x294 32 write-only n BID End of Block Interrupt Disable Bit 0 1 write-only DID End of Disable Interrupt Disable Bit 2 1 write-only FID End of Flush Interrupt Disable Bit 3 1 write-only LID End of Linked List Interrupt Disable Bit 1 1 write-only RBEID Read Bus Error Interrupt Disable Bit 4 1 write-only ROID Request Overflow Error Interrupt Disable Bit 6 1 write-only WBEID Write Bus Error Interrupt Disable Bit 5 1 write-only CIE0 Channel Interrupt Enable Register (chid = 0) 0x50 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE1 Channel Interrupt Enable Register (chid = 1) 0x90 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE10 Channel Interrupt Enable Register (chid = 10) 0x2D0 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE11 Channel Interrupt Enable Register (chid = 11) 0x310 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE12 Channel Interrupt Enable Register (chid = 12) 0x350 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE13 Channel Interrupt Enable Register (chid = 13) 0x390 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE14 Channel Interrupt Enable Register (chid = 14) 0x3D0 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE15 Channel Interrupt Enable Register (chid = 15) 0x410 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE16 Channel Interrupt Enable Register (chid = 16) 0x450 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE17 Channel Interrupt Enable Register (chid = 17) 0x490 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE18 Channel Interrupt Enable Register (chid = 18) 0x4D0 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE19 Channel Interrupt Enable Register (chid = 19) 0x510 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE2 Channel Interrupt Enable Register (chid = 2) 0xD0 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE20 Channel Interrupt Enable Register (chid = 20) 0x550 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE21 Channel Interrupt Enable Register (chid = 21) 0x590 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE22 Channel Interrupt Enable Register (chid = 22) 0x5D0 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE23 Channel Interrupt Enable Register (chid = 23) 0x610 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE3 Channel Interrupt Enable Register (chid = 3) 0x110 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE4 Channel Interrupt Enable Register (chid = 4) 0x150 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE5 Channel Interrupt Enable Register (chid = 5) 0x190 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE6 Channel Interrupt Enable Register (chid = 6) 0x1D0 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE7 Channel Interrupt Enable Register (chid = 7) 0x210 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE8 Channel Interrupt Enable Register (chid = 8) 0x250 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIE9 Channel Interrupt Enable Register (chid = 9) 0x290 32 write-only n BIE End of Block Interrupt Enable Bit 0 1 write-only DIE End of Disable Interrupt Enable Bit 2 1 write-only FIE End of Flush Interrupt Enable Bit 3 1 write-only LIE End of Linked List Interrupt Enable Bit 1 1 write-only RBIE Read Bus Error Interrupt Enable Bit 4 1 write-only ROIE Request Overflow Error Interrupt Enable Bit 6 1 write-only WBIE Write Bus Error Interrupt Enable Bit 5 1 write-only CIM0 Channel Interrupt Mask Register (chid = 0) 0x58 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM1 Channel Interrupt Mask Register (chid = 1) 0x98 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM10 Channel Interrupt Mask Register (chid = 10) 0x2D8 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM11 Channel Interrupt Mask Register (chid = 11) 0x318 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM12 Channel Interrupt Mask Register (chid = 12) 0x358 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM13 Channel Interrupt Mask Register (chid = 13) 0x398 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM14 Channel Interrupt Mask Register (chid = 14) 0x3D8 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM15 Channel Interrupt Mask Register (chid = 15) 0x418 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM16 Channel Interrupt Mask Register (chid = 16) 0x458 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM17 Channel Interrupt Mask Register (chid = 17) 0x498 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM18 Channel Interrupt Mask Register (chid = 18) 0x4D8 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM19 Channel Interrupt Mask Register (chid = 19) 0x518 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM2 Channel Interrupt Mask Register (chid = 2) 0xD8 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM20 Channel Interrupt Mask Register (chid = 20) 0x558 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM21 Channel Interrupt Mask Register (chid = 21) 0x598 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM22 Channel Interrupt Mask Register (chid = 22) 0x5D8 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM23 Channel Interrupt Mask Register (chid = 23) 0x618 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM3 Channel Interrupt Mask Register (chid = 3) 0x118 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM4 Channel Interrupt Mask Register (chid = 4) 0x158 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM5 Channel Interrupt Mask Register (chid = 5) 0x198 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM6 Channel Interrupt Mask Register (chid = 6) 0x1D8 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM7 Channel Interrupt Mask Register (chid = 7) 0x218 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM8 Channel Interrupt Mask Register (chid = 8) 0x258 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIM9 Channel Interrupt Mask Register (chid = 9) 0x298 32 write-only n BIM End of Block Interrupt Mask Bit 0 1 write-only DIM End of Disable Interrupt Mask Bit 2 1 write-only FIM End of Flush Interrupt Mask Bit 3 1 write-only LIM End of Linked List Interrupt Mask Bit 1 1 write-only RBEIM Read Bus Error Interrupt Mask Bit 4 1 write-only ROIM Request Overflow Error Interrupt Mask Bit 6 1 write-only WBEIM Write Bus Error Interrupt Mask Bit 5 1 write-only CIS0 Channel Interrupt Status Register (chid = 0) 0x5C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS1 Channel Interrupt Status Register (chid = 1) 0x9C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS10 Channel Interrupt Status Register (chid = 10) 0x2DC 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS11 Channel Interrupt Status Register (chid = 11) 0x31C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS12 Channel Interrupt Status Register (chid = 12) 0x35C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS13 Channel Interrupt Status Register (chid = 13) 0x39C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS14 Channel Interrupt Status Register (chid = 14) 0x3DC 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS15 Channel Interrupt Status Register (chid = 15) 0x41C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS16 Channel Interrupt Status Register (chid = 16) 0x45C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS17 Channel Interrupt Status Register (chid = 17) 0x49C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS18 Channel Interrupt Status Register (chid = 18) 0x4DC 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS19 Channel Interrupt Status Register (chid = 19) 0x51C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS2 Channel Interrupt Status Register (chid = 2) 0xDC 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS20 Channel Interrupt Status Register (chid = 20) 0x55C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS21 Channel Interrupt Status Register (chid = 21) 0x59C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS22 Channel Interrupt Status Register (chid = 22) 0x5DC 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS23 Channel Interrupt Status Register (chid = 23) 0x61C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS3 Channel Interrupt Status Register (chid = 3) 0x11C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS4 Channel Interrupt Status Register (chid = 4) 0x15C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS5 Channel Interrupt Status Register (chid = 5) 0x19C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS6 Channel Interrupt Status Register (chid = 6) 0x1DC 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS7 Channel Interrupt Status Register (chid = 7) 0x21C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS8 Channel Interrupt Status Register (chid = 8) 0x25C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CIS9 Channel Interrupt Status Register (chid = 9) 0x29C 32 read-only n 0x0 BIS End of Block Interrupt Status Bit 0 1 read-only DIS End of Disable Interrupt Status Bit 2 1 read-only FIS End of Flush Interrupt Status Bit 3 1 read-only LIS End of Linked List Interrupt Status Bit 1 1 read-only RBEIS Read Bus Error Interrupt Status Bit 4 1 read-only ROIS Request Overflow Error Interrupt Status Bit 6 1 read-only WBEIS Write Bus Error Interrupt Status Bit 5 1 read-only CNDA0 Channel Next Descriptor Address Register (chid = 0) 0x68 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA1 Channel Next Descriptor Address Register (chid = 1) 0xA8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA10 Channel Next Descriptor Address Register (chid = 10) 0x2E8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA11 Channel Next Descriptor Address Register (chid = 11) 0x328 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA12 Channel Next Descriptor Address Register (chid = 12) 0x368 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA13 Channel Next Descriptor Address Register (chid = 13) 0x3A8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA14 Channel Next Descriptor Address Register (chid = 14) 0x3E8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA15 Channel Next Descriptor Address Register (chid = 15) 0x428 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA16 Channel Next Descriptor Address Register (chid = 16) 0x468 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA17 Channel Next Descriptor Address Register (chid = 17) 0x4A8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA18 Channel Next Descriptor Address Register (chid = 18) 0x4E8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA19 Channel Next Descriptor Address Register (chid = 19) 0x528 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA2 Channel Next Descriptor Address Register (chid = 2) 0xE8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA20 Channel Next Descriptor Address Register (chid = 20) 0x568 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA21 Channel Next Descriptor Address Register (chid = 21) 0x5A8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA22 Channel Next Descriptor Address Register (chid = 22) 0x5E8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA23 Channel Next Descriptor Address Register (chid = 23) 0x628 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA3 Channel Next Descriptor Address Register (chid = 3) 0x128 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA4 Channel Next Descriptor Address Register (chid = 4) 0x168 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA5 Channel Next Descriptor Address Register (chid = 5) 0x1A8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA6 Channel Next Descriptor Address Register (chid = 6) 0x1E8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA7 Channel Next Descriptor Address Register (chid = 7) 0x228 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA8 Channel Next Descriptor Address Register (chid = 8) 0x268 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDA9 Channel Next Descriptor Address Register (chid = 9) 0x2A8 32 read-write n 0x0 NDA Channel x Next Descriptor Address 2 30 read-write NDAIF Channel x Next Descriptor Interface 0 1 read-write CNDC0 Channel Next Descriptor Control Register (chid = 0) 0x6C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC1 Channel Next Descriptor Control Register (chid = 1) 0xAC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC10 Channel Next Descriptor Control Register (chid = 10) 0x2EC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC11 Channel Next Descriptor Control Register (chid = 11) 0x32C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC12 Channel Next Descriptor Control Register (chid = 12) 0x36C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC13 Channel Next Descriptor Control Register (chid = 13) 0x3AC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC14 Channel Next Descriptor Control Register (chid = 14) 0x3EC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC15 Channel Next Descriptor Control Register (chid = 15) 0x42C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC16 Channel Next Descriptor Control Register (chid = 16) 0x46C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC17 Channel Next Descriptor Control Register (chid = 17) 0x4AC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC18 Channel Next Descriptor Control Register (chid = 18) 0x4EC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC19 Channel Next Descriptor Control Register (chid = 19) 0x52C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC2 Channel Next Descriptor Control Register (chid = 2) 0xEC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC20 Channel Next Descriptor Control Register (chid = 20) 0x56C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC21 Channel Next Descriptor Control Register (chid = 21) 0x5AC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC22 Channel Next Descriptor Control Register (chid = 22) 0x5EC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC23 Channel Next Descriptor Control Register (chid = 23) 0x62C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC3 Channel Next Descriptor Control Register (chid = 3) 0x12C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC4 Channel Next Descriptor Control Register (chid = 4) 0x16C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC5 Channel Next Descriptor Control Register (chid = 5) 0x1AC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC6 Channel Next Descriptor Control Register (chid = 6) 0x1EC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC7 Channel Next Descriptor Control Register (chid = 7) 0x22C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC8 Channel Next Descriptor Control Register (chid = 8) 0x26C 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CNDC9 Channel Next Descriptor Control Register (chid = 9) 0x2AC 32 read-write n 0x0 NDDUP Channel x Next Descriptor Destination Update 2 1 read-write DST_PARAMS_UNCHANGED Destination parameters remain unchanged. 0 DST_PARAMS_UPDATED Destination parameters are updated when the descriptor is retrieved. 1 NDE Channel x Next Descriptor Enable 0 1 read-write DSCR_FETCH_DIS Descriptor fetch is disabled. 0 DSCR_FETCH_EN Descriptor fetch is enabled. 1 NDSUP Channel x Next Descriptor Source Update 1 1 read-write SRC_PARAMS_UNCHANGED Source parameters remain unchanged. 0 SRC_PARAMS_UPDATED Source parameters are updated when the descriptor is retrieved. 1 NDVIEW Channel x Next Descriptor View 3 2 read-write NDV0 Next Descriptor View 0 0x0 NDV1 Next Descriptor View 1 0x1 NDV2 Next Descriptor View 2 0x2 NDV3 Next Descriptor View 3 0x3 CSA0 Channel Source Address Register (chid = 0) 0x60 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA1 Channel Source Address Register (chid = 1) 0xA0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA10 Channel Source Address Register (chid = 10) 0x2E0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA11 Channel Source Address Register (chid = 11) 0x320 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA12 Channel Source Address Register (chid = 12) 0x360 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA13 Channel Source Address Register (chid = 13) 0x3A0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA14 Channel Source Address Register (chid = 14) 0x3E0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA15 Channel Source Address Register (chid = 15) 0x420 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA16 Channel Source Address Register (chid = 16) 0x460 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA17 Channel Source Address Register (chid = 17) 0x4A0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA18 Channel Source Address Register (chid = 18) 0x4E0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA19 Channel Source Address Register (chid = 19) 0x520 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA2 Channel Source Address Register (chid = 2) 0xE0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA20 Channel Source Address Register (chid = 20) 0x560 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA21 Channel Source Address Register (chid = 21) 0x5A0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA22 Channel Source Address Register (chid = 22) 0x5E0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA23 Channel Source Address Register (chid = 23) 0x620 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA3 Channel Source Address Register (chid = 3) 0x120 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA4 Channel Source Address Register (chid = 4) 0x160 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA5 Channel Source Address Register (chid = 5) 0x1A0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA6 Channel Source Address Register (chid = 6) 0x1E0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA7 Channel Source Address Register (chid = 7) 0x220 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA8 Channel Source Address Register (chid = 8) 0x260 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSA9 Channel Source Address Register (chid = 9) 0x2A0 32 read-write n 0x0 SA Channel x Source Address 0 32 read-write CSUS0 Channel Source Microblock Stride (chid = 0) 0x80 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS1 Channel Source Microblock Stride (chid = 1) 0xC0 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS10 Channel Source Microblock Stride (chid = 10) 0x300 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS11 Channel Source Microblock Stride (chid = 11) 0x340 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS12 Channel Source Microblock Stride (chid = 12) 0x380 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS13 Channel Source Microblock Stride (chid = 13) 0x3C0 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS14 Channel Source Microblock Stride (chid = 14) 0x400 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS15 Channel Source Microblock Stride (chid = 15) 0x440 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS16 Channel Source Microblock Stride (chid = 16) 0x480 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS17 Channel Source Microblock Stride (chid = 17) 0x4C0 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS18 Channel Source Microblock Stride (chid = 18) 0x500 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS19 Channel Source Microblock Stride (chid = 19) 0x540 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS2 Channel Source Microblock Stride (chid = 2) 0x100 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS20 Channel Source Microblock Stride (chid = 20) 0x580 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS21 Channel Source Microblock Stride (chid = 21) 0x5C0 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS22 Channel Source Microblock Stride (chid = 22) 0x600 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS23 Channel Source Microblock Stride (chid = 23) 0x640 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS3 Channel Source Microblock Stride (chid = 3) 0x140 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS4 Channel Source Microblock Stride (chid = 4) 0x180 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS5 Channel Source Microblock Stride (chid = 5) 0x1C0 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS6 Channel Source Microblock Stride (chid = 6) 0x200 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS7 Channel Source Microblock Stride (chid = 7) 0x240 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS8 Channel Source Microblock Stride (chid = 8) 0x280 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CSUS9 Channel Source Microblock Stride (chid = 9) 0x2C0 32 read-write n 0x0 SUBS Channel x Source Microblock Stride 0 24 read-write CUBC0 Channel Microblock Control Register (chid = 0) 0x70 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC1 Channel Microblock Control Register (chid = 1) 0xB0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC10 Channel Microblock Control Register (chid = 10) 0x2F0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC11 Channel Microblock Control Register (chid = 11) 0x330 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC12 Channel Microblock Control Register (chid = 12) 0x370 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC13 Channel Microblock Control Register (chid = 13) 0x3B0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC14 Channel Microblock Control Register (chid = 14) 0x3F0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC15 Channel Microblock Control Register (chid = 15) 0x430 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC16 Channel Microblock Control Register (chid = 16) 0x470 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC17 Channel Microblock Control Register (chid = 17) 0x4B0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC18 Channel Microblock Control Register (chid = 18) 0x4F0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC19 Channel Microblock Control Register (chid = 19) 0x530 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC2 Channel Microblock Control Register (chid = 2) 0xF0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC20 Channel Microblock Control Register (chid = 20) 0x570 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC21 Channel Microblock Control Register (chid = 21) 0x5B0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC22 Channel Microblock Control Register (chid = 22) 0x5F0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC23 Channel Microblock Control Register (chid = 23) 0x630 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC3 Channel Microblock Control Register (chid = 3) 0x130 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC4 Channel Microblock Control Register (chid = 4) 0x170 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC5 Channel Microblock Control Register (chid = 5) 0x1B0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC6 Channel Microblock Control Register (chid = 6) 0x1F0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC7 Channel Microblock Control Register (chid = 7) 0x230 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC8 Channel Microblock Control Register (chid = 8) 0x270 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write CUBC9 Channel Microblock Control Register (chid = 9) 0x2B0 32 read-write n 0x0 UBLEN Channel x Microblock Length 0 24 read-write GCFG Global Configuration Register 0x4 32 read-write n 0x0 0x0 BXKBEN Boundary X Kilobyte Enable 8 1 CGDISFIFO FIFO Clock Gating Disable 2 1 CGDISIF Bus Interface Clock Gating Disable 3 1 CGDISPIPE Pipeline Clock Gating Disable 1 1 CGDISREG Configuration Registers Clock Gating Disable 0 1 GD Global Channel Disable Register 0x20 32 write-only n 0x0 0x0 DI0 XDMAC Channel 0 Disable Bit 0 1 DI1 XDMAC Channel 1 Disable Bit 1 1 DI10 XDMAC Channel 10 Disable Bit 10 1 DI11 XDMAC Channel 11 Disable Bit 11 1 DI12 XDMAC Channel 12 Disable Bit 12 1 DI13 XDMAC Channel 13 Disable Bit 13 1 DI14 XDMAC Channel 14 Disable Bit 14 1 DI15 XDMAC Channel 15 Disable Bit 15 1 DI16 XDMAC Channel 16 Disable Bit 16 1 DI17 XDMAC Channel 17 Disable Bit 17 1 DI18 XDMAC Channel 18 Disable Bit 18 1 DI19 XDMAC Channel 19 Disable Bit 19 1 DI2 XDMAC Channel 2 Disable Bit 2 1 DI20 XDMAC Channel 20 Disable Bit 20 1 DI21 XDMAC Channel 21 Disable Bit 21 1 DI22 XDMAC Channel 22 Disable Bit 22 1 DI23 XDMAC Channel 23 Disable Bit 23 1 DI3 XDMAC Channel 3 Disable Bit 3 1 DI4 XDMAC Channel 4 Disable Bit 4 1 DI5 XDMAC Channel 5 Disable Bit 5 1 DI6 XDMAC Channel 6 Disable Bit 6 1 DI7 XDMAC Channel 7 Disable Bit 7 1 DI8 XDMAC Channel 8 Disable Bit 8 1 DI9 XDMAC Channel 9 Disable Bit 9 1 GE Global Channel Enable Register 0x1C 32 write-only n 0x0 0x0 EN0 XDMAC Channel 0 Enable Bit 0 1 EN1 XDMAC Channel 1 Enable Bit 1 1 EN10 XDMAC Channel 10 Enable Bit 10 1 EN11 XDMAC Channel 11 Enable Bit 11 1 EN12 XDMAC Channel 12 Enable Bit 12 1 EN13 XDMAC Channel 13 Enable Bit 13 1 EN14 XDMAC Channel 14 Enable Bit 14 1 EN15 XDMAC Channel 15 Enable Bit 15 1 EN16 XDMAC Channel 16 Enable Bit 16 1 EN17 XDMAC Channel 17 Enable Bit 17 1 EN18 XDMAC Channel 18 Enable Bit 18 1 EN19 XDMAC Channel 19 Enable Bit 19 1 EN2 XDMAC Channel 2 Enable Bit 2 1 EN20 XDMAC Channel 20 Enable Bit 20 1 EN21 XDMAC Channel 21 Enable Bit 21 1 EN22 XDMAC Channel 22 Enable Bit 22 1 EN23 XDMAC Channel 23 Enable Bit 23 1 EN3 XDMAC Channel 3 Enable Bit 3 1 EN4 XDMAC Channel 4 Enable Bit 4 1 EN5 XDMAC Channel 5 Enable Bit 5 1 EN6 XDMAC Channel 6 Enable Bit 6 1 EN7 XDMAC Channel 7 Enable Bit 7 1 EN8 XDMAC Channel 8 Enable Bit 8 1 EN9 XDMAC Channel 9 Enable Bit 9 1 GID Global Interrupt Disable Register 0x10 32 write-only n 0x0 0x0 ID0 XDMAC Channel 0 Interrupt Disable Bit 0 1 ID1 XDMAC Channel 1 Interrupt Disable Bit 1 1 ID10 XDMAC Channel 10 Interrupt Disable Bit 10 1 ID11 XDMAC Channel 11 Interrupt Disable Bit 11 1 ID12 XDMAC Channel 12 Interrupt Disable Bit 12 1 ID13 XDMAC Channel 13 Interrupt Disable Bit 13 1 ID14 XDMAC Channel 14 Interrupt Disable Bit 14 1 ID15 XDMAC Channel 15 Interrupt Disable Bit 15 1 ID16 XDMAC Channel 16 Interrupt Disable Bit 16 1 ID17 XDMAC Channel 17 Interrupt Disable Bit 17 1 ID18 XDMAC Channel 18 Interrupt Disable Bit 18 1 ID19 XDMAC Channel 19 Interrupt Disable Bit 19 1 ID2 XDMAC Channel 2 Interrupt Disable Bit 2 1 ID20 XDMAC Channel 20 Interrupt Disable Bit 20 1 ID21 XDMAC Channel 21 Interrupt Disable Bit 21 1 ID22 XDMAC Channel 22 Interrupt Disable Bit 22 1 ID23 XDMAC Channel 23 Interrupt Disable Bit 23 1 ID3 XDMAC Channel 3 Interrupt Disable Bit 3 1 ID4 XDMAC Channel 4 Interrupt Disable Bit 4 1 ID5 XDMAC Channel 5 Interrupt Disable Bit 5 1 ID6 XDMAC Channel 6 Interrupt Disable Bit 6 1 ID7 XDMAC Channel 7 Interrupt Disable Bit 7 1 ID8 XDMAC Channel 8 Interrupt Disable Bit 8 1 ID9 XDMAC Channel 9 Interrupt Disable Bit 9 1 GIE Global Interrupt Enable Register 0xC 32 write-only n 0x0 0x0 IE0 XDMAC Channel 0 Interrupt Enable Bit 0 1 IE1 XDMAC Channel 1 Interrupt Enable Bit 1 1 IE10 XDMAC Channel 10 Interrupt Enable Bit 10 1 IE11 XDMAC Channel 11 Interrupt Enable Bit 11 1 IE12 XDMAC Channel 12 Interrupt Enable Bit 12 1 IE13 XDMAC Channel 13 Interrupt Enable Bit 13 1 IE14 XDMAC Channel 14 Interrupt Enable Bit 14 1 IE15 XDMAC Channel 15 Interrupt Enable Bit 15 1 IE16 XDMAC Channel 16 Interrupt Enable Bit 16 1 IE17 XDMAC Channel 17 Interrupt Enable Bit 17 1 IE18 XDMAC Channel 18 Interrupt Enable Bit 18 1 IE19 XDMAC Channel 19 Interrupt Enable Bit 19 1 IE2 XDMAC Channel 2 Interrupt Enable Bit 2 1 IE20 XDMAC Channel 20 Interrupt Enable Bit 20 1 IE21 XDMAC Channel 21 Interrupt Enable Bit 21 1 IE22 XDMAC Channel 22 Interrupt Enable Bit 22 1 IE23 XDMAC Channel 23 Interrupt Enable Bit 23 1 IE3 XDMAC Channel 3 Interrupt Enable Bit 3 1 IE4 XDMAC Channel 4 Interrupt Enable Bit 4 1 IE5 XDMAC Channel 5 Interrupt Enable Bit 5 1 IE6 XDMAC Channel 6 Interrupt Enable Bit 6 1 IE7 XDMAC Channel 7 Interrupt Enable Bit 7 1 IE8 XDMAC Channel 8 Interrupt Enable Bit 8 1 IE9 XDMAC Channel 9 Interrupt Enable Bit 9 1 GIM Global Interrupt Mask Register 0x14 32 read-only n 0x0 0x0 IM0 XDMAC Channel 0 Interrupt Mask Bit 0 1 IM1 XDMAC Channel 1 Interrupt Mask Bit 1 1 IM10 XDMAC Channel 10 Interrupt Mask Bit 10 1 IM11 XDMAC Channel 11 Interrupt Mask Bit 11 1 IM12 XDMAC Channel 12 Interrupt Mask Bit 12 1 IM13 XDMAC Channel 13 Interrupt Mask Bit 13 1 IM14 XDMAC Channel 14 Interrupt Mask Bit 14 1 IM15 XDMAC Channel 15 Interrupt Mask Bit 15 1 IM16 XDMAC Channel 16 Interrupt Mask Bit 16 1 IM17 XDMAC Channel 17 Interrupt Mask Bit 17 1 IM18 XDMAC Channel 18 Interrupt Mask Bit 18 1 IM19 XDMAC Channel 19 Interrupt Mask Bit 19 1 IM2 XDMAC Channel 2 Interrupt Mask Bit 2 1 IM20 XDMAC Channel 20 Interrupt Mask Bit 20 1 IM21 XDMAC Channel 21 Interrupt Mask Bit 21 1 IM22 XDMAC Channel 22 Interrupt Mask Bit 22 1 IM23 XDMAC Channel 23 Interrupt Mask Bit 23 1 IM3 XDMAC Channel 3 Interrupt Mask Bit 3 1 IM4 XDMAC Channel 4 Interrupt Mask Bit 4 1 IM5 XDMAC Channel 5 Interrupt Mask Bit 5 1 IM6 XDMAC Channel 6 Interrupt Mask Bit 6 1 IM7 XDMAC Channel 7 Interrupt Mask Bit 7 1 IM8 XDMAC Channel 8 Interrupt Mask Bit 8 1 IM9 XDMAC Channel 9 Interrupt Mask Bit 9 1 GIS Global Interrupt Status Register 0x18 32 read-only n 0x0 0x0 IS0 XDMAC Channel 0 Interrupt Status Bit 0 1 IS1 XDMAC Channel 1 Interrupt Status Bit 1 1 IS10 XDMAC Channel 10 Interrupt Status Bit 10 1 IS11 XDMAC Channel 11 Interrupt Status Bit 11 1 IS12 XDMAC Channel 12 Interrupt Status Bit 12 1 IS13 XDMAC Channel 13 Interrupt Status Bit 13 1 IS14 XDMAC Channel 14 Interrupt Status Bit 14 1 IS15 XDMAC Channel 15 Interrupt Status Bit 15 1 IS16 XDMAC Channel 16 Interrupt Status Bit 16 1 IS17 XDMAC Channel 17 Interrupt Status Bit 17 1 IS18 XDMAC Channel 18 Interrupt Status Bit 18 1 IS19 XDMAC Channel 19 Interrupt Status Bit 19 1 IS2 XDMAC Channel 2 Interrupt Status Bit 2 1 IS20 XDMAC Channel 20 Interrupt Status Bit 20 1 IS21 XDMAC Channel 21 Interrupt Status Bit 21 1 IS22 XDMAC Channel 22 Interrupt Status Bit 22 1 IS23 XDMAC Channel 23 Interrupt Status Bit 23 1 IS3 XDMAC Channel 3 Interrupt Status Bit 3 1 IS4 XDMAC Channel 4 Interrupt Status Bit 4 1 IS5 XDMAC Channel 5 Interrupt Status Bit 5 1 IS6 XDMAC Channel 6 Interrupt Status Bit 6 1 IS7 XDMAC Channel 7 Interrupt Status Bit 7 1 IS8 XDMAC Channel 8 Interrupt Status Bit 8 1 IS9 XDMAC Channel 9 Interrupt Status Bit 9 1 GRS Global Channel Read Suspend Register 0x28 32 read-write n 0x0 0x0 RS0 XDMAC Channel 0 Read Suspend Bit 0 1 RS1 XDMAC Channel 1 Read Suspend Bit 1 1 RS10 XDMAC Channel 10 Read Suspend Bit 10 1 RS11 XDMAC Channel 11 Read Suspend Bit 11 1 RS12 XDMAC Channel 12 Read Suspend Bit 12 1 RS13 XDMAC Channel 13 Read Suspend Bit 13 1 RS14 XDMAC Channel 14 Read Suspend Bit 14 1 RS15 XDMAC Channel 15 Read Suspend Bit 15 1 RS16 XDMAC Channel 16 Read Suspend Bit 16 1 RS17 XDMAC Channel 17 Read Suspend Bit 17 1 RS18 XDMAC Channel 18 Read Suspend Bit 18 1 RS19 XDMAC Channel 19 Read Suspend Bit 19 1 RS2 XDMAC Channel 2 Read Suspend Bit 2 1 RS20 XDMAC Channel 20 Read Suspend Bit 20 1 RS21 XDMAC Channel 21 Read Suspend Bit 21 1 RS22 XDMAC Channel 22 Read Suspend Bit 22 1 RS23 XDMAC Channel 23 Read Suspend Bit 23 1 RS3 XDMAC Channel 3 Read Suspend Bit 3 1 RS4 XDMAC Channel 4 Read Suspend Bit 4 1 RS5 XDMAC Channel 5 Read Suspend Bit 5 1 RS6 XDMAC Channel 6 Read Suspend Bit 6 1 RS7 XDMAC Channel 7 Read Suspend Bit 7 1 RS8 XDMAC Channel 8 Read Suspend Bit 8 1 RS9 XDMAC Channel 9 Read Suspend Bit 9 1 GRWR Global Channel Read Write Resume Register 0x34 32 write-only n 0x0 0x0 RWR0 XDMAC Channel 0 Read Write Resume Bit 0 1 RWR1 XDMAC Channel 1 Read Write Resume Bit 1 1 RWR10 XDMAC Channel 10 Read Write Resume Bit 10 1 RWR11 XDMAC Channel 11 Read Write Resume Bit 11 1 RWR12 XDMAC Channel 12 Read Write Resume Bit 12 1 RWR13 XDMAC Channel 13 Read Write Resume Bit 13 1 RWR14 XDMAC Channel 14 Read Write Resume Bit 14 1 RWR15 XDMAC Channel 15 Read Write Resume Bit 15 1 RWR16 XDMAC Channel 16 Read Write Resume Bit 16 1 RWR17 XDMAC Channel 17 Read Write Resume Bit 17 1 RWR18 XDMAC Channel 18 Read Write Resume Bit 18 1 RWR19 XDMAC Channel 19 Read Write Resume Bit 19 1 RWR2 XDMAC Channel 2 Read Write Resume Bit 2 1 RWR20 XDMAC Channel 20 Read Write Resume Bit 20 1 RWR21 XDMAC Channel 21 Read Write Resume Bit 21 1 RWR22 XDMAC Channel 22 Read Write Resume Bit 22 1 RWR23 XDMAC Channel 23 Read Write Resume Bit 23 1 RWR3 XDMAC Channel 3 Read Write Resume Bit 3 1 RWR4 XDMAC Channel 4 Read Write Resume Bit 4 1 RWR5 XDMAC Channel 5 Read Write Resume Bit 5 1 RWR6 XDMAC Channel 6 Read Write Resume Bit 6 1 RWR7 XDMAC Channel 7 Read Write Resume Bit 7 1 RWR8 XDMAC Channel 8 Read Write Resume Bit 8 1 RWR9 XDMAC Channel 9 Read Write Resume Bit 9 1 GRWS Global Channel Read Write Suspend Register 0x30 32 write-only n 0x0 0x0 RWS0 XDMAC Channel 0 Read Write Suspend Bit 0 1 RWS1 XDMAC Channel 1 Read Write Suspend Bit 1 1 RWS10 XDMAC Channel 10 Read Write Suspend Bit 10 1 RWS11 XDMAC Channel 11 Read Write Suspend Bit 11 1 RWS12 XDMAC Channel 12 Read Write Suspend Bit 12 1 RWS13 XDMAC Channel 13 Read Write Suspend Bit 13 1 RWS14 XDMAC Channel 14 Read Write Suspend Bit 14 1 RWS15 XDMAC Channel 15 Read Write Suspend Bit 15 1 RWS16 XDMAC Channel 16 Read Write Suspend Bit 16 1 RWS17 XDMAC Channel 17 Read Write Suspend Bit 17 1 RWS18 XDMAC Channel 18 Read Write Suspend Bit 18 1 RWS19 XDMAC Channel 19 Read Write Suspend Bit 19 1 RWS2 XDMAC Channel 2 Read Write Suspend Bit 2 1 RWS20 XDMAC Channel 20 Read Write Suspend Bit 20 1 RWS21 XDMAC Channel 21 Read Write Suspend Bit 21 1 RWS22 XDMAC Channel 22 Read Write Suspend Bit 22 1 RWS23 XDMAC Channel 23 Read Write Suspend Bit 23 1 RWS3 XDMAC Channel 3 Read Write Suspend Bit 3 1 RWS4 XDMAC Channel 4 Read Write Suspend Bit 4 1 RWS5 XDMAC Channel 5 Read Write Suspend Bit 5 1 RWS6 XDMAC Channel 6 Read Write Suspend Bit 6 1 RWS7 XDMAC Channel 7 Read Write Suspend Bit 7 1 RWS8 XDMAC Channel 8 Read Write Suspend Bit 8 1 RWS9 XDMAC Channel 9 Read Write Suspend Bit 9 1 GS Global Channel Status Register 0x24 32 read-only n 0x0 0x0 ST0 XDMAC Channel 0 Status Bit 0 1 ST1 XDMAC Channel 1 Status Bit 1 1 ST10 XDMAC Channel 10 Status Bit 10 1 ST11 XDMAC Channel 11 Status Bit 11 1 ST12 XDMAC Channel 12 Status Bit 12 1 ST13 XDMAC Channel 13 Status Bit 13 1 ST14 XDMAC Channel 14 Status Bit 14 1 ST15 XDMAC Channel 15 Status Bit 15 1 ST16 XDMAC Channel 16 Status Bit 16 1 ST17 XDMAC Channel 17 Status Bit 17 1 ST18 XDMAC Channel 18 Status Bit 18 1 ST19 XDMAC Channel 19 Status Bit 19 1 ST2 XDMAC Channel 2 Status Bit 2 1 ST20 XDMAC Channel 20 Status Bit 20 1 ST21 XDMAC Channel 21 Status Bit 21 1 ST22 XDMAC Channel 22 Status Bit 22 1 ST23 XDMAC Channel 23 Status Bit 23 1 ST3 XDMAC Channel 3 Status Bit 3 1 ST4 XDMAC Channel 4 Status Bit 4 1 ST5 XDMAC Channel 5 Status Bit 5 1 ST6 XDMAC Channel 6 Status Bit 6 1 ST7 XDMAC Channel 7 Status Bit 7 1 ST8 XDMAC Channel 8 Status Bit 8 1 ST9 XDMAC Channel 9 Status Bit 9 1 GSWF Global Channel Software Flush Request Register 0x40 32 write-only n 0x0 0x0 SWF0 XDMAC Channel 0 Software Flush Request Bit 0 1 SWF1 XDMAC Channel 1 Software Flush Request Bit 1 1 SWF10 XDMAC Channel 10 Software Flush Request Bit 10 1 SWF11 XDMAC Channel 11 Software Flush Request Bit 11 1 SWF12 XDMAC Channel 12 Software Flush Request Bit 12 1 SWF13 XDMAC Channel 13 Software Flush Request Bit 13 1 SWF14 XDMAC Channel 14 Software Flush Request Bit 14 1 SWF15 XDMAC Channel 15 Software Flush Request Bit 15 1 SWF16 XDMAC Channel 16 Software Flush Request Bit 16 1 SWF17 XDMAC Channel 17 Software Flush Request Bit 17 1 SWF18 XDMAC Channel 18 Software Flush Request Bit 18 1 SWF19 XDMAC Channel 19 Software Flush Request Bit 19 1 SWF2 XDMAC Channel 2 Software Flush Request Bit 2 1 SWF20 XDMAC Channel 20 Software Flush Request Bit 20 1 SWF21 XDMAC Channel 21 Software Flush Request Bit 21 1 SWF22 XDMAC Channel 22 Software Flush Request Bit 22 1 SWF23 XDMAC Channel 23 Software Flush Request Bit 23 1 SWF3 XDMAC Channel 3 Software Flush Request Bit 3 1 SWF4 XDMAC Channel 4 Software Flush Request Bit 4 1 SWF5 XDMAC Channel 5 Software Flush Request Bit 5 1 SWF6 XDMAC Channel 6 Software Flush Request Bit 6 1 SWF7 XDMAC Channel 7 Software Flush Request Bit 7 1 SWF8 XDMAC Channel 8 Software Flush Request Bit 8 1 SWF9 XDMAC Channel 9 Software Flush Request Bit 9 1 GSWR Global Channel Software Request Register 0x38 32 write-only n 0x0 0x0 SWREQ0 XDMAC Channel 0 Software Request Bit 0 1 SWREQ1 XDMAC Channel 1 Software Request Bit 1 1 SWREQ10 XDMAC Channel 10 Software Request Bit 10 1 SWREQ11 XDMAC Channel 11 Software Request Bit 11 1 SWREQ12 XDMAC Channel 12 Software Request Bit 12 1 SWREQ13 XDMAC Channel 13 Software Request Bit 13 1 SWREQ14 XDMAC Channel 14 Software Request Bit 14 1 SWREQ15 XDMAC Channel 15 Software Request Bit 15 1 SWREQ16 XDMAC Channel 16 Software Request Bit 16 1 SWREQ17 XDMAC Channel 17 Software Request Bit 17 1 SWREQ18 XDMAC Channel 18 Software Request Bit 18 1 SWREQ19 XDMAC Channel 19 Software Request Bit 19 1 SWREQ2 XDMAC Channel 2 Software Request Bit 2 1 SWREQ20 XDMAC Channel 20 Software Request Bit 20 1 SWREQ21 XDMAC Channel 21 Software Request Bit 21 1 SWREQ22 XDMAC Channel 22 Software Request Bit 22 1 SWREQ23 XDMAC Channel 23 Software Request Bit 23 1 SWREQ3 XDMAC Channel 3 Software Request Bit 3 1 SWREQ4 XDMAC Channel 4 Software Request Bit 4 1 SWREQ5 XDMAC Channel 5 Software Request Bit 5 1 SWREQ6 XDMAC Channel 6 Software Request Bit 6 1 SWREQ7 XDMAC Channel 7 Software Request Bit 7 1 SWREQ8 XDMAC Channel 8 Software Request Bit 8 1 SWREQ9 XDMAC Channel 9 Software Request Bit 9 1 GSWS Global Channel Software Request Status Register 0x3C 32 read-only n 0x0 0x0 SWRS0 XDMAC Channel 0 Software Request Status Bit 0 1 SWRS1 XDMAC Channel 1 Software Request Status Bit 1 1 SWRS10 XDMAC Channel 10 Software Request Status Bit 10 1 SWRS11 XDMAC Channel 11 Software Request Status Bit 11 1 SWRS12 XDMAC Channel 12 Software Request Status Bit 12 1 SWRS13 XDMAC Channel 13 Software Request Status Bit 13 1 SWRS14 XDMAC Channel 14 Software Request Status Bit 14 1 SWRS15 XDMAC Channel 15 Software Request Status Bit 15 1 SWRS16 XDMAC Channel 16 Software Request Status Bit 16 1 SWRS17 XDMAC Channel 17 Software Request Status Bit 17 1 SWRS18 XDMAC Channel 18 Software Request Status Bit 18 1 SWRS19 XDMAC Channel 19 Software Request Status Bit 19 1 SWRS2 XDMAC Channel 2 Software Request Status Bit 2 1 SWRS20 XDMAC Channel 20 Software Request Status Bit 20 1 SWRS21 XDMAC Channel 21 Software Request Status Bit 21 1 SWRS22 XDMAC Channel 22 Software Request Status Bit 22 1 SWRS23 XDMAC Channel 23 Software Request Status Bit 23 1 SWRS3 XDMAC Channel 3 Software Request Status Bit 3 1 SWRS4 XDMAC Channel 4 Software Request Status Bit 4 1 SWRS5 XDMAC Channel 5 Software Request Status Bit 5 1 SWRS6 XDMAC Channel 6 Software Request Status Bit 6 1 SWRS7 XDMAC Channel 7 Software Request Status Bit 7 1 SWRS8 XDMAC Channel 8 Software Request Status Bit 8 1 SWRS9 XDMAC Channel 9 Software Request Status Bit 9 1 GTYPE Global Type Register 0x0 32 read-only n 0x0 0x0 FIFO_SZ Number of Bytes 5 11 NB_CH Number of Channels Minus One 0 5 NB_REQ Number of Peripheral Requests Minus One 16 7 GWAC Global Weighted Arbiter Configuration Register 0x8 32 read-write n 0x0 0x0 PW0 Pool Weight 0 0 4 PW1 Pool Weight 1 4 4 PW2 Pool Weight 2 8 4 PW3 Pool Weight 3 12 4 GWS Global Channel Write Suspend Register 0x2C 32 read-write n 0x0 0x0 WS0 XDMAC Channel 0 Write Suspend Bit 0 1 WS1 XDMAC Channel 1 Write Suspend Bit 1 1 WS10 XDMAC Channel 10 Write Suspend Bit 10 1 WS11 XDMAC Channel 11 Write Suspend Bit 11 1 WS12 XDMAC Channel 12 Write Suspend Bit 12 1 WS13 XDMAC Channel 13 Write Suspend Bit 13 1 WS14 XDMAC Channel 14 Write Suspend Bit 14 1 WS15 XDMAC Channel 15 Write Suspend Bit 15 1 WS16 XDMAC Channel 16 Write Suspend Bit 16 1 WS17 XDMAC Channel 17 Write Suspend Bit 17 1 WS18 XDMAC Channel 18 Write Suspend Bit 18 1 WS19 XDMAC Channel 19 Write Suspend Bit 19 1 WS2 XDMAC Channel 2 Write Suspend Bit 2 1 WS20 XDMAC Channel 20 Write Suspend Bit 20 1 WS21 XDMAC Channel 21 Write Suspend Bit 21 1 WS22 XDMAC Channel 22 Write Suspend Bit 22 1 WS23 XDMAC Channel 23 Write Suspend Bit 23 1 WS3 XDMAC Channel 3 Write Suspend Bit 3 1 WS4 XDMAC Channel 4 Write Suspend Bit 4 1 WS5 XDMAC Channel 5 Write Suspend Bit 5 1 WS6 XDMAC Channel 6 Write Suspend Bit 6 1 WS7 XDMAC Channel 7 Write Suspend Bit 7 1 WS8 XDMAC Channel 8 Write Suspend Bit 8 1 WS9 XDMAC Channel 9 Write Suspend Bit 9 1